DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1991
INTEGRATED CIRCUITS
74HC/HCT594
8-bit shift register with output
register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1991
2
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
FEATURES
Synchronous serial input and output
8-bit parallel output
Shift and storage register have independent direct clear
and clocks
100 MHz (typ.)
Output capability:
parallel outputs: bus driver
serial outputs: standard
I
CC
category: MSI
APPLICATIONS
Serial-to parallel data conversion
Remote control holding register
DESCRIPTION
The 74HC/HCT594 are high-speed, Si-gate CMOS
devices, and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC/HCT594 contain an 8-bit, non-inverting,
serial-in, parallel-out shift register that feeds an 8-bit
D-type storage register. Separate clocks and direct
overriding clears are provided on both the shift and storage
registers. A serial output (Q
7
') is provided for cascading
purposes.
Both the shift and storage register clocks are positive-edge
triggered. If the user wishes to connect both clocks
together, the shift register will always be one count pulse
ahead of the storage register.
QUICK REFERENCE DATA
GND = 0 V: T
amb
= 250 C; t
r
= t
f
= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
), where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of the outputs;
C
L
= output load capacitance in pF; V
CC
= supply voltage in V.
2. For HC, the condition is V
I
= GND to V
CC
; for HCT, the condition is V
I
= GND to V
CC
-
1.5 V.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
SH
CP
to Q
7
'
13
15
ns
ST
CP
to Q
n
13
15
ns
SH
R
to Q
n
11
14
ns
ST
R
to Q
n
11
14
ns
f
max
maximum clock frequency SH
CP
, ST
CP
100
100
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
84
89
pF
EXTENDED TYPE NUMBER
PACKAGES
PINS
PIN POSITION
MATERIAL
CODE
PC74HC/HCT594P
16
DIL
plastic
SOT38C, P
PC74HC/HCT594T
16
SO
plastic
SOT109A
December 1991
3
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
PINNING
SYMBOL
PIN
DESCRIPTION
Q
0
to Q
7
15 & 1 to 7
parallel data outputs
GND
8
ground (0 V)
Q
7
'
9
serial data output
SH
R
10
shift register reset (active LOW)
SH
CP
11
shift register clock input
ST
CP
12
storage register clock input
ST
R
13
storage register reset active (LOW)
D
s
14
serial data input
V
CC
16
supply voltage
Fig.1 Logic symbol.
ge
MBC319
SH CP STCP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SH R ST R
D S
14
10
13
11
12
15
9
1
2
3
4
5
6
7
Q7'
Fig.2 Pin configuration.
ge
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
594
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
Q 0
GND
SH R
SH CP
ST CP
ST R
D S
VCC
MBC318
Fig.3 IEC logic symbol.
halfpage
MBC322 - 1
SH CP
ST CP
Q0
Q1
Q2
Q3
Q4
Q5
Q 6
Q 7
SH R
ST R
DS
15
9
1
2
3
4
5
6
7
1D
2D
C1/
10
11
14
C2
12
13
2
R
SRG8
R 1
Q7'
December 1991
4
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
= LOW-to-HIGH transition
NC = no change
X = don't care.
INPUTS
OUTPUTS
FUNCTION
SH
CP
ST
CP
SH
R
ST
R
D
S
Q
7
'
Q
n
X
X
L
X
X
L
NC
a LOW level on SH
R
only affects the shift registers.
X
X
X
L
X
NC
L
a LOW level on ST
R
only affects the storage registers.
X
L
H
X
L
L
empty shift register loaded into storage register.
X
H
X
H
Q
6
'
NC
logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage
6 (internal Q
6
') appears on the serial output (Q
7
').
X
H
H
X
NC
Q
n
'
contents of shift register stages (internal Q
n
') are transferred to
the storage register and parallel output stages.
H
H
X
Q
6
n
Q
n
'
contents of shift register shifted through. Previous contents of
shift register transferred to the storage register and the parallel
output stages.
Fig.4 Functional diagram.
handbook, halfpage
MBC320
SHCP
STCP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SH R
ST R
D S
14
10
13
11
12
15
9
1
2
3
4
5
6
7
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
Q7'
December 1991
5
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
Fig.5 Logic diagram.
handbook, full pagewidth
MBC321 - 1
SHCP
ST CP
Q0
Q1 Q2 Q3 Q4 Q5 Q6
SH R
ST R
D S
D
Q
CP
FFSH0
R
STAGE 0
D
Q
CP
FFST 0
R
STAGES 1 TO
6
D
Q
Q7
D
Q
CP
FFSH7
R
STAGE 7
D
Q
CP
FFST 7
R
Q7'
Fig.6 Timing diagram.
handbook, full pagewidth
MBC323 - 1
SH CP
STCP
Q '
7
Q0
Q1
Q6
Q7
SH R
ST R
D S
PDF 
ZIP