DATA SHEET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT7731
Quad 64-bit static shift register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993
2
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
FEATURES
Frequency range DC to 100 MHz.
Separate serial data inputs
Cascadable
Functionally compatible with
HEF 4731
Includes recycling mode
Direct shift out
Output capability: Standard
I
CC
category: LSI.
APPLICATIONS
Data storage
Delay line.
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs D
a
to D
d
, clock inputs CP
a
to CP
d
and data outputs Q
a
to Q
d
.
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
REC
ab
for registers A and B and
REC
cd
for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= (C
PD
x V
CC
2
x f
i
) + (C
L
+ V
CC
2
x f
o
) + (I
pull-up
x V
CC
)
where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
V
CC
= supply voltage in V.
C
L
= output load capacitance in pF.
I
pull-up
= pull-up currents in
A.
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay
CP
a-d
to Q
a-d
C
L
= 15 pF;
V
CC
= 5 V
15
20
ns
f
max
maximum clock
frequency
100
100
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation
capacitance per register
notes 1, 2
and 3
58
61
pF
EXTENDED TYPE
NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
74HC/HCT7731N
16
DIL
plastic
SOT38Z
74HC/HCT7731D
16
SO16
plastic
SOT109A
September 1993
5
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: LSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
Note
1. The maximum power dissipation has to be observed. See power dissipation information.
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITION
+
25
-
40 to
+
85
-
40 to
+
125
V
CC
(V)
WAVEFORMS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
PHL
/t
PLH
propagation
delay time CP
to Q
n
-
-
-
50
18
15
155
31
26
-
-
-
190
38
32
-
-
-
230
46
39
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
THL
/t
TLH
output transition
time
-
-
-
19
7
6
75
15
13
-
-
-
90
18
15
-
-
-
110
22
19
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
W
clock pulse
width
HIGH or LOW
80
16
14
19
7
6
-
-
-
100
20
17
-
-
-
120
24
20
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
su
set-up time D
n
to CP
n
60
12
10
8
3
3
-
-
-
75
15
13
-
-
-
90
18
15
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
su
set-up time
REC
n
to CP
n
75
15
13
22
8
7
-
-
-
90
18
15
-
-
-
110
22
19
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.5
t
h
hold time D
n
to
CP
n
25
5
4
-
3
-
1
-
1
-
-
-
30
6
5
-
-
-
35
7
6
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.4
t
h
hold time REC
n
to CP
n
10
2
2
-
8
-
3
-
3
-
-
-
10
2
2
-
-
-
15
3
3
-
-
-
ns
ns
ns
2.0
4.5
6.0
Fig.5
f
max
maximum clock
pulse frequency
6
30
35
26
78
93
-
-
-
4.8
24
28
-
-
-
4
20
23
-
-
-
MHz
MHZ
MHz
2.0
4.5
6.0
Fig.4 (note 1)
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