DATA SHEET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
INTEGRATED CIRCUITS
74HC/HCT174
Hex D-type flip-flop with reset;
positive-edge trigger
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Jul 08
2
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
FEATURES
Six edge-triggered D-type flip-flops
Asynchronous master reset
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
CP to Q
n
17
18
ns
MR to Q
n
13
17
ns
f
max
maximum clock frequency
99
69
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation
capacitance per flip-flop
notes 1 and 2
17
17
pF
1998 Jul 08
3
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC174N;
74HCT174N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC174D;
74HCT174D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC174DB;
74HCT174DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC174PW;
74HCT174PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
asynchronous master reset (active LOW)
2, 5, 7, 10, 12, 15
Q
0
to Q
5
flip-flop outputs
3, 4, 6, 11, 13, 14
D
0
to D
5
data inputs
8
GND
ground (0 V)
9
CP
clock input (LOW-to-HIGH, edge-triggered)
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
1998 Jul 08
4
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don't care
= LOW-to-HIGH CP transition
OPERATING MODES
INPUTS
OUTPUTS
MR
CP
D
n
Q
n
reset (clear)
L
X
X
L
load "1"
H
h
H
load "0"
H
I
L
Fig.4 Functional diagram.
Fig.5 Logic diagram.
1998 Jul 08
5
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive-edge trigger
74HC/HCT174
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25
-
40 to +85
-
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
55
165
205
250
ns
2.0
Fig.6
20
33
41
50
4.5
16
28
35
43
6.0
t
PHL
propagation delay
MR to Q
n
44
150
190
225
ns
2.0
Fig.7
16
30
38
45
4.5
13
26
33
38
6.0
t
THL
/ t
TLH
output transition time
19
75
95
110
ns
2.0
Fig.6
7
15
19
22
4.5
6
13
16
19
6.0
t
W
clock pulse width
HIGH or LOW
80
17
100
120
ns
2.0
Fig.6
16
6
20
24
4.5
14
5
17
20
6.0
t
W
master reset pulse
width; LOW
80
12
100
120
ns
2.0
Fig.7
16
4
20
24
4.5
14
3
17
20
6.0
t
rem
removal time
MR to CP
5
-
11
5
5
ns
2.0
Fig.7
5
-
4
5
5
4.5
5
-
3
5
5
6.0
t
su
set-up time
D
n
to CP
60
6
75
90
ns
2.0
Fig.8
12
2
15
18
4.5
10
2
13
15
6.0
t
h
hold time
D
n
to CP
3
-
6
3
3
ns
2.0
Fig.8
3
-
2
3
3
4.5
3
-
2
3
3
6.0
f
max
maximum clock pulse
frequency
6
30
5
4
MHz
2.0
Fig.6
30
90
24
20
4.5
35
107
28
24
6.0
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