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Электронный компонент: 74HCT4515D

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DATA SHEET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT4515
4-to-16 line decoder/demultiplexer
with input latches; inverting
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
September 1993
2
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
FEATURES
Inverting outputs
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4515 are high-speed Si-gate CMOS
devices and are pin compatible with "4515" of the "4000B"
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4515 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A
0
to A
3
) with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 inverting
outputs (Q
0
to Q
15
) are mutually exclusive active LOW.
When LE is HIGH, the selected output is determined by the
data on A
n
. When LE goes LOW, the last data present at
A
n
are stored in the latches and the outputs remain stable.
When E is LOW, the selected output, determined by the
contents of the latch, is LOW. When E is HIGH, all outputs
are HIGH. The enable input (E) does not affect the state of
the latch.
When the "4515" is used as a demultiplexer, E is the data
input and A
0
to A
3
are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay A
n
to Q
n
C
L
= 15 pF; V
CC
= 5 V
25
26
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
44
46
pF
September 1993
3
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LE
latch enable input (active HIGH)
2, 3, 21, 22
A
0
to A
3
address inputs
11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15 Q
0
to Q
15
multiplexer outputs (active LOW)
12
GND
ground (0 V)
23
E
enable input (active LOW)
24
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
4
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
Fig.4 Functional diagram.
APPLICATIONS
Digital multiplexing
Address decoding
Hexadecimal/BCD decoding
FUNCTION TABLE
Notes
1. LE = HIGH
H = HIGH voltage level
L = LOW voltage level
X = don't care
INPUTS
OUTPUTS
E
A
0
A
1
A
2
A
3
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
September 1993
5
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
Fig.5 Logic diagram.
September 1993
6
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25
-
40 to +85
-
40 to +125
min.
typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
A
n
to Q
n
80
29
23
250
50
43
315
63
54
375
75
64
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
66
24
19
225
45
38
280
56
48
340
68
58
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
E to Q
n
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
t
W
latch enable pulse width
HIGH
75
15
13
14
5
4
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
A
n
to LE
90
18
15
28
10
8
115
23
20
135
27
23
ns
2.0
4.5
6.0
Fig.7
t
h
hold time
A
n
to LE
0
0
0
-
11
-
4
-
3
0
0
0
0
0
0
ns
2.0
4.5
6.0
Fig.7
September 1993
7
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
A
n
LE
E
0.65
1.40
1.00
SYMBOL PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25
-
40 to+85
-
40 to +125
min.
typ.
max.
min. max.
min.
max.
t
PHL
/ t
PLH
propagation delay
A
n
to Q
n
30
55
69
83
ns
4.5
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
29
50
63
75
ns
4.5
Fig.6
t
PHL
/ t
PLH
propagation delay
E to Q
n
18
40
50
60
ns
4.5
Fig.6
t
THL
/ t
TLH
output transition time
7
15
19
22
ns
4.5
Fig.6
t
W
latch enable pulse width
HIGH
16
3
20
24
ns
4.5
Fig.7
t
su
set-up time
A
n
to LE
18
9
23
27
ns
4.5
Fig.7
t
h
hold time
A
n
to LE
3
-
2
3
3
ns
4.5
Fig.7
September 1993
8
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with
input latches; inverting
74HC/HCT4515
AC WAVEFORMS
PACKAGE OUTLINES
See
"74HC/HCT/HCU/HCMOS Logic Package Outlines"
.
Fig.6
Waveforms showing the input (A
n
, LE, E) to output (Q
n
) propagation delays and the output transition times.
(1)
HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the minimum pulse width of the latch enable input (LE) and the set-up and hold times
for LE to A
n
. Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1)
HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.