Document Outline
- FEATURES
- GENERAL DESCRIPTION
- APPLICATIONS
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FEATURES
- RECOMMENDED OPERATING CONDITIONS
- RATINGS
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- FIGURE REFERENCES FOR DC CHARACTERISTICS
- AC WAVEFORMS
- APPLICATION INFORMATION
- Lock-detection circuit
- PLL design example
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT7046A
Phase-locked-loop with lock
detector
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
FEATURES
Low power consumption
Centre frequency up to 17 MHz
(typ.) at V
CC
= 4.5 V
Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
Minimal frequency drift
Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (C
LD
) and pin 8
(GND). The value of the C
LD
capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
amplifiers. With a passive low-pass
filter, the "7046" forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
VCO
The VCO requires one external
capacitor C1 (between C1
A
and C1
B
)
and one external resistor R1
(between R
1
and GND) or two
external resistors R1 and R2
(between R
1
and GND, and R
2
and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM
OUT
). In contrast to conventional
techniques where the DEM
OUT
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEM
OUT
voltage equals that of the
VCO input. If DEM
OUT
is used, a load
resistor (R
S
) should be connected
from DEM
OUT
to GND; if unused,
DEM
OUT
should be left open. The
VCO output (VCO
OUT
) can be
connected directly to the comparator
input (COMP
IN
), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators' sections are identical,
so that there is no difference in the
SIG
IN
(pin 14) or COMP
IN
(pin 3)
inputs between the HC and HCT
versions.
Phase comparators
The signal input (SIG
IN
) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (f
i
) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (f
r
= 2f
i
) is
suppressed,
is:
where V
DEMOUT
is the demodulator
output at pin 10;
V
DEMOUT
= V
PC1OUT
(via low-pass
filter).
The phase comparator gain
is:
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
DEMOUT
), is the resultant of the
phase differences of signals (SIG
IN
)
and the comparator input (COMP
IN
)
as shown in Fig.6. The average of
V
DEMOUT
is equal to 1/2 V
CC
when
there is no signal or noise at SIG
IN
and with this input the VCO oscillates
at the centre frequency (f
o
). Typical
V
DEMOUT
V
CC
-----------
SIGIN
COMPIN
(
)
=
K
p
V
CC
-----------
V r
/
(
)
.
=
December 1990
3
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
waveforms for the PC1 loop locked at
f
o
are shown in Fig.7.
The frequency capture range (2f
c
) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2f
L
) is defined
as the frequency range of input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration retains lock
even with very noisy input signals.
Typical behaviour of this type of
phase comparator is that it can lock to
input frequencies close to the
harmonics of the VCO centre
frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIG
IN
and COMP
IN
are not important.
PC2 comprises two D-type flip-flops,
control-gating and a 3-state output
stage. The circuit functions as an
up-down counter (Fig.5) where SIG
IN
causes an up-count and COMP
IN
a
down-count. The transfer function of
PC2, assuming ripple (f
r
= f
i
) is
suppressed,
is:
where V
DEMOUT
is the demodulator
output at pin 10;
V
DEMOUT
= V
PC2OUT
(via low-pass
filter).
V
DEMOUT
V
CC
4
-----------
SIGIN
COMPIN
(
)
=
The phase comparator gain is:
V
DEMOUT
is the resultant of the initial
phase differences of SIG
IN
and
COMP
IN
as shown in Fig.8. Typical
waveforms for the PC2 loop locked at
f
o
are shown in Fig.9.
When the frequencies of SIG
IN
and
COMP
IN
are equal but the phase of
SIG
IN
leads that of COMP
IN
, the
p-type output driver at PC2
OUT
is held
"ON" for a time corresponding to the
phase difference (
DEMOUT
). When
the phase of SIG
IN
lags that of
COMP
IN
, the n-type driver is held
"ON".
When the frequency of SIG
IN
is higher
than that of COMP
IN
, the p-type
output driver is held "ON" for most of
the input signal cycle time, and for
the remainder of the cycle both n and
p- type drivers are "OFF" (3-state). If
the SIG
IN
frequency is lower than the
COMP
IN
frequency, then it is the
n-type driver that is held "ON" for
most of the cycle. Subsequently, the
voltage at the capacitor (C2) of the
low-pass filter connected to PC2
OUT
varies until the signal and comparator
inputs are equal in both phase and
frequency. At this stable point the
voltage on C2 remains constant as
the PC2 output is in 3-state and the
VCO input at pin 9 is a high
impedance.
Thus, for PC2, no phase difference
exists between SIG
IN
and COMP
IN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both p and n-type
drivers are "OFF" for most of the
signal input cycle. It should be noted
that the PLL lock range for this type of
phase comparator is equal to the
capture range and is independent of
K
p
V
CC
4
----------- V r
/
(
)
.
=
the low-pass filter. With no signal
present at SIG
IN
the VCO adjusts, via
PC2, to its lowest frequency.
APPLICATIONS
FM modulation and demodulation
Frequency synthesis and
multiplication
Frequency discrimination
Tone decoding
Data synchronization and
conditioning
Voltage-to-frequency conversion
Motor-speed control
December 1990
4
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C;
Notes
1. Applies to the phase comparator section only (VCO disabled).
For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22.
2. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
f
o
VCO centre frequency
C1 = 40 pF; R1 = 3 k
; V
CC
= 5 V
19
19
MHz
C
I
input capacitance (pin 5)
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
24
24
pF
December 1990
5
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LD
lock detector output (active HIGH)
2
PC1
OUT
phase comparator 1 output
3
COMP
IN
comparator input
4
VCO
OUT
VCO output
5
INH
inhibit input
6
C1
A
capacitor C1 connection A
7
C1
B
capacitor C1 connection B
8
GND
ground (0 V)
9
VCO
IN
VCO input
10
DEM
OUT
demodulator output
11
R
1
resistor R1 connection
12
R
2
resistor R2 connection
13
PC2
OUT
phase comparator 2 output
14
SIG
IN
signal input
15
C
LD
lock detector capacitor input
16
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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