Document Outline
- FEATURES
- GENERAL DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- DC CHARACTERISTICS FOR 74HC
- AC CHARACTERISTICS FOR 74HC
- DC CHARACTERISTICS FOR 74HCT
- AC CHARACTERISTICS FOR 74HCT
- AC WAVEFORMS
- TEST CIRCUIT AND WAVEFORMS
- PACKAGE OUTLINES
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT7080
16-bit even/odd parity
generator/checker
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
16-bit even/odd parity
generator/checker
74HC/HCT7080
FEATURES
Word-length easily expanded by cascading
Generates either even or odd parity for 16-data bits
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7080 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT7080 are 16-bit parity generators or
checkers commonly used to detect errors in high-speed
data transmission or data retrieval systems.
The even and odd parity output is available for generating
or checking even/odd parity up to 16-bits.
The even/odd parity output (E/O) is HIGH when an even
number of data inputs (I
0
to I
15
) are HIGH and the
cascade/even-odd-changing input (X) is HIGH.
Expansion to larger word sizes is accomplished by
connecting the even/odd parity output (E/O) to the
cascade/even-odd-changing input (X) of the final stage.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W):
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
V
CC
2
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
-
1.5 V
ORDERING INFORMATION
See
"74HC/HCT/HCU/HCMOS Logic Package Information"
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
I
n
to E/O
29
32
ns
X to E/O
12
15
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
24
25
pF
December 1990
3
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
X
cascade/even-odd-changing input
2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18
I
0
to I
15
data inputs
10
GND
ground (0 V)
19
E/O
even/odd parity output
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
E = even
INPUTS
OUTPUTS
I
n
X
E/O
= E
H
L
H
L
E
H
L
L
H
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min.
typ.
max.
min. max.
min.
max.
t
PHL
/ t
PLH
propagation delay
I
n
to E/O
91
33
26
280
56
48
350
70
60
420
84
71
ns
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
X to E/O
41
15
12
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
December 1990
6
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
"74HC/HCT/HCU/HCMOS Logic Family Specifications"
.
Output capability: standard
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
I
n
X
1.0
1.0
SYMBOL PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
-
40 to
+
85
-
40 to
+
125
min. typ. max. min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
I
n
to E/O
37
63
79
95
ns
4.5
Fig.7
t
PHL
/ t
PLH
propagation delay
X to E/O
18
32
40
48
ns
4.5
Fig.6
t
THL
/ t
TLH
output transition time
7
15
19
22
ns
4.5
Figs 6 and 7
December 1990
7
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
AC WAVEFORMS
Fig.6
Waveforms showing the cascade/even-odd-changing input (X) to the even/odd parity output (E/O)
propagation delays and the output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the data inputs (I
n
) to the even/odd parity output (E/O) propagation delays and the
output transition times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
December 1990
8
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
TEST CIRCUIT AND WAVEFORMS
PACKAGE OUTLINES
See
"74HC/HCT/HCU/HCMOS Logic Package Outlines"
.
Fig.8 Test circuit for measuring AC performance.
C
L
=
load capacitance including jig and
probe capacitance
(see AC CHARACTERISTICS for values).
R
T
=
termination resistance should be equal to the output
impedance Z
O
of the pulse generator.
FAMILY
AMPLITUDE
V
M
t
r
; t
f
f
max
; PULSE WIDTH
OTHER
74HC
V
CC
50%
<
2 ns
6 ns
74HCT
3.0 V
1.3 V
<
2 ns
6 ns
Fig.9 Input pulse definitions.
C
L
=
load capacitance including jig and
probe capacitance
(see AC CHARACTERISTICS for values).
R
T
=
termination resistance should be equal to the output
impedance Z
O
of the pulse generator.
FAMILY
AMPLITUDE
V
M
t
r
; t
f
f
max
; PULSE WIDTH
OTHER
74HC
V
CC
50%
<
2 ns
6 ns
74HCT
3.0 V
1.3 V
<
2 ns
6 ns
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