Philips
Semiconductors
74LV107
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Apr 20
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
2
1998 Apr 20
8531904 19255
FEATURES
Wide operating: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
C
Output capability: standard
I
CC
category: flip-flops
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop
featuring individual J, K, clock (nCP) and reset (nR) inputs; also
complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to the
HIGH-to-LOW clock transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it
overrides the clock and data inputs, forcing the Q output LOW and
the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
C
L
= 15 pF;
V
CC
= 3.3 V
15
15
15
ns
f
max
Maximum clock frequency
77
MHz
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per flip-flop
V
I
= GND to V
CC
1
30
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
40
C to +125
C
74LV107 N
74LV107 N
SOT27-1
14-Pin Plastic SO
40
C to +125
C
74LV107 D
74LV107 D
SOT108-1
14-Pin Plastic SSOP Type II
40
C to +125
C
74LV107 DB
74LV107 DB
SOT337-1
14-Pin Plastic TSSOP Type I
40
C to +125
C
74LV107 PW
74LV107PW DH
SOT402-1
PIN CONFIGURATION
SV00497
1J
1Q
1Q
1K
2Q
2Q
GND
1R
1CP
2K
2R
2CP
2J
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 8, 4, 11
1J, 2J, 1K, 2K
Synchronous inputs; flip-flops 1 and 2
2, 6
1Q, 2Q
Complement flip-flop outputs
3, 5
1Q, 2Q
True flip-flop outputs
7
GND
Ground (0 V)
12, 9
1CP, 2CP
Clock input
(HIGH-to-LOW, edge-triggered)
13, 10
1R, 2R
Asynchronous reset inputs
(active LOW)
14
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
3
LOGIC SYMBOL
SV00498
8
2J
1
1J
J
11
2K
4
1K
K
FF
9
12 1CP
2CP
CP
Q
2
1Q
6
2Q
Q
3
1Q
5
2Q
10
13
R
1R
2R
LOGIC SYMBOL (IEEE/IEC)
SV00499
1
8
1J
2J
1K
2K
1R
2R
C1
C1
3
5
2
6
12
9
4
11
13
10
FUNCTIONAL DIAGRAM
SV00500
1
8
1J
2J
J
J
4
11
13
10
1K
2K
K
K
FF1
FF2
12
9
1CP
2CP
CP
CP
Q
Q
2
6
1Q
2Q
Q
Q
3
5
1Q
2Q
R
R
1R
2R
LOGIC DIAGRAM
SV00501
C
C
C
C
C
C
C
C
CP
R
J
K
Q
Q
C
C
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
4
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
OPERATING MODES
nR
nCP
nJ
nK
nQ
nQ
Asynchronous reset
L
X
X
X
L
H
Toggle
H
h
h
q
q
Load "0" (reset)
H
l
h
L
H
Load "1" (set)
H
h
l
H
L
Hold "no change"
H
l
l
q
q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition.
X = don't care
= HIGH-to-LOW CP transition
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
"
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
"
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
"
I
O
DC output source or sink current
standard outputs
0.5V < V
O
< V
CC
+ 0.5V
25
mA
"
I
GND
,
"
I
CC
DC V
CC
or GND current for types with
standard outputs
50
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125
C
above +70
C derate linearly with 12 mW/K
above +70
C derate linearly with 8 mW/K
above +60
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
V
CC
DC supply voltage
See Note 1
1.0
3.3
5.5
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
See DC and AC
characteristics
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times except for
Schmitt-trigger inputs
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
500
200
100
50
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
V
CC
= 1.2 V
0.9
0.9
V
IH
HIGH level Input
V
CC
= 2.0 V
1.4
1.4
V
V
IH
voltage
V
CC
= 2.7 to 3.6 V
2.0
2.0
V
V
CC
= 4.5 to 5.5 V
0.7
<
V
CC
0.7
<
V
CC
V
CC
= 1.2 V
0.3
0.3
V
IL
LOW level Input
V
CC
= 2.0 V
0.6
0.6
V
V
IL
voltage
V
CC
= 2.7 to 3.6 V
0.8
0.8
V
V
CC
= 4.5 to 5.5
0.3
<
V
CC
0.3
<
V
CC
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
HIGH level output
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
V
OH
HIGH level output
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
voltage all out uts
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
4.3
4.5
4.3
V
OH
HIGH level output
voltage;
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
2.40
2.82
2.20
V
V
OH
g
STANDARD
outputs
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 12mA
3.60
4.20
3.50
V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
LOW level output
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
voltage all out uts
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage;
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
V
OL
g
STANDARD
outputs
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 12mA
0.35
0.55
0.65
V
I
I
Input leakage
current
V
CC
= 5.5 V; V
I
= V
CC
or GND
1.0
1.0
A
I
CC
Quiescent supply
current; flip-flops
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
80
A
I
CC
Additional
quiescent supply
current per input
V
CC
= 2.7 V to 3.6 V; V
I
= V
CC
0.6 V
500
850
A
NOTE:
1. All typical values are measured at T
amb
= 25
C.
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
CONDITION
40 to +85
C
40 to +125
C
UNIT
V
CC
(V)
MIN
TYP
1
MAX
MIN
MAX
1.2
95
Propagation delay
2.0
32
44
56
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
Figures 1, 2
2.7
24
33
41
ns
nCP to nQ, nQ
3.0 to 3.6
18
2
26
33
4.5 to 5.5
22
28
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