Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
2
1998 May 07
8531915 19349
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
C
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT165.
The 74LV165 is an 8-bit parallel-load or serial-in shift register with
complementary serial outputs (Q
7
and Q
7
) available from the last
stage. When the parallel load (PL) input is LOW, parallel data from the
D
0
to D
7
inputs are loaded into the register asynchronously. When PL
is HIGH, data enters the register serially at the D
S
input and shifts one
place to the right (Q
0
Q
1
Q
2
, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter expansion by
tying the Q
7
output to the D
S
input of the succeeding stage.
The clock input is a gated-OR structure which allows one input to be
used as an active LOW clock enable (CE) input. The pin assignment
for the CP and CE inputs is arbitrary and can be reversed for layout
convenience. The LOW-to-HIGH transition of input CE should only
take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL is activated.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CE, CP to Q
7
, Q
7
PL to Q
7
, Q
7
D
7
to Q
7
, Q
7
C
L
= 15 pF;
V
CC
= 3.3 V
18
18
14
ns
f
max
Maximum clock frequency
78
MHz
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per gate
V
CC
= 3.3 V
V
I
= GND to V
CC
1
35
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
40
C to +125
C
74LV165 N
74LV165 N
SOT38-4
16-Pin Plastic SO
40
C to +125
C
74LV165 D
74LV165 D
SOT109-1
16-Pin Plastic SSOP Type II
40
C to +125
C
74LV165 DB
74LV165 DB
SOT338-1
16-Pin Plastic TSSOP Type I
40
C to +125
C
74LV165 PW
74LV165PW DH
SOT403-1
PIN CONFIGURATION
SV00585
1
2
3
4
5
6
PL
CP
D
4
D
5
D
6
D
7
V
CC
CE
D
3
16
15
14
13
12
11
7
8
GND
D
S
Q
7
10
9
Q
7
D
2
D
1
D
0
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
PL
Asynchronous parallel load
input (active LOW)
2
CP
Clock input (LOW to
HIGH, edge-triggered)
7
Q
7
Complementary output from
the last stage
8
GND
Ground (0 V)
9
Q
7
Serial output from last stage
10
D
S
Serial data input
11, 12, 13, 14, 3, 4, 5, 6
D
0
to D
7
Parallel data inputs
15
CE
Clock enable input
(active LOW)
16
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07
4
FUNCTION TABLE
OPERATING MODES
INPUTS
Qn REGISTERS
OUTPUTS
OPERATING MODES
PL
CE
CP
D
S
D
0
D
7
Q
0
Q
1
Q
6
Q
7
Q
7
Parallel load
L
X
X
X
L
L
LL
L
H
Parallel load
L
X
X
X
H
H
HH
H
L
Serial Shift
H
L
l
X
L
q
0
q
5
q
6
q
6
Serial Shift
H
L
h
X
H
q
0
q
5
q
6
q
6
Hold "do nothing"
H
H
X
X
X
q
0
q
1
q
6
q
7
q
7
NOTES:
H =
HIGH voltage level
h
=
HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L
=
LOW voltage level
I
=
LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
q
=
lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X =
don't care
=
LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
DC supply voltage
See Note 1
1.0
3.3
5.5
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
See DC and AC
characteristics
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
500
200
100
50
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
"
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
"
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
"
I
O
DC output source or sink current
standard outputs
0.5V < V
O
< V
CC
+ 0.5V
25
mA
"
I
GND
,
"
I
CC
DC V
CC
or GND current for types with
standard outputs
50
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125
C
above +70
C derate linearly with 12 mW/K
above +70
C derate linearly with 8 mW/K
above +60
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
V
CC
= 1.2 V
0.9
0.9
V
HIGH level Input
V
CC
= 2.0 V
1.4
1.4
V
V
IH
voltage
V
CC
= 2.7 to 3.6 V
2.0
2.0
V
V
CC
= 4.5 to 5.5 V
0.7
<
V
CC
0.7
<
V
CC
V
CC
= 1.2 V
0.3
0.3
V
LOW level Input
V
CC
= 2.0 V
0.6
0.6
V
V
IL
voltage
V
CC
= 2.7 to 3.6 V
0.8
0.8
V
V
CC
= 4.5 to 5.5
0.3
<
V
CC
0.3
<
V
CC
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
HIGH l
l
t
t
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
V
OH
HIGH level output
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
voltage all out uts
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
4.3
4.5
4.3
V
O
HIGH level output
voltage;
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
2.40
2.82
2.20
V
V
OH
g
STANDARD
outputs
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 12mA
3.60
4.20
3.50
V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
LOW l
l
t
t
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
voltage all out uts
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
O
LOW level output
voltage;
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
V
OL
g
STANDARD
outputs
V
CC
= 4.5 V; V
I
= V
IH
or V
IL;
I
O
= 12mA
0.35
0.55
0.65
V
I
I
Input leakage
current
V
CC
= 5.5 V; V
I
= V
CC
or GND
1.0
1.0
A
I
CC
Quiescent supply
current; MSI
V
CC
= 5.5 V; V
I
= V
CC
or GND; I
O
= 0
20.0
160
A
I
CC
Additional
quiescent supply
current per input
V
CC
= 2.7 V to 3.6 V; V
I
= V
CC
0.6 V
500
850
A
NOTE:
1. All typical values are measured at T
amb
= 25
C.
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