Philips Semiconductors
Product specification
74LV259
8-bit addressable latch
2
1998 May 20
853-1988 19420
FEATURES
Optimized for low voltage applications: 1.0 to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
T
amb
= 25
C
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Output capability: standard
I
CC
category: MSI
DESCRIPTION
The 74LV259 is a low-voltage CMOS device and is pin and function
compatible with 74HC/HCT259.
The 74LV259 is a high-speed 8-bit addressable latch designed for
general purpose storage applications in digital systems. The
74LV259 is a multifunction device capable of storing single-line data
in eight addressable latches, and also 3-to-8 decoder and
demultiplexer, with active HIGH outputs (Q
0
to Q
7
), functions are
available. The 74LV259 also incorporate an active LOW common
reset (MR) for resetting all latches, as well as an active LOW enable
input (LE). The 74LV259 has four modes of operation as shown in
the mode select table. In the addressable latch mode, data on the
data line (D) is written into the addressed latch. The addressed latch
will follow the data input with all non-addressed latches remaining in
their previous states. In the memory mode, all latches remain in their
previous states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the addressed output
follows the state of the D input with all other outputs in the LOW
state. In the reset mode all outputs are LOW and unaffected by the
address (A
0
to A
2
) and date (D) input. When operating the 74LV259
as an addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this should only
be done while in the memory mode. The mode select table
summarizes the operations of the 74LV259.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
D, A
n
to Q
n
LE to Q
n
MR to Q
n
C
L
= 15 pF;
V
CC
= 3.3 V
17
16
14
ns
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per latch
V
I
= GND to V
CC
1
19
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
40
C to +125
C
74LV259 N
74LV259 N
SOT38-4
16-Pin Plastic SO
40
C to +125
C
74LV259 D
74LV259 D
SOT109-1
16-Pin Plastic SSOP Type II
40
C to +125
C
74LV259 DB
74LV259 DB
SOT338-1
16-Pin Plastic TSSOP Type I
40
C to +125
C
74LV259 PW
74LV259PW DH
SOT403-1
Philips Semiconductors
Product specification
74LV259
8-bit addressable latch
1998 May 20
4
FUNCTION TABLE
OPERATING MODES
INPUTS
OUTPUTS
OPERATING MODES
MR
LE
D
A
0
A
1
A
2
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Master reset
L
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
d
L
L
L
Q=d
L
L
L
L
L
L
L
L
L
d
H
L
L
L
Q=d
L
L
L
L
L
L
Demultiplex
L
L
d
L
H
L
L
L
Q=d
L
L
L
L
L
Demultiplex
(active HIGH)
L
L
d
H
H
L
L
L
L
Q=d
L
L
L
L
(
)
decoder
(when D = H)
L
L
d
L
L
H
L
L
L
L
Q=d
L
L
L
(when D = H)
L
L
d
H
L
H
L
L
L
L
L
Q=d
L
L
L
L
d
L
H
H
L
L
L
L
L
L
Q=d
L
L
L
d
H
H
H
L
L
L
L
L
L
L
Q=d
Store (do nothing)
H
H
X
X
X
X
q0
q1
q2
q3
q4
q5
q6
q7
H
L
d
L
L
L
Q=d
q1
q2
q3
q4
q5
q6
q7
H
L
d
H
L
L
q0
Q=d
q2
q3
q4
q5
q6
q7
H
L
d
L
H
L
q0
q1
Q=d
q3
q4
q5
q6
q7
Addressable latch
H
L
d
H
H
L
q0
q1
q2
Q=d
q4
q5
q6
q7
Addressable latch
H
L
d
L
L
H
q0
q1
q2
q3
Q=d
q5
q6
q7
H
L
d
H
L
H
q0
q1
q2
q3
q4
Q=d
q6
q7
H
L
d
L
H
H
q0
q1
q2
q3
q4
q5
Q=q
q7
H
L
d
H
H
H
q0
q1
q2
q3
q4
q5
q6
Q=d
NOTES:
H =
HIGH voltage level
L
=
LOW voltage level
X =
don't care
d
=
HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q
=
lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which
it was addressed or cleared
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
DC supply voltage
See Note 1
1.0
3.3
3.6
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
See DC and AC
characteristics
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
500
200
100
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
Philips Semiconductors
Product specification
74LV259
8-bit addressable latch
1998 May 20
5
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
"
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
"
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
"
I
O
DC output source or sink current
standard outputs
0.5V < V
O
< V
CC
+ 0.5V
25
mA
"
I
GND
,
"
I
CC
DC V
CC
or GND current for types with
standard outputs
50
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125
C
above +70
C derate linearly with 12 mW/K
above +70
C derate linearly with 8 mW/K
above +60
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
HIGH l
l I
t
V
CC
= 1.2 V
0.9
0.9
V
IH
HIGH level Input
voltage
V
CC
= 2.0 V
1.4
1.4
V
voltage
V
CC
= 2.7 to 3.6 V
2.0
2.0
LOW l
l I
t
V
CC
= 1.2 V
0.3
0.3
V
IL
LOW level Input
voltage
V
CC
= 2.0 V
0.6
0.6
V
voltage
V
CC
= 2.7 to 3.6 V
0.8
0.8
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
V
O
HIGH level output
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
V
V
OH
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
OH
HIGH level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
2.40
2.82
2.20
V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
V
O
LOW level output
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
V
OL
voltage; all outputs
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
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