Document Outline
- FEATURES
- DESCRIPTION
- QUICK REFERENCE DATA
- ORDERING INFORMATION
- PIN DESCRIPTION
- FUNCTION TABLE
- PIN CONFIGURATION
- LOGIC SYMBOL
- LOGIC SYMBOL (IEEE/IEC)
- FUNCTIONAL DIAGRAM
- LOGIC DIAGRAM
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- DC CHARACTERISTICS FOR THE LV FAMILY
- AC CHARACTERISTICS
- AC WAVEFORMS
- TEST CIRCUIT
- PACKAGE OUTLINES
- SOT146-1
- SOT163-1
- SOT339-1
- DEFINITIONS
Philips
Semiconductors
74LV374
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of 1996 Feb
IC24 Data Handbook
1997 Mar 20
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
2
1997 Mar 20
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
T
amb
= 25
C
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
T
amb
= 25
C
Common 3-State output enable input
Output capability: bus driver
I
CC
category: MSI
DESCRIPTION
The 74LV374 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT374.
The 74LV374 is an octal D-type flipflop featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
=t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
C
L
= 15pF
V
CC
= 3.3V
14
ns
f
max
Maximum clock frequency
77
MHz
C
I
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per flip-flop
Notes 1 and 2
25
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)S
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
40
C to +125
C
74LV374 N
74LV374 N
SOT146-1
20-Pin Plastic SO
40
C to +125
C
74LV374 D
74LV374 D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +125
C
74LV374 DB
74LV374 DB
SOT339-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0 to Q7
3-State flip-flop outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data inputs
10
GND
Ground (0V)
11
CP
Clock input (LOW-to-HIGH, edge-
triggered)
20
V
CC
Positive supply voltage
FUNCTION TABLE
OPERATING
INPUTS
INTERNAL
OUTPUTS
MODES
OE
CP
Dn
FLIP-FLOPS
Q0 to Q7
Load and read
register
L
L
l
h
L
H
L
H
Load register and
disable outputs
H
H
l
h
L
H
Z
Z
H
= HIGH voltage level
h
= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L
= LOW voltage level
l
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
Z
= High impedance OFF-state
= LOWtoHIGH clock transition
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
SV00338
LOGIC SYMBOL (IEEE/IEC)
11
1
C1
EN1
1D
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SV00340
LOGIC SYMBOL
CP
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
SV00339
1
OE
FUNCTIONAL DIAGRAM
SV00341
3
4
7
6
5
2
8
9
13
12
14
15
17
16
18
19
11
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FF1
to
FF8
3-STATE
OUTPUTS
LOGIC DIAGRAM
SV00342
D
D0
Q0
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
OE
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
4
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +7.0
V
I
IK
DC input diode current
V
I
< 0.5 or V
I
> V
CC
+ 0.5V
20
mA
I
OK
DC output diode current
V
O
< 0.5 or V
O
> V
CC
+ 0.5V
50
mA
I
O
DC output source or sink current
standard outputs
bus driver outputs
0.5V < V
O
< V
CC
+ 0.5V
25
35
mA
I
GND
,
I
CC
DC V
CC
or GND current for types with
standard outputs
bus driver outputs
50
70
mA
T
stg
Storage temperature range
65 to +150
C
P
TOT
Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125
C
above +70
C derate linearly with 12mW/K
above +70
C derate linearly with 8 mW/K
above +60
C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
V
CC
DC supply voltage
See Note1
1.0
3.3
5.5
V
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free
air
See DC and AC
characteristics per device
40
40
+85
+125
C
t
r
, t
f
Input rise and fall times except for
Schmitt-trigger inputs
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
500
200
100
50
ns/V
NOTES:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
5
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
C to +85
C
-40
C to +125
C
UNIT
MIN
TYP
1
MAX
MIN
MAX
V
CC
= 1.2V
0.9
0.9
V
IH
HIGH level Input
V
CC
= 2.0V
1.4
1.4
V
V
IH
voltage
V
CC
= 2.7 to 3.6V
2.0
2.0
V
V
CC
= 4.5 to 5.5V
0.7*V
CC
0.7*V
CC
V
CC
= 1.2V
0.3
0.3
V
IL
LOW level Input
V
CC
= 2.0V
0.6
0.6
V
V
IL
voltage
V
CC
= 2.7 to 3.6V
0.8
0.8
V
V
CC
= 4.5 to 5.5
0.3*V
CC
0.3*V
CC
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.2
HIGH level output
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
1.8
2.0
1.8
V
OH
HIGH level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.5
2.7
2.5
V
voltage all out uts
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
2.8
3.0
2.8
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 100
A
4.3
4.5
4.3
V
OH
HIGH level output
voltage;
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 6mA
2.40
2.82
2.20
V
V
OH
g
STANDARD
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 12mA
3.60
4.20
3.50
V
V
OH
HIGH level output
voltage; BUS driver
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 8mA
2.40
2.82
2.20
V
V
OH
voltage; BUS driver
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 16mA
3.60
4.20
3.50
V
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
LOW level output
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage; all outputs
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
voltage all out uts
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 100
A
0
0.2
0.2
V
OL
LOW level output
voltage;
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
V
OL
g
STANDARD
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 12mA
0.35
0.55
0.65
V
V
OL
LOW level output
voltage; BUS driver
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 8mA
0.20
0.40
0.50
V
V
OL
voltage; BUS driver
outputs
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 16mA
0.35
0.55
0.65
V
I
I
Input leakage
current
V
CC
= 5.5V; V
I
= V
CC
or GND
1.0
1.0
A
I
OZ
3-State output
OFF-state current
V
CC
= 5.5V; V
I
= V
IH
or V
IL;
V
O
= V
CC
or GND
5
10
A
I
CC
Quiescent supply
current; SSI
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
40
A
I
CC
Quiescent supply
current; flip-flops
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
80
A
I
CC
Quiescent supply
current; MSI
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
160
A
I
CC
Quiescent supply
current; LSI
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
500
1000
A
I
CC
Additional
quiescent supply
current per input
V
CC
= 2.7V to 3.6V; V
I
= V
CC
0.6V
500
850
A
NOTE:
1. All typical values are measured at T
amb
= 25
C.
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
6
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
= 2.5ns; C
L
= 50pF; R
L
= 500
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
40 to +85
C
LIMITS
40 to +125
C
UNIT
V
CC
(V)
MIN
TYP
MAX
MIN
MAX
1.2
90
Propagation delay
2.0
31
39
49
t
PHL/
t
PLH
Propagation delay
CP to Qn
Figure 1
2.7
23
29
36
ns
CP to Qn
3.0 to 3.6
17
2
23
29
4.5 to 5.5
19
24
1.2
75
Propagation delay
2.0
26
34
43
t
PZH/
t
PZL
Propagation delay
OE to Qn
Figure 2
2.7
19
25
31
ns
OE to Qn
3.0 to 3.6
14
2
20
25
4.5 to 5.5
17
21
1.2
80
Propagation delay
2.0
29
39
48
t
PHZ/
t
PLZ
Propagation delay
OE to Qn
Figure 2
2.7
22
29
36
ns
OE to Qn
3.0 to 3.6
17
2
24
29
4.5 to 5.5
20
24
Clock pulse width
2.0
34
12
41
t
W
Clock pulse width
HIGH or LOW
Figure 1
2.7
25
9
30
ns
HIGH or LOW
3.0 to 3.6
20
7
2
24
1.2
25
t
Set-up time
Figure 3
2.0
22
9
26
ns
t
su
Dn to CP
Figure 3
2.7
16
6
19
ns
3.0 to 3.6
13
5
2
15
1.2
10
t
h
Hold time
Figure 3
2.0
5
3
5
ns
t
h
Dn to CP
Figure 3
2.7
5
2
5
ns
3.0 to 3.6
5
2
2
5
Maximum clock
2.0
15
40
12
f
max
Maximum clock
pulse frequency
Figure 2
2.7
19
58
16
MHz
ulse frequency
3.0 to 3.6
24
70
2
20
NOTE:
1. Unless otherwise stated, all typical values are at T
amb
= 25
C.
2. Typical value measured at V
CC
= 3.3V.
3. Typical value measured at V
CC
= 5.0V.
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
w
2.7V
v
3.6V
V
M
= 0.5V * V
CC
at V
CC
t
2.7V and
w
4.5V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
t
PLH
t
PHL
SV00343
CP INPUT
Qn
OUTPUT
1/f
max
V
M
t
W
90%
V
M
10%
t
THL
t
TLH
Figure 1. Waveforms showing the clock (CP) to output (Qn)
propagation delays, the clock pulse width, output transition
times and the maximum clock pulse frequency
outputs
disabled
SV00344
V
I
OE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
V
M
t
PLZ
t
PHZ
t
PZL
V
Y
outputs
enabled
outputs
enabled
V
X
V
M
t
PZH
V
M
Figure 2. Waveforms showing the 3-state enable and disable
times
t
su
t
su
SV00345
CP INPUT
D
n
INPUT
Q
n
OUTPUT
V
M
t
h
V
M
V
M
(1)
t
h
V
I
GND
V
I
GND
V
OH
V
OL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Waveforms showing the data set-up and hold times
for the Dn input to the CP input
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
8
TEST CIRCUIT
V
M
V
M
t
W
NEGATIVE
PULSE
10%
10%
90%
90%
0V
V
M
V
M
t
W
V
I
POSITIVE
PULSE
90%
90%
10%
10%
0V
t
THL
(t
f
)
t
TLH
(t
r
)
t
THL
(t
f
)
t
TLH
(t
r
)
V
M
= 1.5V
Input Pulse Definition
SY00044
SWITCH POSITION
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
= 50pF
R
L
= 1k
V
cc
Test Circuit for Outputs
Open
GND
S
1
V
S1
DEFINITIONS
V
CC
V
I
< 2.7V
2.73.6V
V
CC
2.7V
TEST
S
1
t
PLZ/
t
PZL
t
PLH/
t
PHL
t
PHZ
/t
PZH
V
S1
Open
GND
V
S1
4.5 V
2
<
V
CC
V
CC
2
<
V
CC
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
V
I
2
<
V
CC
R
L
= 1k
Figure 4. Load circuitry for switching times
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
9
DIP20:
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
10
SO20:
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
1997 Mar 20
11
SSOP20:
plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
Philips Semiconductors
Product specification
74LV374
Octal D-type flip-flop; positive edge-trigger (3-State)
yyyy mmm dd
12
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
print code
Date of release: 05-96
Document order number:
9397-750-04448
Philips
Semiconductors
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