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Электронный компонент: 74LVC07AD

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DATA SHEET
Product specification
File under Integrated Circuits, IC24
2000 Mar 07
INTEGRATED CIRCUITS
74LVC07A
Hex buffer with open-drain outputs
2000 Mar 07
2
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
FEATURES
5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
Wide supply voltage range from 1.65 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard no. 8-1A.
DESCRIPTION
The 74LVC07A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. This feature allows
the use of these devices as translators in a mixed
3.3 to 5 V environment.
The 74LVC07A provides six non-inverting buffers.
The outputs of the 74LVC07A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
(C
L
V
CC
2
f
o
) = sum of the outputs.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
t
PLZ
/t
PZL
propagation delay nA to nY
C
L
= 50 pF; V
CC
= 3.3 V
2.2
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per gate
V
I
= GND to V
CC
; note 1
6.0
pF
INPUT
OUTPUT
nA
nY
L
L
H
Z
2000 Mar 07
3
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
ORDERING INFORMATION
PINNING
TYPE NUMBER
PACKAGES
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC07AD
-
40 to +85
C
14
SO
plastic
SOT108-1
74LVC07APW
14
TSSOP
plastic
SOT402-1
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
1A to 6A
data inputs
2, 4, 6, 8, 10 and 12
1Y to 6Y
data outputs
7
GND
ground (0 V)
14
V
CC
DC supply voltage
handbook, halfpage
07
MNA531
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
Fig.1 Pin configuration.
MNA535
handbook, halfpage
2
1
1A
1Y
4
3
2A
2Y
6
5
3A
3Y
8
9
4A
4Y
10
11
5A
5Y
12
13
6A
6Y
Fig.2 Logic symbol.
2000 Mar 07
4
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
MNA534
handbook, halfpage
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
2
1
1
4
3
6
5
8
9
10
11
12
13
1
1
1
1
1
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one gate).
MNA533
handbook, halfpage
GND
A
Y
2000 Mar 07
5
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
MIN.
MAX.
V
CC
DC supply voltage
1.65
5.5
V
V
I
DC input voltage
0
5.5
V
V
O
DC output voltage
active mode
0
V
CC
V
high-impedance mode
0
5.5
V
T
amb
operating ambient temperature
-
40
+85
C
t
r
, t
f
input rise and fall ratios
V
CC
= 1.65 to 2.7 V
0
20
ns/V
V
CC
= 2.7 to 5.5 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
DC supply voltage
-
0.5
+6.5
V
I
IK
DC input diode current
V
I
< 0
-
-
50
mA
V
I
DC input voltage
note 1
-
0.5
+6.5
V
I
OK
DC output clamping diode current
V
O
< 0
-
-
50
mA
V
O
DC output voltage
active mode; note 1
-
0.5
V
CC
+ 0.5 V
high-impedance mode; note 1
-
0.5
+6.5
V
I
O
DC output sink current
V
O
= 0 to V
CC
-
50
mA
I
CC
, I
GND
DC V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation per package
SO package
above 70
C derate linearly
with 8 mW/K
-
500
mW
TSSOP package
above 60
C derate linearly
with 5.5 mW/K
-
500
mW