DATA SHEET
Product specification
Supersedes data of 2002 Mar 8
2003 Feb 28
INTEGRATED CIRCUITS
74LVC126A
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
2003 Feb 28
2
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
74LVC126A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74LVC126A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC126A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A LOW at nOE causes the
outputs to assume a high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA to nY
C
L
= 50 pF; V
CC
= 3.3 V
2.4
ns
C
I
input capacitance
4.0
pF
C
PD
power dissipation capacitance per gate
V
CC
= 3.3 V;
notes 1 and 2
12
pF
TYPE NUMBER
TEMPERATURE RANGE
PACKAGE
PINS
PACKAGE
MATERIAL
CODE
74LVC126AD
-
40 to +125
C
14
SO14
plastic
SOT108-1
74LVC126ADB
-
40 to +125
C
14
SSOP14
plastic
SOT337-1
74LVC126APW
-
40 to +125
C
14
TSSOP14
plastic
SOT402-1
74LVC126ABQ
-
40 to +125
C
14
DHVQFN14
plastic
SOT762-1
2003 Feb 28
3
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
74LVC126A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
Z = high-impedance OFF-state.
PINNING
INPUT
OUTPUT
nOE
nA
nY
H
L
L
H
H
H
L
X
Z
PIN
SYMBOL
DESCRIPTION
1
1OE
data enable input (active HIGH)
2
1A
data input
3
1Y
data output
4
2OE
data enable input (active HIGH)
5
2A
data input
6
2Y
data output
7
GND
ground (0 V)
8
3Y
data output
9
3A
data input
10
3OE
data enable input (active HIGH)
11
4Y
data output
12
4A
data input
13
4OE
data enable input (active HIGH)
14
V
CC
supply voltage
2003 Feb 28
4
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
74LVC126A
MNA233
126
1
2
3
4
5
6
7
8
14
13
12
11
10
9
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
VCC
Fig.1 Pin configuration SO14 and (T)SSOP14.
handbook, halfpage
1
14
1OE
VCC
7
2
3
4
5
6
1A
1Y
2OE
2A
2Y
13
12
11
10
9
4OE
4A
4Y
3OE
3A
8
GND
3Y
GND
(1)
Top view
MCE197
Fig.2 Pin configuration DHVQFN14.
* The die substrate is attached to this pad using conductive die attach
material. It can not be used as a supply pin or input.
handbook, halfpage
MNA235
1A
1Y
2
1
3
1OE
2A
2Y
5
4
6
2OE
3A
3Y
9
10
8
3OE
4A
4Y
12
13
11
4OE
Fig.3 Logic symbol.
handbook, halfpage
MNA236
1
EN1
1
3
2
4
6
5
10
8
9
13
11
12
Fig.4 Logic symbol (IEEE/IEC).
2003 Feb 28
5
Philips Semiconductors
Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
74LVC126A
handbook, halfpage
MNA234
nOE
nA
nY
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70
C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C the value of P
tot
derates linearly with 4.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
for maximum speed performance
2.7
3.6
V
for low voltage applications
1.2
3.6
V
V
I
input voltage
0
5.5
V
V
O
output voltage
output HIGH or LOW state
0
V
CC
V
output 3-state
0
5.5
V
T
amb
operating ambient temperature
-
40
+125
C
t
r
, t
f
input rise and fall times
V
CC
= 1.2 to 2.7 V
0
20
ns/V
V
CC
= 2.7 to 3.6 V
0
10
ns/V
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.5
+6.5
V
I
IK
input diode current
V
I
< 0
-
-
50
mA
V
I
input voltage
note 1
-
0.5
+6.5
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0
-
50
mA
V
O
output voltage
output HIGH or LOW state; note 1
-
0.5
V
CC
+ 0.5
V
output 3-state; note 1
-
0.5
+6.5
V
I
O
output source or sink current
V
O
= 0 to V
CC
-
50
mA
I
GND
, I
CC
V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation per package
T
amb
=
-
40 to +125
C; note 2
-
500
mW
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