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1.
General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2.
Features
s
Wide supply voltage range from 1.65 V to 5.5 V
s
5 V tolerant inputs for interfacing with 5 V logic
s
High noise immunity
s
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V).
s
24 mA output drive (V
CC
= 3.0 V)
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
CMOS low power consumption
s
Latch-up performance exceeds 250 mA
s
Direct interface with TTL levels
s
Inputs accept voltages up to 5 V
s
Multiple package options
s
Specified from
-
40
C to +85
C and
-
40
C to +125
C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 -- 18 October 2004
Product data sheet
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
2 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
3.
Quick reference data
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4.
Ordering information
5.
Functional diagram
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
PHL
, t
PLH
propagation delay
CP to Q
C
L
= 50 pF; V
CC
= 3.3 V
1.0
3.1
5.7
ns
propagation delay
MR to Q
C
L
= 50 pF; V
CC
= 3.3 V
1.0
2.5
5.8
ns
f
max
maximum clock
frequency
C
L
= 50 pF; V
CC
= 3.3 V
175
300
-
MHz
C
I
input capacitance
-
2.5
-
pF
C
PD
power dissipation
capacitance
V
CC
= 3.3 V
[1] [2]
-
14
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC1G175GW
-
40
C to +125
C
SC-88
plastic surface mounted package; 6 leads
SOT363
74LVC1G175GV
-
40
C to +125
C
SC-74
plastic surface mounted package; 6 leads
SOT457
74LVC1G175GM
-
40
C to +125
C
XSON6
plastic extremely thin small outline package; no
leads; 6 terminals; body 1
1.45
0.5 mm
SOT886
Fig 1.
Logic symbol.
Fig 2.
IEC logic symbol.
001aaa468
FF
MR
Q
4
3
6
1
CP
D
001aaa469
1
3
C1
1D
6
R
4
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
3 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
6.
Pinning information
6.1 Pinning
6.2 Pin description
Fig 3.
Logic diagram.
001aaa466
CP
D
MR
C
C
C
C
C
C
C
C
Q
C
C
Fig 4.
Pin configuration SC-88 and SC-74.
Fig 5.
Pin configuration XSON6.
175
5
6
MR
2
GND
1
CP
3
D
V
CC
4
Q
001aaa467
175
GND
001aab657
CP
D
V
CC
MR
Q
Transparent top view
2
3
1
5
4
6
Table 3:
Pin description
Symbol
Pin
Description
CP
1
clock input (LOW-to-HIGH, edge-triggered)
GND
2
ground (0 V)
D
3
data input
Q
4
flip-flop output
V
CC
5
supply voltage
MR
6
master reset input (active LOW)
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
4 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
7.
Functional description
7.1 Function table
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH CP transition;
X = don't care.
8.
Limiting values
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
9.
Recommended operating conditions
Table 4:
Function table
[1]
Operating mode
Input
Output
MR
CP
D
Q
Reset (clear)
L
X
X
L
Load `1'
H
h
H
Load `0'
H
l
L
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
-
0.5
+6.5
V
I
IK
input diode current
V
I
< 0 V
-
-
50
mA
V
I
input voltage
[1]
-
0.5
+6.5
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0 V
-
50
mA
V
O
output voltage
active mode
[1] [2]
-
0.5
V
CC
+ 0.5 V
Power-down mode
[1] [2]
-
0.5
+6.5
V
I
O
output diode current
V
O
= 0 V to V
CC
-
50
mA
I
CC
, I
GND
V
CC
or GND current
-
100
mA
T
stg
storage temperature
-
65
+150
C
P
tot
power dissipation
T
amb
=
-
40
C to +125
C
-
250
mW
Table 6:
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
1.65
5.5
V
V
I
input voltage
0
5.5
V
V
O
output voltage
active mode
0
V
CC
V
Power-down mode; V
CC
= 0 V
0
5.5
V
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 18 October 2004
5 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
10. Static characteristics
T
amb
ambient temperature
-
40
+125
C
t
r
, t
f
input rise and fall times
V
CC
= 1.65 V to 2.7 V
0
20
ns/V
V
CC
= 2.7 V to 5.5 V
0
10
ns/V
Table 6:
Recommended operating conditions
...continued
Symbol
Parameter
Conditions
Min
Max
Unit
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
T
amb
=
-
40
C to +85
C
[1]
V
IH
HIGH-level input voltage V
CC
= 1.65 V to 1.95 V
0.65
V
CC
-
-
V
V
CC
= 2.3 V to 2.7 V
1.7
-
-
V
V
CC
= 2.7 V to 3.6 V
2.0
-
-
V
V
CC
= 4.5 V to 5.5 V
0.7
V
CC
-
-
V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
-
-
0.35
V
CC
V
V
CC
= 2.3 V to 2.7 V
-
-
0.7
V
V
CC
= 2.7 V to 3.6 V
-
-
0.8
V
V
CC
= 4.5 V to 5.5 V
-
-
0.3
V
CC
V
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
-
100
A; V
CC
= 1.65 V to 5.5 V
V
CC
-
0.1
-
-
V
I
O
=
-
4 mA; V
CC
= 1.65 V
1.2
1.54
-
V
I
O
=
-
8 mA; V
CC
= 2.3 V
1.9
2.15
-
V
I
O
=
-
12 mA; V
CC
= 2.7 V
2.2
2.50
-
V
I
O
=
-
24 mA; V
CC
= 3.0 V
2.3
2.62
-
V
I
O
=
-
32 mA; V
CC
= 4.5 V
3.8
4.11
-
V
V
OL
LOW-level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
A; V
CC
= 1.65 V to 5.5 V
-
-
0.10
V
I
O
= 4 mA; V
CC
= 1.65 V
-
0.07
0.45
V
I
O
= 8 mA; V
CC
= 2.3 V
-
0.12
0.30
V
I
O
= 12 mA; V
CC
= 2.7 V
-
0.17
0.40
V
I
O
= 24 mA; V
CC
= 3.0 V
-
0.33
0.55
V
I
O
= 32 mA; V
CC
= 4.5 V
-
0.39
0.55
V
I
LI
input leakage current
V
I
= 5.5 V or GND; V
CC
= 5.5 V
-
0.1
5
A
I
off
power OFF leakage
current
V
I
or V
O
= 5.5 V; V
CC
= 0 V
-
0.1
10
A
I
CC
quiescent supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
-
0.1
10
A
I
CC
additional quiescent
supply current per pin
V
I
= V
CC
-
0.6 V; I
O
= 0 A;
V
CC
= 2.3 V to 5.5 V
-
5
500
A
C
I
input capacitance
-
2.5
-
pF
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