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Электронный компонент: 74LVC1G386

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DATA SHEET
Product specification
2003 Nov 04
INTEGRATED CIRCUITS
74LVC1G386
3-input EXCLUSIVE-OR gate
2003 Nov 04
2
Philips Semiconductors
Product specification
3-input EXCLUSIVE-OR gate
74LVC1G386
FEATURES
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +125
C
SOT363 and SOT457.
DESCRIPTION
The 74LVC1G386 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The input can be driven from either 3.3 or 5 V devices.
This feature allows the use of these devices in a mixed
3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G386 provides the 3-input EXCLUSIVE-OR
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay inputs A, B,
C to output Y
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
8.0
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
5.0
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
5.0
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
4.5
ns
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
3.5
ns
C
I
input capacitance
4
pF
C
PD
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes 1 and 2
13
pF
2003 Nov 04
3
Philips Semiconductors
Product specification
3-input EXCLUSIVE-OR gate
74LVC1G386
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PINNING
INPUT
OUTPUT
A
B
C
Y
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
L
H
H
H
H
TYPE NUMBER
PACKAGE
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
74LVC1G386GV
-
40 to +125
C
6
SC-74
plastic
SOT457
YH
74LVC1G386GW
-
40 to +125
C
6
SC-88
plastic
SOT363
YH
PIN
SYMBOL
DESCRIPTION
1
A
data input
2
GND
ground (0 V)
3
B
data input
4
Y
data output
5
V
CC
supply voltage
6
C
data input
2003 Nov 04
4
Philips Semiconductors
Product specification
3-input EXCLUSIVE-OR gate
74LVC1G386
handbook, halfpage
1
2
3
6
5
4
MNB146
386
VCC
B
Y
C
GND
A
Fig.1 Pin configuration.
handbook, halfpage
MNB143
B
A
C
Y
6
3
1
4
Fig.2 Logic symbol.
handbook, halfpage
1
6
= 1
4
MNB145
3
Fig.3 Logic symbol.
2003 Nov 04
5
Philips Semiconductors
Product specification
3-input EXCLUSIVE-OR gate
74LVC1G386
handbook, full pagewidth
MNB144
A
B
C
Y
Fig.4 Logic diagram.