1.
General description
The 74LVC1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
The three inputs (A, B and C) are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage V
T+
and the negative voltage V
T
-
is defined as the
hysteresis voltage V
H
.
2.
Features
s
Wide supply voltage range from 1.65 V to 5.5 V
s
5 V tolerant input/output for interfacing with 5 V logic
s
High noise immunity
s
Complies with JEDEC standard:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V).
s
24 mA output drive (V
CC
= 3.0 V)
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
CMOS low power consumption
s
Latch-up performance exceeds 250 mA
s
Direct interface with TTL levels
s
Inputs accept voltages up to 5 V
s
Multiple package options
s
Specified from
-
40
C to +85
C and
-
40
C to +125
C.
74LVC1G58
Low-power configurable multiple function gate
Rev. 01 -- 15 September 2004
Product data sheet
9397 750 13852
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 15 September 2004
2 of 18
Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
3.
Quick reference data
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4.
Ordering information
5.
Marking
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
PHL
, t
PLH
propagation delay
input A, B and
C to output Y
V
CC
= 1.8 V; C
L
= 30 pF;
R
L
= 1 k
-
6
-
ns
V
CC
= 2.5 V; C
L
= 30 pF;
R
L
= 500
-
3.5
-
ns
V
CC
= 2.7 V; C
L
= 50 pF;
R
L
= 500
-
4.2
-
ns
V
CC
= 3.3 V; C
L
= 50 pF;
R
L
= 500
-
3.8
-
ns
V
CC
= 5.0 V; C
L
= 50 pF;
R
L
= 500
-
3.0
-
ns
C
I
input capacitance
-
2.5
-
pF
C
PD
power dissipation
capacitance per buffer
V
CC
= 3.3 V
[1] [2]
-
20
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC1G58GW
-
40
C to +125
C
SC-88
plastic surface mounted package; 6 leads
SOT363
74LVC1G58GV
-
40
C to +125
C
SC-74
plastic surface mounted package; 6 leads
SOT457
74LVC1G58GM
-
40
C to +125
C
XSON6
plastic extremely thin small outline package; no
leads; 6 terminals; body 1
1.45
0.5 mm
SOT886
Table 3:
Marking
Type number
Marking code
74LVC1G58GW
YK
74LVC1G58GV
V58
74LVC1G58GM
YK
9397 750 13852
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 15 September 2004
3 of 18
Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
6.
Functional diagram
7.
Pinning information
7.1 Pinning
7.2 Pin description
Fig 1.
Logic symbol.
Y
C
B
A
6
1
3
4
001aab687
Fig 2.
Pin configuration SC-88 and SC-74.
Fig 3.
Pin configuration XSON6.
58
B
C
GND
A
Y
001aab686
1
2
3
6
V
CC
5
4
GND
001aab731
B
A
V
CC
C
Y
Transparent top view
2
3
1
5
4
6
58
Table 4:
Pin description
Symbol
Pin
Description
B
1
data input B
GND
2
ground (0 V)
A
3
data input A
Y
4
data output Y
V
CC
5
supply voltage
C
6
data input C
9397 750 13852
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 15 September 2004
4 of 18
Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
8.
Functional description
8.1 Function table
[1]
H = HIGH voltage level;
L = LOW voltage level.
8.2 Logic configurations
Table 5:
Function table
[1]
Inputs
Output
C
B
A
Y
L
L
L
L
L
L
H
H
L
H
L
L
L
H
H
H
H
L
L
H
H
L
H
H
H
H
L
L
H
H
H
L
Table 6:
Function selection table
Logic function
Figure
2-input NAND
see
Figure 4
2-input NAND with both inputs inverted
see
Figure 7
2-input AND with inverted input
see
Figure 5
and
6
2-input NOR with inverted input
see
Figure 5
and
6
2-input OR
see
Figure 7
2-input OR with both inputs inverted
see
Figure 4
2-input XOR
see
Figure 8
Buffer
see
Figure 9
Inverter
see
Figure 10
Fig 4.
2-input NAND gate or 2-input OR
with both inputs inverted.
Fig 5.
2-input AND gate with inverted B
input or 2-input NOR gate with
inverted C input.
001aab688
B
B
6
Y
C
1
5
2
4
3
Y
Y
C
B
C
V
CC
001aab689
B
B
6
Y
C
1
5
2
4
3
Y
Y
C
B
C
V
CC
9397 750 13852
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 15 September 2004
5 of 18
Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
9.
Limiting values
Fig 6.
2-input AND gate with inverted C
input or 2-input NOR gate with
inverted A input.
Fig 7.
2-input OR gate or 2-input NAND
gate with both inputs inverted.
Fig 8.
2-input XOR gate.
Fig 9.
Buffer.
Fig 10. Inverter.
001aab690
A
A
6
Y
C
1
5
2
4
3
Y
Y
C
A
C
V
CC
001aab691
A
6
C
1
5
2
4
3
Y
V
CC
A
Y
C
Y
A
C
001aab692
B
6
C
1
5
2
4
3
Y
V
CC
Y
B
C
001aab693
A
A
6
Y
1
5
2
4
3
Y
V
CC
001aab694
B
B
6
Y
1
5
2
4
3
Y
V
CC
Table 7:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
supply voltage
-
0.5
+6.5
V
I
IK
input diode current
V
I
< 0 V
-
-
50
mA
V
I
input voltage
[1]
-
0.5
+6.5
V
I
OK
output diode current
V
O
> V
CC
or V
O
< 0 V
-
50
mA
V
O
output voltage
active mode
[1] [2]
-
0.5
+6.5
V
Power-down mode
[1] [2]
-
0.5
+6.5
V
I
O
output source or sink
current
V
O
= 0 V to V
CC
-
50
mA
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