2004 Sep 08
2
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
FEATURES
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40
C to +85
C and
-
40
C to +125
C.
DESCRIPTION
The 74LVC1G86 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices.
These features allow the use of these devices in a mixed
3.3 V and 5 V environment.
This device is fully specified for partial Power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G86 provides the 2-input EXCLUSIVE-OR
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay inputs A and B to
output Y
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
3.7
ns
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
2.5
ns
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
2.8
ns
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
2.3
ns
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
1.9
ns
C
I
input capacitance
5
pF
C
PD
power dissipation capacitance per
buffer
V
CC
= 3.3 V; notes 1 and 2
25
pF
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