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Электронный компонент: 74LVC2373A

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Philips
Semiconductors
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs; damping resistor
(3-State)
Product specification
IC24 Data Handbook
1997 Mar 12
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
2
1997 Mar 12
8531940 17843
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
CC
= 0V
Bushold on all data inputs (74LVCH2373A only)
Integrated 30
W
damping resistor
DESCRIPTION
The 74LVC2373A/74LVCH2373A is a high performance, low-power,
low-voltage Si-gate CMOS device and superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. This feature allows the use of these devices as
translators in a mixed 3.3V/5V environment.
The 74LVC2373A/74LVCH2373A is an octal D-type transparent
latch featuring separate D-type inputs for each latch and 3-State
outputs for bus oriented applications. A latch enable (LE) input and
an output enable (OE) input are common to all internal latches.
The `2373' consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
Dn to Qn
LE to Qn
C
L
= 50pF
V
CC
= 3.3V
4.4
5.0
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per latch
Notes 1, 2
20
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic SO
40
C to +85
C
74LVC2373A D
74LVC2373A D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +85
C
74LVC2373A DB
74LVC2373A DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +85
C
74LVC2373A PW
LVC2373APW DH
SOT360-1
20-Pin Plastic SO
40
C to +85
C
74LVCH2373A D
74LVCH2373A D
SOT163-1
20-Pin Plastic SSOP Type II
40
C to +85
C
74LVCH2373A DB
7LVCH2373A DB
SOT339-1
20-Pin Plastic TSSOP Type I
40
C to +85
C
74LVCH2373A PW
VCH2373APW DH
SOT360-1
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
1997 Mar 12
3
PIN CONFIGURATION
SV00657
Q0
Q1
Q2
Q3
GND
Q4
Q5
Q6
Q7
D0
D1
D2
D3
V
CC
D4
D5
D6
D7
LE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0Q7
3-State latch outputs
3, 4, 7, 8, 13,
14, 17, 18
D0D7
Data inputs
10
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
V
CC
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
SV00659
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
C1
EN1
1D
11
1
LOGIC SYMBOL
SV00658
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
LE
2
5
6
9
12
15
16
19
11
3
4
7
8
13
14
17
18
1
OE
FUNCTIONAL DIAGRAM
SV00660
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
LE
1
LATCH
1 to 8
3STATE
OUTPUTS
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
OE
FUNCTION TABLE
OPERATING
INPUTS
INTERNAL
OUTPUTS
MODES
OE
LE
Dn
LATCHES
Q0 to Q7
Enable and
read register
(transparent
mode)
L
L
H
H
L
H
L
H
L
H
Latch and read
register
L
L
L
L
I
h
L
H
L
H
Latch register
and disable
outputs
H
H
L
L
I
h
L
H
Z
Z
H = HIGH voltage level
h
= HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L
= LOW voltage level
I
= LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
X = Don't care
Z = High impedance OFF-state
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
1997 Mar 12
4
LOGIC DIAGRAM
LATCH
1
D
Q
LE LE
Q0
D0
LATCH
2
D
Q
LE LE
Q1
D1
LATCH
3
D
Q
LE LE
Q2
D2
LATCH
4
D
Q
LE LE
Q3
D3
LATCH
5
D
Q
LE LE
Q4
D4
LATCH
6
D
Q
LE LE
Q5
D5
LATCH
7
D
Q
LE LE
Q6
D6
LATCH
8
D
Q
LE LE
Q7
D7
LE
OE
SV00661
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage (for max. speed performance)
2.7
3.6
V
V
CC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
V
I
DC input voltage range
0
5.5
V
V
I/O
DC input voltage range for I/Os
0
V
CC
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +6.5
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
Note 2
0.5 to +5.5
V
V
I/O
DC input voltage range for I/Os
0.5 to V
CC
+0.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
50
mA
V
OUT
DC output voltage; output HIGH or LOW
Note 2
0.5 to V
CC
+0.5
V
V
OUT
DC output voltage; output 3-State
Note 2
0.5 to +6.5
V
I
OUT
DC output source or sink current
V
O
= 0 to V
CC
50
mA
I
GND
, I
CC
DC V
CC
or GND current
100
mA
T
stg
Storage temperature range
60 to +150
C
Power dissipation per package
P
TOT
plastic mini-pack (SO)
above +70
C derate linearly with 8 mW/K
500
mW
plastic shrink mini-pack (SSOP and TSSOP)
above +60
C derate linearly with 5.5 mW/K
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
1997 Mar 12
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
HIGH level Input voltage
V
CC
= 1.2V
V
CC
V
V
IH
HIGH level Input voltage
V
CC
= 2.7 to 3.6V
2.0
V
V
LOW level Input voltage
V
CC
= 1.2V
GND
V
V
IL
LOW level Input voltage
V
CC
= 2.7 to 3.6V
0.8
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
V
CC
*
0.2
V
CC
V
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 12mA
V
CC
*
0.6
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
V
CC
*
1.0
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 6mA
7
V
CC
*
0.5
V
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
7
V
CC
*
0.2
V
CC
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 12mA
7
V
CC
*
0.8
V
O
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
GND
0.20
V
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
0.55
V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 6mA
7
0.40
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
7
GND
0.20
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 12mA
7
0.55
I
I
Input leakage current
V
CC
= 3.6V; V
I
= 5.5V or GND
Not for I/O pins
0.1
5
A
I
IHZ
/I
ILZ
Input current for common I/O pins
V
CC
= 3.6V; V
I
= V
CC
or GND
0.1
15
A
I
OZ
3-State output OFF-state current
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
0.1
10
A
I
CC
Quiescent supply current
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
0.1
20
A
I
CC
Additional quiescent supply current per
input pin
V
CC
= 2.7V to 3.6V; V
I
= V
CC
0.6V; I
O
= 0
5
500
A
I
BHL
Bushold LOW sustaining current
2, 3, 4
V
CC
= 3.0V; V
I
=0.8V
75
A
I
BHH
Bushold HIGH sustaining current
2, 3, 4
V
CC
= 3.0V; V
I
=2.0V
75
A
I
BHLO
Bushold LOW overdrive current
2, 3, 5
V
CC
= 3.6V
500
A
I
BHHO
Bushold HIGH overdrive current
2, 3, 5
V
CC
= 3.6V
500
A
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. Valid for data inputs of bushold parts (LVCH-A) only.
3. For data inputs only, control inputs do not have a bushold circuit.
4. The specified sustaining current at the data inputs do not have a bushold circuit.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6. For bushold parts, the bushold circuit is switched off when V
I
exceeds V
CC
allowing 5.5V on the input terminal.
7. For data outputs of damping resistor parts only.