Philips
Semiconductors
74LVC544A
Octal D-type registered transceiver,
inverting (3-State)
Product specification
1998 Jul 29
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVC544A
Octal D-type registered transceiver, inverting
(3-State)
2
1998 Jul 29
853-2107 19804
FEATURES
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
Combines 74LVC640 and 74LVC533 type functions in one chip
Octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-State inverting outputs for bus oriented applications
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC544A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC544A is an octal registered inverting transceiver
containing two sets of D-type latches for temporary storage of the
data flow in either direction. Separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) inputs are provided for each
register to permit independent control of inputting and outputting in
either direction of the data flow.
The `544A' contains eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for example, the
A-to-B enable (EAB) input must be LOW in order to enter data from
A0A7 or take data from B0B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB)
input makes the A-to-B latches transparent; a subsequent
LOW-to-HIGH transition of the LEAB signal puts the A data into the
latches where it is stored and the B outputs no longer change with
the A inputs. With EAB and OEAB both LOW, the 3-State B output
buffers are active and display the data present at the outputs of the
A latches.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
C; t
r
= t
f
v
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Bn
C
L
= 50pF
V
CC
= 3.3V
4
ns
C
I
Input capacitance
5.0
pF
C
I/O
Input/output capacitance
10
pF
C
PD
Power dissipation capacitance per latch
Notes 1, 2
30
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
x f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
40
C to +85
C
74LVC544A D
74LVC544A D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74LVC544A DB
74LVC544A DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74LVC544A PW
7LVC544APW DH
SOT355-1
Philips Semiconductors
Product specification
74LVC544A
Octal D-type registered transceiver, inverting
(3-State)
1998 Jul 29
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
LEBA
`B' to `A' latch enable input (active
LOW)
2
OEBA
`B' to `A' output enable input (active
LOW)
3, 4, 5, 6,
7, 8, 9, 10
A0A7
`A' data inputs/outputs
11
EBA
`B' to `A' enable input (active LOW)
12
GND
Ground (0V)
22, 21, 20, 19,
18, 17, 16, 15
B0B7
`B' data inputs/outputs
13
OEAB
`A' to `B' output enable input (active
LOW)
14
LEAB
`A' to `B' latch enable input (active
LOW)
23
EAB
`A' to `B' enable input (active LOW)
24
VCC
Positive supply voltage
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
EAB
VCC
EBA
B0
B1
B2
B3
B4
B6
B5
B7
LEAB
OEAB
GND
SV00733
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
OEXX
EXX
LEXX
DATA
OUTPUTS
STATUS
H
X
X
X
Z
Disabled
X
H
X
X
Z
Disabled
L
L
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
h
l
L
H
Latch + Display
L
L
L
L
L
L
H
L
L
H
Transparent
L
L
H
X
NC
Hold
XX
= AB for A-to-B direction, BA for B-to-A direction
H
= HIGH voltage level
L
= LOW voltage level
h
= HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA
l
= LOW state must be present one set-up time before the LOW-to-HIGH transition of LEAB, LEBA, EAB, EBA
X
= Don't care
= LOWtoHIGH level transition
NC
= No change
Z
= High impedance OFF-state
Philips Semiconductors
Product specification
74LVC544A
Octal D-type registered transceiver, inverting
(3-State)
1998 Jul 29
4
LOGIC SYMBOL
8
9
7
10
4
5
3
6
17
16
18
15
21
20
22
19
B5
B6
B4
B7
B1
B2
B0
B3
1
14
13
11
2
23
A5
A6
A4
A7
A1
A2
A0
A3
LEBA
LEAB
OEAB
EAB
OEBA
EBA
SV00734
LOGIC SYMBOL (IEEE/IEC)
2EN4
13
G2
1
2C6
3
4
3
4
5
6
7
8
9
10
22
21
20
19
18
17
16
15
6D
5D
1C5
G1
1EN3
2
23
11
14
SV00735
LOGIC DIAGRAM
LE
D
LE
D
An
Bn
TO 7 OTHER CHANNELS
8 IDENTICAL
CHANNELS
OEBA
EBA
LEBA
OEAB
EAB
LEAB
SV00736
Philips Semiconductors
Product specification
74LVC544A
Octal D-type registered transceiver, inverting
(3-State)
1998 Jul 29
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage (for max. speed performance)
2.7
3.6
V
V
CC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
V
I
DC input voltage range
0
5.5
V
V
O
DC output voltage range; output HIGH or LOW state
0
V
CC
V
V
O
DC output voltage range; output 3-State
0
5.5
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +6.5
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
Note 2
0.5 to +6.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
O
DC output voltage; output HIGH or LOW
Note 2
0.5 to V
CC
+0.5
V
V
O
DC output voltage; output 3-State
Note 2
0.5 to 6.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
65 to +150
C
Power dissipation per package
P
TOT
plastic mini-pack (SO)
above +70
C derate linearly with 8 mW/K
500
P
TOT
plastic shrink mini-pack (SSOP and
TSSOP)
above +60
C derate linearly with 5.5 mW/K
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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