Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
2
1998 Jun 17
853-2071 19589
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with the JEDEC standard no. 8-1 A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
DESCRIPTION
The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-State
operation, outputs can handle 5 V. This feature allows the use of
these devices as translators in a mixed 3.3 V/5 V environment. The
74LVC841A is a 10-bit transparent latch featuring separate D-type
inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches. The 74LVC841A consists of
ten transparent latches with 3-State true outputs. When LE is HIGH,
data at the D
n
inputs enters the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes. When LE is LOW the latches store
the information that was present at the D-inputs a set-up time
preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the ten latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
=t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
D
n
to Q
n
;
LE to Q
n
C
L
= 50 pF;
V
CC
= 3.3 V
4.5
5.0
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per latch
V
I
= GND to V
CC
1
22
pF
NOTE:
1
C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
P
D
= C
PD
V
CC
2
f
i
)
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
40
C to +125
C
74LVC841A D
74LVC841A D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +125
C
74LVC841A DB
74LVC841A DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +125
C
74LVC841A PW
7LVC841APW DH
SOT355-1
PIN CONFIGURATION
24
23
1
SV01723
D
0
D
1
D
2
D
3
D
4
D
5
D
6
GND
D
7
D
8
D
9
Q
0
Q
1
Q
2
Q
3
Q
4
V
CC
Q
5
Q
6
Q
7
Q
8
Q
9
LE
2
3
4
5
6
7
8
9
10
11
12
20
21
22
19
18
17
16
15
14
13
OE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OE
Output enable input (active Low)
2, 3, 4, 5, 6, 7, 8,
9, 10, 11
D
0
to D
9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Q
0
to Q
9
3-state latch outputs
12
GND
Ground (0 V)
13
LE
Latch enable input (active HIGH)
24
V
CC
Positive supply voltage
Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
1998 Jun 17
3
LOGIC SYMBOL (IEEE/IEC)
SV01724
LE
13
Q7
Q8
Q9
2
D0
Q0
19
20
21
22
23
9
10
11
D7
D8
D9
8
D6
Q6
7
D5
Q5
14
6
D4
Q4
15
5
D3
Q3
16
4
D2
Q2
17
3
D1
Q1
18
1
OE
LOGIC SYMBOL
SV01725
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
C1
EN
13
1
1D
LOGIC DIAGRAM
D
D
D
LE
SV01726
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
Q
6
Q
7
Q
8
Q
9
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
D
7
D
8
D
9
LE
OE
D
Q
LATCH
1
LE LE
D
Q
LATCH
2
LE LE
D
Q
LATCH
3
LE LE
D
Q
LATCH
4
LE LE
D
Q
LATCH
5
LE LE
D
Q
LATCH
6
LE LE
D
Q
LATCH
7
LE LE
Q
Q
Q
LATCH
8
LATCH
9
LATCH
10
LE
LE
LE
LE
LE
LE
LE
LE
FUNCTION TABLE for register A
n
or B
n
OPERATING MODES
INPUTS
INTERNAL
OUTPUTS
OPERATING MODES
OE
LE
D
n
LATCHES
Q
0
TO Q
9
Enable and read register (transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
L
L
l
h
L
H
L
H
latch register and disable outputs
H
H
X
X
l
h
L
H
Z
Z
Hold
L
L
X
NC
NC
NOTES:
H
=
HIGH voltage level
h
=
HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L
=
LOW voltage level
l
=
LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X
=
don't care
Z
=
high impedance OFF-state
NC =
no change
Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
1998 Jun 17
4
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
CC
DC supply voltage (for max. speed performance)
2.7
3.6
V
V
CC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
V
I
DC input voltage range
0
5.5
V
V
O
DC output voltage range
0
V
CC
V
T
amb
Operating free-air temperature range
40
+85
C
t
r
, t
f
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +6.5
V
I
IK
DC input diode current
V
I
t
0
50
mA
V
I
DC input voltage
Note 2
0.5 to +5.5
V
I
OK
DC output diode current
V
O
u
V
CC
or V
O
t
0
"
50
mA
V
O
DC output voltage
Note 2
0.5 to V
CC
+0.5
V
I
O
DC output source or sink current
V
O
= 0 to V
CC
"
50
mA
I
GND
, I
CC
DC V
CC
or GND current
"
100
mA
T
stg
Storage temperature range
65 to +150
C
Power dissipation per package
P
TOT
plastic mini-pack (SO)
above +70
C derate linearly with 8 mW/K
500
mW
plastic shrink mini-pack (SSOP and TSSOP)
above +60
C derate linearly with 5.5 mW/K
500
mW
NOTES:
1
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
1998 Jun 17
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
V
V
IH
HIGH level In ut voltage
V
CC
= 2.7 to 3.6V
2.0
V
V
IL
LOW level Input voltage
V
CC
= 1.2V
GND
V
V
IL
LOW level In ut voltage
V
CC
= 2.7 to 3.6V
0.8
V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
CC
*
0.5
V
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
V
CC
*
0.2
V
CC
V
V
OH
HIGH level out ut voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 18mA
V
CC
*
0.6
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
V
CC
*
1.0
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
0.40
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
A
GND
0.20
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
0.55
I
I
Input leakage current
V
CC
= 3 6V; V
I
= 5 5V or GND
"
0 1
"
5
A
I
I
In ut leakage current
V
CC
= 3.6V; V
I
= 5.5V or GND
"
0.1
"
5
A
I
OZ
3-State output OFF-state current
V
CC
= 3.6V; V
I
= V
IH
or V
IL
; V
O
= V
CC
or GND
0.1
"
5
A
I
CC
Quiescent supply current
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
0.1
10
A
I
CC
Additional quiescent supply current per
input pin
V
CC
= 2.7V to 3.6V; V
I
= V
CC
0.6V; I
O
= 0
5
500
A
NOTE:
1
All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF; R
L
= 500
W
; T
amb
= 40
_
C to +85
_
C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
0.3V
V
CC
= 2.7V
UNIT
MIN
TYP
1
MAX
MIN
MAX
t
PHL
/t
PLH
Propagation delay
D
n
to Q
n
Figures 1, 5
1.5
4.5
6.7
1.5
7.5
ns
t
PHL/
t
PLH
Propagation delay
LE to Q
n
Figures 2, 5
1.5
4.9
7.6
1.5
8.6
ns
t
PZH/
t
PZL
3-state output enable time
OE to Q
n
Figures 3, 5
1.5
5.4
7.9
1.5
8.9
ns
t
PHZ/
t
PLZ
3-state output disable time
OE to Q
n
Figures 3, 5
1.5
3.8
5.9
1.5
6.9
ns
t
w
LE pulse width, HIGH
Figure 4
2.0
0.7
2.0
ns
t
su
Set-up time
D
n
to LE
Figure 4
2.0
0.5
2.0
ns
t
h
Hold time
D
n
to LE
Figure 4
1.0
0.5
1.0
ns
NOTE:
1
All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
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