1999 Aug 31
2
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range of 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE
TM
flow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74LVCH32244A only)
Typical output ground bounce voltage:
V
OLP
<0.8 V at V
CC
= 3.3 V; T
amb
= 25
C
Typical output V
OH
undershoot voltage:
V
OHV
>2 V at V
CC
= 3.3 V; T
amb
= 25
C
Power-off disabled outputs, permitting live insertion
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVC(H)32244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
The 74LVC(H)32244A is a 32-bit non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1OE and 2OE.
A HIGH on input nOE causes the outputs to assume a
high-impedance OFF-state.
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to V
CC
through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH32244A bus hold data input circuit eliminates
the need for external pull-up resistors to hold unused or
floating data inputs at a valid logic level (see Fig.3).
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
(C
L
V
CC
2
f
o
) = sum of the outputs.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nA
n
to nY
n
C
L
= 50 pF; V
CC
= 3.3 V
3.0
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per buffer
V
I
= GND to V
CC
; note 1
25
pF
1999 Aug 31
3
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don't care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PINNING
INPUT
OUTPUT
nOE
nA
n
nY
n
L
L
L
L
H
H
H
X
Z
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE MATERIAL
CODE
74LVC32244AEC
-
40 to +85
C
96
LFBGA96
plastic
SOT536-1
74LVCH32244AEC
96
LFBGA96
plastic
SOT536-1
SYMBOL
DESCRIPTION
nA
n
data inputs
nY
n
data outputs
GND
ground (0 V)
nOE
3-state output enable inputs (active LOW)
V
CC
DC supply voltage
1999 Aug 31
4
Philips Semiconductors
Product specification
32-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC32244A;
74LVCH32244A
Fig.1 Pin configuration.
handbook, full pagewidth
MNA471
1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A2 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A2
1A0 1A2 2A0 2A2 3A0 3A2 4A0 4A3 5A0 5A2 6A0 6A2 7A0 7A2 8A0 8A3
1Y0 1Y2 2Y0 2Y2 3Y0 3Y2 4Y0 4Y3 5Y0 5Y2 6Y0 6Y2 7Y0 7Y2 8Y0 8Y3
1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y2 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y2
2OE
3OE 6OE
GND
GND GND
GND
7OE
VCC
VCC
GND
GND GND
GND
VCC
VCC
1OE
6
5
2
1
4
3
4OE 5OE
GND
GND GND
GND
8OE
VCC
VCC
GND
GND GND
GND
VCC
VCC
A
H
J
B
D
E
G
T
C
F
K
M
N
R
L
P
Fig.2 Logic symbol.
handbook, full pagewidth
A3
B6
B5
A6
A5
1A3
1A2
1A1
1A0
A2
A1
B2
B1
1Y0
1Y1
1Y2
1Y3
1OE
H4
F6
F5
E6
E5
3A3
3A2
3A1
3A0
E2
E1
F2
F1
3Y0
3Y1
3Y2
3Y3
3OE
J3
K6
K5
J6
J5
5A3
5A2
5A1
5A0
J2
J1
K2
K1
5Y0
5Y1
5Y2
5Y3
5OE
T4
P6
P5
N6
N5
7A3
7A2
7A1
7A0
N2
N1
P2
P1
7Y0
7Y1
7Y2
7Y3
7OE
A4
D6
D5
C6
C5
2A3
2A2
2A1
2A0
C2
C1
D2
D1
2Y0
2Y1
2Y2
2Y3
2OE
H3
H5
H6
G6
G5
4A3
4A2
4A1
4A0
G2
G1
H1
H2
4Y0
4Y1
4Y2
4Y3
4OE
J4
M6
M5
L6
L5
6A3
6A2
6A1
6A0
L2
L1
M2
M1
6Y0
6Y1
6Y2
6Y3
6OE
MNA472
T3
T5
T6
R6
R5
8A3
8A2
8A1
8A0
R2
R1
T1
T2
8Y0
8Y1
8Y2
8Y3
8OE
PDF 
ZIP
