Philips
Semiconductors
74LVT543
3.3V Octal latched transceiver with
dual enable (3-State)
Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook
1998 Feb 19
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74LVT543
3.3V Octal latched transceiver with dual enable
(3-State)
2
1998 Feb 19
853-1749 18988
FEATURES
Combines 74LVT245 and 74LVT373 type functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Output capability: +64mA/32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74LVT543 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.
FUNCTIONAL DESCRIPTION
The 74LVT543 contains two sets of eight Dtype latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
C; GND = 0V
TYPICAL
UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF;
V
CC
= 3.3V
2.3
3.0
ns
C
IN
Input capacitance
V
I
= 0V or 3.0V
4
pF
C
I/O
I/O capacitance
Outputs disabled; V
I/O
= 0V or 3.0V
10
pF
I
CCZ
Total supply current
Outputs disabled; V
CC
= 3.6V
0.13
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic SOL
40
C to +85
C
74LVT543 D
74LVT543 D
SOT137-1
24-Pin Plastic SSOP Type II
40
C to +85
C
74LVT543 DB
74LVT543 DB
SOT340-1
24-Pin Plastic TSSOP Type I
40
C to +85
C
74LVT543 PW
74LVT543PW DH
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
10
15
9
8
7
6
5
4
3
2
1
VCC
EBA
B0
B1
B2
B3
B4
B5
B6
B7
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
LEBA
14
12
13
11
LEAB
OEAB
EAB
GND
SV00026
LOGIC SYMBOL
21
22
B0 B1 B2
19
20
B3
3
4
5
6
A0 A1 A2 A3
11
23
17
18
B4 B5 B6
15
16
B7
7
8
9
10
A4 A5 A6 A7
EAB
EBA
14
LEAB
1
LEBA
13
OEAB
2
OEBA
SV00027
Philips Semiconductors
Product specification
74LVT543
3.3V Octal latched transceiver with dual enable
(3-State)
1998 Feb 19
3
LOGIC SYMBOL (IEEE/IEC)
14
11
13
1
23
2
3
22
4
21
5
20
6
19
7
18
8
17
10
15
9
16
1EN3
G1
IC5
ZEN4 (AB)
GZ.
ZC6
V3
5D
6D
2V
SV00028
LOGIC DIAGRAM
D
LE
Q
D
LE
Q
DETAIL A
22
B0
21 B1
4
A1
20 B2
5
A2
19 B3
6
A3
18 B4
7
A4
17 B5
8
A5
16 B6
9
A6
15 B7
10
A7
DETAIL A X 7
13
OEAB
11
EAB
14
LEAB
2
OEBA
23
EBA
1
LEBA
3
A0
SV00029
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
14, 1
LEAB / LEBA
A to B / B to A Latch Enable input (active-Low)
11, 23
EAB / EBA
A to B / B to A Enable input (active-Low)
13, 2
OEAB / OEBA
A to B / B to A Output Enable input (active-Low)
3, 4, 5, 6, 7, 8, 9, 10
A0 A7
Port A, 3-State outputs
22, 21, 20, 19, 18, 17, 16, 15
B0 B7
Port B, 3-State outputs
12
GND
Ground (0V)
24
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
OEXX
EXX
LEXX
An or Bn
Bn or An
STATUS
H
X
X
X
Z
Disabled
X
H
X
X
Z
Disabled
L
L
L
L
h
l
Z
Z
Disabled + Latch
L
L
L
L
h
l
H
L
Latch + Display
L
L
L
L
L
L
H
L
H
L
Transparent
L
L
H
X
NC
Hold
H = High voltage level
h
= High voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
L
= Low voltage level
l
= Low voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
X = Don't care
= Low-to-High transition of LEXX or EXX (XX = AB or BA)
NC= No change
Z = High impedance or "off" state
Philips Semiconductors
Product specification
74LVT543
3.3V Octal latched transceiver with dual enable
(3-State)
1998 Feb 19
4
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
CC
DC supply voltage
0.5 to +4.6
V
I
IK
DC input diode current
V
I
< 0
50
mA
V
I
DC input voltage
3
0.5 to +7.0
V
I
OK
DC output diode current
V
O
< 0
50
mA
V
OUT
DC output voltage
3
Output in Off or High state
0.5 to +7.0
V
I
O
DC output current
Output in Low state
128
mA
I
OUT
DC output current
Output in High state
64
mA
T
stg
Storage temperature range
65 to 150
C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
CC
DC supply voltage
2.7
3.6
V
V
I
Input voltage
0
5.5
V
V
IH
High-level input voltage
2.0
V
V
IL
Low-level input voltage
0.8
V
I
OH
High-level output current
32
mA
I
O
Low-level output current
32
mA
I
OL
Low-level output current; current duty cycle
50%; f
1kHz
64
mA
t/
v
Input transition rise or fall rate; outputs enabled
10
ns/V
T
amb
Operating free-air temperature range
40
+85
C
Philips Semiconductors
Product specification
74LVT543
3.3V Octal latched transceiver with dual enable
(3-State)
1998 Feb 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
C to +85
C
UNIT
MIN
TYP
1
MAX
V
IK
Input clamp voltage
V
CC
= 2.7V; I
IK
= 18mA
0.9
1.2
V
V
CC
= 2.7 to 3.6V; I
OH
= 100
A
V
CC
-0.2
V
CC
-0.1
V
OH
High-level output voltage
V
CC
= 2.7V; I
OH
= 8mA
2.4
2.5
V
V
CC
= 3.0V; I
OH
= 32mA
2.0
2.2
V
CC
= 2.7V; I
OL
= 100
A
0.1
0.2
V
CC
= 2.7V; I
OL
= 24mA
0.3
0.5
V
OL
Low-level output voltage
V
CC
= 3.0V; I
OL
= 16mA
0.25
0.4
V
V
CC
= 3.0V; I
OL
= 32mA
0.3
0.5
V
CC
= 3.0V; I
OL
= 64mA
0.4
0.55
V
RST
Power-up output low voltage
5
V
CC
= 3.6V; I
O
= 1mA; V
I
= GND or V
CC
0.13
0.55
V
V
CC
= 3.6V; V
I
= V
CC
or GND
Control pins
0.1
1
V
CC
= 0 or 3.6V; V
I
= 5.5V
Control pins
1
10
I
I
Input leakage current
V
CC
= 3.6V; V
I
= 5.5V
1
20
A
V
CC
= 3.6V; V
I
= V
CC
I/O Data pins
4
0.1
1
V
CC
= 3.6V; V
I
= 0
1
-5
I
OFF
Output off current
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
1
100
A
6
V
CC
= 3V; V
I
= 0.8V
75
150
I
HOLD
Bus Hold current A inputs
6
V
CC
= 3V; V
I
= 2.0V
75
150
A
V
CC
= 0V to 3.6V; V
CC
= 3.6V
500
I
EX
Current into an output in the
High state when V
O
> V
CC
V
O
= 5.5V; V
CC
= 3.0V
60
125
A
I
PU/PD
Power up/down 3-State output
current
3
V
CC
1.2V; V
O
= 0.5V to V
CC
; V
I
= GND or V
CC
;
OE/OE = Don't care
15
100
A
I
CCH
V
CC
= 3.6V; Outputs High, V
I
= GND or V
CC,
I
O =
0
0.13
0.19
I
CCL
Quiescent supply current
V
CC
= 3.6V; Outputs Low, V
I
= GND or V
CC,
I
O =
0
3
12
mA
I
CCZ
V
CC
= 3.6V; Outputs Disabled; V
I
= GND or V
CC,
I
O =
0
0.13
0.19
I
CC
Additional supply current per
input pin
2
V
CC
= 3V to 3.6V; One input at V
CC
-0.6V,
Other inputs at V
CC
or GND
0.1
0.2
mA
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
C.
2. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND
3. This parameter is valid for any V
CC
between 0V and 1.2V with a transition time of up to 10msec. From V
CC
= 1.2V to V
CC
= 3.3V
0.3V a
transition time of 100
sec is permitted. This parameter is valid for T
amb
= 25
C only.
4. Unused pins at V
CC
or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
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