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Электронный компонент: 80C851

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Philips
Semiconductors
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
Supersedes data of 1992 Nov 25
IC20 Data Handbook
1998 Jul 03
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
2
1998 Jul 03
DESCRIPTION
The Philips 80C851/83C851 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The 80C851/83C851 has the same
instruction set as the 80C51. The Philips
CMOS technology combines the high speed
and density characteristics of HMOS with the
low power attributes of CMOS. The Philips
epitaxial substrate minimizes latch-up
sensitivity.
The 80C851/83C851 contains a 4k
8 ROM
with mask-programmable ROM code
protection, a 128
8 RAM, 256
8
EEPROM, 32 I/O lines, two 16-bit
counter/timers, a seven-source, five vector,
two-priority level nested interrupt structure,
a serial I/O port for either multi-processor
communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock
circuits.
In addition, the 80C851/83C851 has two
software selectable modes of power
reduction -- idle mode and power-down
mode. The idle mode freezes the CPU while
allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The
power-down mode saves the RAM and
EEPROM contents but freezes the oscillator,
causing all other chip functions to be
inoperative.
FEATURES
80C51 based architecture
4k
8 ROM
128
8 RAM
Two 16-bit counter/timers
Full duplex serial channel
Boolean processor
Non-volatile 256
8-bit EEPROM
(electrically erasable programmable read
only memory)
On-chip voltage multiplier for erase/write
10,000 erase/write cycles per byte
10 years non-volatile data retention
Infinite number of read cycles
User selectable security mode
Block erase capability
Mask-programmable ROM code protection
Memory addressing capability
64k ROM and 64k RAM
Power control modes:
Idle mode
Power-down mode
CMOS and TTL compatible
1.2 to 16MHz or 3.5 to 24MHz
Three package styles
Three temperature ranges
ROM code protection
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
NORTH AMERICA PHILIPS
PART ORDER NUMBER
ROMless
Version
ROM Version
ROMless
Version
ROM Version
TEMPERATURE RANGE
C
AND PACKAGE
FREQ.
(MHz)
DRAWING
NUMBER
P80C851 FBP
P83C851 FBP
S80C851-4N40
S83C851-4N40
0 to +70, Plastic Dual In-line Package
1.2 to 16
SOT129-1
P80C851 IBP
P83C851 IBP
0 to +70, Plastic Dual In-line Package
3.5 to 24
SOT129-1
P80C851 FBA
P83C851 FBA
S80C851-4A44
S83C851-4A44
0 to +70, Plastic Leaded Chip Carrier
1.2 to 16
SOT187-1
P80C851 IBA
P83C851 IBA
0 to +70, Plastic Leaded Chip Carrier
3.5 to 24
SOT187-1
P80C851 FBB
P83C851 FBB
S80C851-4B44
S83C851-4B44
0 to +70, Plastic Quad Flat Pack
1.2 to 16
SOT307-2
P80C851 IBB
P83C851 IBB
0 to +70, Plastic Quad Flat Pack
3.5 to 24
SOT307-2
P80C851 FFP
P83C851 FFP
S80C851-5N40
S83C851-5N40
40 to +85, Plastic Dual In-line Package
1.2 to 16
SOT129-1
P80C851 FFA
P83C851 FFA
S80C851-5A44
S83C851-5A44
40 to +85, Plastic Leaded Chip Carrier
1.2 to 16
SOT187-1
P80C851 FFB
P83C851 FFB
S80C851-5B44
S83C851-5B44
40 to +85, Plastic Quad Flat Pack
1.2 to 16
SOT307-2
P80C851 FHP
P83C851 FHP
S80C851-6N40
S83C851-6N40
40 to +125, Plastic Dual In-line Package
1.2 to 16
SOT129-1
P80C851 FHA
P83C851 FHA
S80C851-6A44
S83C851-6A44
40 to +125, Plastic Leaded Chip Carrier
1.2 to 16
SOT187-1
P80C851 FHB
P83C851 FHB
S80C851-6B44
S83C851-6B44
40 to +125, Plastic Quad Flat Pack
1.2 to 16
SOT307-2
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
3
BLOCK DIAGRAM
64K BYTE BUS
EXPANSION
CONTRTOL
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
PROGRAMMABLE I/O
CPU
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(4K x 8 ROM)
DATA
MEMORY
(128 x 8 RAM)
TWO 16-BIT
TIMER/EVENT
COUNTERS
T0
T1
COUNTERS
XTAL2
XTAL1
FREQUENCY
REFERENCE
INTERNAL
INTERRUPTS
INT0
INT1
EXTERNAL
INTERRUPTS
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SERIAL IN
SERIAL OUT
SHARED WITH
PORT 3
EEPROM
(256 x 8)
LOGIC SYMBOL
PORT 0
PORT 1
PORT 2
PORT 3
ADDRESS AND
DATA BUS
ADDRESS BUS
SECONDAR
Y
FUNCTIONS
RxD
TxD
INT0
INT1
T0
T1
WR
RD
RST
EA
PSEN
ALE
VSS
XTAL1
XTAL2
VDD
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
4
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
P1.7
WR/P3.6
RD/P3.7
XTAL2
XTAL1
V
SS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
DUAL
IN-LINE
PACKAGE
PLASTIC
LEADED
CHIP
CARRIER
6
1
40
7
17
39
29
18
28
PLASTIC
QUAD
FLAT
PACK
44
34
1
11
33
23
12
22
PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS
PLCC
6
1
40
7
17
39
29
18
28
Pin
Function
Pin
Function
1
NC*
23
NC*
2
P1.0
24
P2.0/A8
3
P1.1
25
P2.1/A9
4
P1.2
26
P2.2/A10
5
P1.3
27
P2.3/A11
6
P1.4
28
P2.4/A12
7
P1.5
29
P2.5/A13
8
P1.6
30
P2.6/A14
9
P1.7
31
P2.7/A15
10
RST
32
PSEN
11
P3.0/RxD
33
ALE
12
NC*
34
NC*
13
P3.1/TxD
35
EA
14
P3.2/INT0
36
P0.7/AD7
15
P3.3/INT1
37
P0.6/AD6
16
P3.4/T0
38
P0.5/AD5
17
P3.5/T1
39
P0.4/AD4
18
P3.6/WR
40
P0.3/AD3
19
P3.7/RD
41
P0.2/AD2
20
XTAL2
42
P0.1/AD1
21
XTAL1
43
P0.0/AD0
22
V
SS
44
V
DD
* NO INTERNAL CONNECTION
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
PQFP
44
34
1
11
33
23
12
22
Pin
Function
Pin
Function
1
P1.5
23
P2.5/A13
2
P1.6
24
P2.6/A14
3
P1.7
25
P2.7/A15
4
RST
26
PSEN
5
P3.0/RxD
27
ALE
6
NC*
28
NC*
7
P3.1/TxD
29
EA
8
P3.2/INT0
30
P0.7/AD7
9
P3.3/INT1
31
P0.6/AD6
10
P3.4/T0
32
P0.5/AD5
11
P3.5/T1
33
P0.4/AD4
12
P3.6/WR
34
P0.3/AD3
13
P3.7RD
35
P0.2/AD2
14
XTAL2
36
P0.1/AD1
15
XTAL1
37
P0.0/AD0
16
V
SS
38
V
DD
17
NC*
39
V
SS
18
P2.0/A8
40
P1.0
19
P2.1/A9
41
P1.1
20
P2.2/A10
42
P1.2
21
P2.3/A11
43
P1.3
22
P2.4/A12
44
P1.4
* NO INTERNAL CONNECTION
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
5
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
LCC
QFP
TYPE
NAME AND FUNCTION
V
SS
20
22
16, 39
I
Ground: 0V reference.
V
DD
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.00.7
3932
4336
3730
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
P1.0P1.7
18
29
4044,
13
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
).
P2.0P2.7
2128
2431
1825
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0P3.7
1017
11,
1319
5,
713
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features
of the SC80C51 family, as listed below:
10
11
5
I
RxD (P3.0): Serial input port
11
13
7
O
TxD (P3.1): Serial output port
12
14
8
I
INT0 (P3.2): External interrupt
13
15
9
I
INT1 (P3.3): External interrupt
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an
external capacitor to V
DD
.
ALE
30
33
27
I/O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When the device
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA
31
35
29
I
External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU
executes out of the internal program memory ROM provided the Program Counter is less
than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of
external program memory. EA is not allowed to float.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
6
Table 1.
8XC851 Special Function Registers
SYMBOL
DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
EF
EE
ED
EC
EB
EA
E9
E8
DPTR:
DPH
DPL
Data pointer
(2 bytes):
High byte
Low byte
83H
82H
00H
00H
EADRH#
EEPROM addr
reg-high
F3H
80H
EADRL#
EEPROM addr
reg-low
F2H
00H
ECNTRL#
EEPROM control reg
F6H
IFE
EEINT
EWP
ECNTR
L3
ECNTR
L2
ECNTR
L1
ECNTR
L0
00H
EDAT#
EEPROM data
register
F4H
xxH
ETIM#
EEPROM timer
register
F5H
08H
BF
BE
BD
BC
BB
BA
B9
B8
IP*
Interrupt priority
B8H
PS
PT1
PX1
PT0
PX0
xxx00000B
AF
AE
AD
AC
AB
AA
A9
A8
IE*
Interrupt enable
A8H
EA
ES
ET1
EX1
ET0
EX0
0xx00000B
P0*
Port 0
80H
87
86
85
84
83
82
81
80
FFH
P1*
Port 1
90H
97
96
95
94
93
92
91
90
FFH
P2*
Port 2
A0H
A7
A6
A5
A4
A3
A2
A1
A0
FFH
P3*
Port 3
B0H
B7
B6
B5
B4
B3
B2
B1
B0
FFH
PCON
Power control
87H
SMOD
GF1
GF0
PD
IDL
0xxx0000B
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0H
CY
AC
F0
RS1
RS0
OV
P
00H
SBUF
Serial data buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00H
SP
Stack pointer
81H
07H
8F
8E
8D
8C
8B
8A
89
88
00H
TCON*
Timer/counter con-
trol
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TMOD
Timer/counter mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
TH0
Timer 0 high byte
8CH
00H
TH1
Timer 1 high byte
8DH
00H
TL0
Timer 0 low byte
8AH
00H
TL1
Timer 1 low byte
8BH
00H
*
SFRs are bit addressable.
#
SFRs are modified from or added to the 80C51 SFRs.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
7
EEPROM
Communications between the CPU and the
EEPROM is accomplished via 5 special
function registers; 2 address registers (high
and low byte), 1 data register for read and
write operations, 1 control register, and 1
timer register to adapt the erase/write time to
the clock frequency. All registers can be read
and written. Figure 1 shows a block diagram
of the CPU, the EEPROM and the interface.
Register and Functional
Description
Address Register (EADRH, EADRL)
The lower byte contains the address of one
of the 256 bytes. The higher byte (EADRH) is
for future extensions and for addressing the
security bits (see Security Facilities). The
EADRH register address is F3H. The EADRL
register address is F2H.
Data Register (EDAT)
This register is required for read and write
operations and also for row/block erase. In
write mode, its contents are written to the
addressed byte (for "row erase" and "block
erase" the contents are don't care). The write
pulse starts all operations, except read. In
read mode, EDAT contains the data of the
addressed byte. The EDAT register address
is F4H.
Timer Register (ETIM)
The timer register is required to adapt the
erase/write time to the oscillator frequency.
The user has to ensure that the erase or
write (program) time is neither too short or
too long.
The ETIM register address is F5H. Table 2
contains the values which must be written to
the ETIM register by software for various
oscillator frequencies (the default value is
08H after RESET).
The general formula is:
2ms Write time:
+
f
XTAL1
[kHz]
512
*
2
Value (decimal,
to be rounded up)
10ms Write time:
+
f
XTAL1
[kHz]
96
*
2
Value (decimal)
Control Register (ECNTRL)
See Figure 2 for a description of this register.
The ECNTRL register address is F6H.
Table 2.
Values for the Timer Register (ETIM)
VALUES FOR ETIM
f
XTAL1
2ms WRITE TIME
10ms WRITE TIME
HEX
DEC
HEX
DEC
1.0MHz
08
8
2.0MHz
02
2
13
19
3.0MHz
04
4
1D
29
4.0MHz
06
6
28
40
5.0MHz
08
8
32
50
6.0MHz
0A
10
3C
60
7.0MHz
0C
12
47
71
8.0MHz
0E
14
51
81
9.0MHz
10
16
5C
92
10.0MHz
12
18
66
102
11.0MHz
14
20
71
113
12.0MHz
16
22
7B
123
13.0MHz
18
24
14.0MHz
1A
26
15.0MHz
1C
28
16.0MHz
1E
30
.
.
24.0MHz
2C
4745
Figure 1. EEPROM Interface Block Diagram
CPU
SEQUENCER
ECNTRL
CLOCK
GENERATOR
ETIM
CONTROL
LOGIC
COLUMN
DECODER
MATRIX
ROW
DECODER
EDATA
EADRH
EADRL
INTERNAL BUS
INTERRUPT
POWER-DOWN IDLE
RESET
CLK
8
8
3
5
8
EEPROM
3
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
8
ECNTRL0
7
6
5
4
3
2
1
0
ECNTRL1
ECNTRL2
ECNTRL3
EWP
EEINT
IFE
Bit
Symbol
Function
ECNTRL.7
IFE
Active high EEPROM interrupt flag: set by the sequencer or by software;
reset by software.
When set and enabled, this flag forces an interrupt to the same vector as the
serial port interrupt (see Interrupt section).
ECNTRL.6
EEINT
EEPROM interrupt enable: set and reset by software (active high).
ECNTRL.5
EWP
Erase/write in progress flag: set and reset by the sequencer (active high).
When EWP is set, access to the EEPROM is not possible. EWP cannot be set or
reset by software.
ECNTRL.4
Reserved.
ECCTRL.3
See table below.
ECNTRL.0
Operation
ECNTRL.3
ECNTRL.2
ECNTRL.1
ECNTRL.0
Byte mode
Row erase
Page write*
Page erase/write*
block erase
0
1


1
0
1


0
0
0


1
0
0


0
Byte mode:
Normal EEPROM mode, default mode after reset. In this mode, data can be read and
written to one byte at a time.
Read mode:
This is the default mode when byte mode is selected. This means that the contents of the
addressed byte are available in the data register.
Write mode:
This mode is activated by writing to the data register. The address register must be loaded
first. Since the old contents are read first (by default), this allows the sequencer to decide
whether an erase/write or write cycle only (data = 00H) is required.
Row erase:
In this mode, the addressed row is cleared. The three LSBs of EADRL are not significant,
i.e. the 8 bytes addressed by EADRL are cleared in the same time normally needed to clear
one byte (t
ROWERASE
= t
E
= t
W
). For the following write modes, only the write and not the
erase/write cycle is required. For example, using the row erase mode, programming 8 bytes
takes t
TOTOAL
= t
E
+ 8
t
W
compared to t
TOTAL
= 8
t
E
+ 8
t
W
(t
E
= t
ERASE
t
W
= t
WRITE
).
Page write:
For future products.
Page erase/write:
For future products.
Block erase:
In this mode all 256 bytes are cleared. The byte containing the security bits is also cleared.
t
BLOCKERASE
= t
E
. The contents of EADRH, EADRL and EDAT are insignificant.
*Future products.
Figure 2. Control Register (ECNTRL)
Program Sequences and Register Contents after Reset
The contents of the EEPROM registers after a Reset are the default values:
EADRH
= 1xxxxxxxB
(security bit address)
EADRL
= 00H
(security bit address)
ETIM
= 08H
(minimum erase time with the lowest permissible oscillator frequency)
ECNTRL
= 00H
(Byte mode, read)
EDAT
= xxH
(security bit)
Initialize:
MOV ETIM, ..
MOV EADRH, ..
Read:
MOV EADRL, ..
MOV .., EDAT
Write:
MOV EADRL, ..
MOV EDAT, ..
Erase row:
MOV EADRL, ..
Row address. 3LSBs don't care
MOV ECNTRL, #0CH
Erase row mode
MOV EDAT, ..
(EDAT) don't care
Erase block: MOV ECNTRL, 0AH
Erase block mode
MOV EDAT, ..
(EDAT) don't care
If the security bit is to be altered, the program generally starts as follows:
MOV EADRH, #80H
MOV EADRL, #00H
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
9
Security Facilities
EEPROM Protection
The EEPROM is protected using four security
bits which are contained in an extra
EEPROM byte at address 8000H
(EADRH/EADRL). They can be set or cleared
by software. To activate the EEPROM
protection, the program sequence in byte
mode must be as follows:
MOV
EADRH, #80H
MOV
EADRL, #00H
MOV
EDAT, #FFH
If two or more of these bits are reset, SB = 0,
the security mode is disabled and the
EEPROM is not protected. If three or four bits
are set, SB = 1 and the EA mode differs from
the internal access mode.
In this case, access to the EEPROM is only
possible in one mode regardless of how the
external access mode is reached (by pulling
the EA pin low or by passing the 4K
boundary). For SB = 1 and "external access"
only, the "block erase" mode is enabled. The
program sequence has to be as follows:
MOV EADRH, #80H (security byte address)
MOV EADRL, #00H (security byte address)
MOV ECNTRL, #0AH (block erase mode)
MOV EDAT, #xxH (start block erase)
All 256 data bytes, the security bits, and SB
will be cleared after completing this mode
(EWP = 0). SB will also be affected in byte
mode when writing to the security byte (not
for SB = 1 and "external access"). Figure 3
illustrates the access to SB.
ROM Code Protection
Since the external access mode can only be
selected by pulling the EA pin low during
reset, it is not possible to read the internal
program memory using the MOVC instruction
while executing external program memory.
Furthermore, it is not possible to change this
mode to internal access within the MOVC
cycle.
Additionally, a mask-programmable ROM
code protection facility is available. When the
program memory passes the 4K boundary
using both the internal and external ROMs, it
is not possible to access the internal ROM
from the external program memory if the
mask-programmable ROM security bit is set.
An access to the lower 4K bytes of program
memory using the MOVC instruction is only
possible while executing internal program
memory.
Also the verification mode (test-mode which
writes the ROM contents to a port for
comparison with a reference code) is not
implemented for security reasons. A different
test-mode is implemented for test purposes.
This mode allows every bit to be tested.
However, the internal code cannot be
accessed via a port.
RESET
RESET
EADRH
EADRL
EEPROM
EA
EDATA
L
n
EAQ
RESET
REGISTERS EADRH AND
EADRL CONTAIN THE
ADDRESS OF THE
SECURITY BYTE
SECURITY BYTE ADDRESS
AND BLOCK ERASE FINISHED
SECURITY BYTE ADDRESS
AND BYTE MODE FINISHED
RESET
SB
SB = 1
EXTERNAL
ACCESS
INHIBIT `READ DATA REGISTER'
INHIBIT `WRITE DATA REGISTER'
EXCEPT (ECNTRL) = BLOCK ERASE
NO
NO
YES
YES
Figure 3. EEPROM Protection (Functional and Flowchart)
8
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
10
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol,
page 3.
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-up reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-up, the voltage on V
DD
and RST must
come up at the same time for a proper
start-up.
Note: Before entering the idle or power-down
modes, the user has to ensure that there is
no EEPROM erase/write cycle in progress
(i.e., the EWP bit has to be reset before
activating the idle or power-down modes;
otherwise EEPROM accesses will be
aborted).
IDLE MODE
In idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM and
EEPROM are preserved. A hardware reset is
the only way to terminate the power-down
mode. The control bits for the reduced power
modes are in the special function register
PCON. Table 3 shows the state of the I/O
ports during low current operating modes.
INTERRUPT SYSTEM
External events and the real-time-driven
on-chip peripherals require service by the
CPU asynchronous to the execution of any
particular section of code. To tie the
asynchronous activities of these functions to
normal program execution, a multiple-source,
two-priority-level, nested interrupt system is
provided. Interrupt response latency is from
3
s to 7
s when using a 12MHz crystal. The
S83C851 acknowledges interrupt requests
from 7 sources as follows:
INT0 and INT1: externally via pins 12 and
13, respectively,
Timer 0 and timer 1: from the two internal
counters,
Serial port: from the internal serial I/O port
or EEPROM (1 vector).
Each interrupt vectors to a separate location
in program memory for its service program.
Each source can be individually enabled (the
EEPROM interrupt can only be enabled when
the serial port interrupt is enabled) or
disabled and can be programmed to a high or
low priority level. All enabled sources can
also be globally disabled or enabled. Both
external interrupts can be programmed to be
level-activated and are active low to allow
"wire-ORing" of several interrupt sources to
one input pin.
Note: The serial port and EEPROM interrupt
flags must be cleared by software; all other
flags are cleared by hardware.
Table 3.
External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
ABSOLUTE MAXIMUM RATINGS
1, 2, 3
PARAMETER
RATING
UNIT
Storage temperature range
65 to +150
C
Voltage on any other pin to V
SS
0.5 to +6.5
V
Input or output DC current on any single I/O pin
5
mA
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.0
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise
noted.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
11
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
C to +70
C (V
DD
= 5V
10%), 40
C to +85
C (V
DD
= 5V
10%), or 40
C to +125
C (V
DD
= 5V
10%), V
SS
= 0V
PART
TEST
LIMITS
SYMBOL
PARAMETER
TYPE
CONDITIONS
MIN
MAX
UNIT
V
IL
Input low voltage, except EA
0 to +70
C
40 to +85
C
40 to +125
C
0.5
0.5
0.5
0.2V
DD
0.1
0.2V
DD
0.15
0.2V
DD
0.25
V
V
V
V
IL1
Input low voltage to EA
0 to +70
C
40 to +85
C
40 to +125
C
0.5
0.5
0.5
0.2V
DD
0.3
0.2V
DD
0.35
0.2V
DD
0.45
V
V
V
V
IH
Input high voltage, except XTAL1, RST
0 to +70
C
40 to +85
C
40 to +125
C
0.2V
DD
+0.9
0.2V
DD
+1.0
0.2V
DD
+1.0
V
DD
+0.5
V
DD
+0.5
V
DD
+0.5
V
V
V
V
IH1
Input high voltage, XTAL1, RST
0 to +70
C
40 to +85
C
40 to +125
C
0.7V
DD
0.7V
DD
+0.1
0.7V
D
+0.1
V
DD
+0.5
V
DD
+0.5
V
DD
+0.5
V
OL
Output low voltage, ports 1, 2, 3
6
I
OL
= 1.6mA
4
0.45
V
V
OL1
Output low voltage, port 0, ALE, PSEN
6
I
OL
= 3.2mA
4
0.45
V
V
OH
Output high voltage, ports 1, 2, 3, ALE, PSEN
I
OH
= 60
A,
I
OH
= 25
A,
I
OH
= 10
A
2.4
0.75V
DD
0.9V
DD
V
V
V
V
OH1
Output high voltage, port 0 in external bus
mode
5
I
OH
= 800
A,
I
OH
= 300
A,
I
OH
= 80
A
2.4
0.75V
DD
0.9V
DD
V
V
V
I
IL
Logical 0 input current, ports 1, 2, 3
0 to +70
C
40 to +85
C
40 to +125
C
V
IN
= 0.45V
50
75
75
A
A
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
0 to +70
C
40 to +85
C
40 to +125
C
V
IN
= 2.0V
650
750
750
A
A
A
I
L1
Input leakage current, port 0, EA
0.45V<V
i
<V
DD
10
A
I
DD
Power supply current:
Active mode @ 16MHz
1
Active mode @ 24MHz
1
Idle mode @ 16MHz
2
Idle mode @ 24MHz
2
Power down mode
3
See note 7
19
29
3.7
5.6
50
mA
mA
mA
mA
A
R
RST
Internal reset pull-down resistor
50
150
k
C
IO
Pin capacitance
f = 1MHz
10
pF
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns; V
IL
= V
SS
+0.5V;
V
IH
= V
DD
0.5V; XTAL2 not connected; EA = RST = Port 0 = V
DD
.
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
r
= t
f
= 5ns; V
IL
= V
SS
+0.5V;
V
IH
= V
DD
0.5V; XTAL2 not connected; EA = Port 0 = V
DD
; RST = V
SS
.
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = V
DD
; RST = XTAL1 = V
SS
.
4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the address bits are stabilizing.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per Port pin:
10mA
Maximum I
OL
per 8-bit port
Port 0:
26mA
Ports 1, 2, and 3:
15mA
Maximum total I
OL
for all output pins:
71mA.
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
7. See Figures 11 through 14 for I
DD
test conditions.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
12
AC ELECTRICAL CHARACTERISTICS
1, 2
16 MHz Version
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
4
Oscillator frequency
1.2
16
MHz
t
LHLL
4
ALE pulse width
85
2t
CLCL
40
ns
t
AVLL
4
Address valid to ALE low
8
t
CLCL
55
ns
t
LLAX
4
Address hold after ALE low
28
t
CLCL
35
ns
t
LLIV
4
ALE low to valid instruction in
150
4t
CLCL
100
ns
t
LLPL
4
ALE low to PSEN low
23
t
CLCL
40
ns
t
PLPH
4
PSEN pulse width
143
3t
CLCL
45
ns
t
PLIV
4
PSEN low to valid instruction in
83
3t
CLCL
105
ns
t
PXIX
4
Input instruction hold after PSEN
0
0
ns
t
PXIZ
4
Input instruction float after PSEN
38
t
CLCL
25
ns
t
AVIV
4
Address to valid instruction in
208
5t
CLCL
105
ns
t
PLAZ
4
PSEN low to address float
10
10
ns
Data Memory
t
RLRH
5
RD pulse width
275
6t
CLCL
100
ns
t
WLWH
5
WR pulse width
275
6t
CLCL
100
ns
t
RLDV
5
RD low to valid data in
148
5t
CLCL
165
ns
t
RHDX
5
Data hold after RD
0
0
ns
t
RHDZ
5
Data float after RD
55
2t
CLCL
70
ns
t
LLDV
5
ALE low to valid data in
350
8t
CLCL
150
ns
t
AVDV
5
Address to valid data in
398
9t
CLCL
165
ns
t
LLWL
5, 6
ALE low to RD or WR low
138
238
3t
CLCL
50
3t
CLCL
+50
ns
t
AVWL
5, 6
Address valid to RD or WR low
120
4t
CLCL
130
ns
t
QVWH
6
Data setup time before WR
288
7t
CLCL
150
ns
t
QVWX
6
Data valid to WR transition
3
t
CLCL
60
ns
t
WHQX
6
Data hold after WR
13
t
CLCL
50
ns
t
RLAZ
5
RD low to address float
0
0
ns
t
WHLH
5, 6
RD or WR high to ALE high
23
103
t
CLCL
40
t
CLCL
+40
ns
External Clock
t
CHCX
8
High time
20
20
ns
t
CLCX
8
Low time
20
20
ns
t
CLCH
8
Rise time
20
20
ns
t
CHCL
8
Fall time
20
20
ns
Erase/write timer constant
3
t
E/W
Erase/write cycle time
4
20
4
20
ms
t
E
Erase time
2
10
2
10
ms
t
W
Write time
2
10
2
10
ms
t
S
Data retention time
4
10
10
years
NE/W
Erase/write cycles
5
10,000
10,000
cycles
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V
DD
must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
spurious parasitic writing to EEPROM cells. If the V
DD
power-off full-time is greater than 1ms, a power-off reset signal should be generated
to prevent this condition from occurring.
4. Test condition: T
amb
= +55
C.
5. Number of erase/write cycles for each EEPROM byte.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
13
AC ELECTRICAL CHARACTERISTICS
1, 2
24 MHz Version
24MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
4
Oscillator frequency
3.5
24
MHz
t
LHLL
4
ALE pulse width
43
2t
CLCL
40
ns
t
AVLL
4
Address valid to ALE low
17
t
CLCL
25
ns
t
LLAX
4
Address hold after ALE low
17
t
CLCL
25
ns
t
LLIV
4
ALE low to valid instruction in
102
4t
CLCL
65
ns
t
LLPL
4
ALE low to PSEN low
17
t
CLCL
25
ns
t
PLPH
4
PSEN pulse width
80
3t
CLCL
45
ns
t
PLIV
4
PSEN low to valid instruction in
65
3t
CLCL
60
ns
t
PXIX
4
Input instruction hold after PSEN
0
0
ns
t
PXIZ
4
Input instruction float after PSEN
17
t
CLCL
25
ns
t
AVIV
4
Address to valid instruction in
128
5t
CLCL
80
ns
t
PLAZ
4
PSEN low to address float
10
10
ns
Data Memory
t
RLRH
5
RD pulse width
150
6t
CLCL
100
ns
t
WLWH
5
WR pulse width
150
6t
CLCL
100
ns
t
RLDV
5
RD low to valid data in
118
5t
CLCL
90
ns
t
RHDX
5
Data hold after RD
0
0
ns
t
RHDZ
5
Data float after RD
55
2t
CLCL
28
ns
t
LLDV
5
ALE low to valid data in
183
8t
CLCL
150
ns
t
AVDV
5
Address to valid data in
210
9t
CLCL
165
ns
t
LLWL
5, 6
ALE low to RD or WR low
75
175
3t
CLCL
50
3t
CLCL
+50
ns
t
AVWL
5, 6
Address valid to RD or WR low
92
4t
CLCL
75
ns
t
QVWH
6
Data setup time before WR
162
7t
CLCL
130
ns
t
QVWX
6
Data valid to WR transition
12
t
CLCL
30
ns
t
WHQX
6
Data hold after WR
17
t
CLCL
25
ns
t
RLAZ
5
RD low to address float
0
0
ns
t
WHLH
5, 6
RD or WR high to ALE high
17
67
t
CLCL
25
t
CLCL
+25
ns
External Clock
t
CHCX
8
High time
17
17
ns
t
CLCX
8
Low time
17
17
ns
t
CLCH
8
Rise time
5
20
ns
t
CHCL
8
Fall time
5
20
ns
Erase/write timer constant
3
t
E/W
Erase/write cycle time
4
20
4
20
ms
t
E
Erase time
2
10
2
10
ms
t
W
Write time
2
10
2
10
ms
t
S
Data retention time
4
10
10
years
NE/W
Erase/write cycles
5
10,000
10,000
cycles
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. The power-off fall-time of V
DD
must be less than 1ms to prevent an overwrite pulse from being generated in the EEPROM which can cause
spurious parasitic writing to EEPROM cells. If the V
DD
power-off full-time is greater than 1ms, a power-off reset signal should be generated
to prevent this condition from occurring.
4. Test condition: T
amb
= +55
C.
5. Number of erase/write cycles for each EEPROM byte.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
14
EXPLANATION OF THE
AC SYMBOLS
Each timing symbol has five characters. The
first character is always `t' (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN
Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t
AVLL
= Time for address valid to
ALE low.
t
LLPL
= Time for ALE low to
PSEN low.
t
PXIZ
Figure 4. External Program Memory Read Cycle
ALE
PSEN
PORT 0
PORT 2
A8A15
A8A15
A0A7
A0A7
t
AVLL
t
PXIX
t
LLAX
INSTR IN
t
PLIV
t
LHLL
t
PLPH
t
LLIV
t
PLAZ
t
LLPL
t
AVIV
t
LLAX
ALE
PSEN
PORT 0
PORT 2
Figure 5. External Data Memory Read Cycle
RD
A0A7
FROM RI OR DPL
DATA IN
A0A7 FROM PCL
INSTR IN
P2.0P2.7 OR A8A15 FROM DPH
A8A15 FROM PCH
t
WHLH
t
LLDV
t
LLWL
t
RLRH
t
RLAZ
t
AVLL
t
RHDX
t
RHDZ
t
AVWL
t
AVDV
t
RLDV
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
15
t
LLAX
Figure 6. External Data Memory Write Cycle
ALE
PSEN
PORT 0
PORT 2
WR
A0A7
FROM RI OR DPL
DATA OUT
A0A7 FROM PCL
INSTR IN
P2.0P2.7 OR A8A15 FROM DPH
A8A15 FROM PCH
t
WHLH
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
t
AW
t
QVWH
Figure 7. Instruction Timing
S1
S2
S3
S4
S5
S6
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
S1
S2
S3
S4
S5
S6
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
XTAL1
INPUT
ALE
PSEN
RD
WR
BUS
PORT 0
PORT 2
(EXTERNAL)
PORT
OUTPUT
PORT
INPUT
SERIAL
PORT
(SHIFT CLOCK)
EXTERNAL
PROGRAM
MEMORY
FETCH
SAMPLING TIME OF I/O PORT PINS DURING INPUT (INCLUDING INT0 AND INT1)
OLD DATA
NEW DATA
ADDRESS TRANSITIONS
DATA
FLOAT
ADDRESS
DATA
FLOAT
ADDRESS
DATA
FLOAT
ADDRESS
FLOAT
FLOAT
FLOAT
FLOAT
ADDRESS
DATA
FLOAT
ONE MACHINE CYCLE
ONE MACHINE CYCLE
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
16
Table 4.
External Clock Drive XTAL1
VARIABLE CLOCK
f = 1.2 16MHz
VARIABLE CLOCK
f = 3.5 24MHz
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
t
CLCL
Oscillator clock period
63
833
42
286
ns
t
HIGH
HIGH time
20
t
CLCL
t
LOW
17
t
CLCL
t
LOW
ns
t
LOW
LOW time
20
t
CLCL
t
HIGH
17
t
CLCL
t
HIGH
ns
t
r
Rise time
20
5
ns
t
f
Fall time
20
5
ns
t
CY
Cycle time
1
0.75
10
0.5
3.43
m
s
NOTE:
1. t
CY
= 12 t
CLCL
.
VDD0.5
0.45V
0.7VDD
0.2VDD0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
Figure 8. External Clock Drive
2.4V
0.45V
2.0V
0.8V
NOTE:
Figure 9. AC Testing Input/Output
AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'.
Timing measurements are made at 2.0V min for a logic `1' and 0.8V for a logic `0'.
VLOAD
VLOAD+0.1V
VLOAD0.1V
VOH0.1V
VOL+0.1V
NOTE:
Figure 10. Float Waveform
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change
from the loaded VOH/VOL level occurs. IOH/IOL
20mA.
Philips Semiconductors
Product specification
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
1998 Jul 03
17
VDD
P0
EA
RST
XTAL1
XTAL2
VSS
VDD
VDD
VDD
IDD
(NC)
CLOCK SIGNAL
Figure 11. I
DD
Test Condition, Active Mode
All other pins are disconnected
VDD
P0
EA
RST
XTAL1
XTAL2
VSS
VDD
VDD
IDD
(NC)
CLOCK SIGNAL
Figure 12. I
DD
Test Condition, Idle Mode
All other pins are disconnected
VDD0.5
0.5V
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
Figure 13. Clock Signal Waveform for I
DD
Tests
in Active and Idle Modes
t
CLCH
= t
CHCL
= 5ns
VDD
P0
EA
RST
XTAL1
XTAL2
VSS
VDD
VDD
IDD
(NC)
Figure 14. I
DD
Test Condition, Power Down Mode
All other pins are disconnected.
V
DD
= 2V to 5.5V
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
Philips Semiconductors
Product specification
80C851/83C851
1998 Jul 03
18
DIP40:
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
Philips Semiconductors
Product specification
80C851/83C851
1998 Jul 03
19
PLCC44:
plastic leaded chip carrier; 44 leads
SOT187-2
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
Philips Semiconductors
Product specification
80C851/83C851
1998 Jul 03
20
QFP44:
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
Philips Semiconductors
Product specification
80C851/83C851
1998 Jul 03
21
NOTES
CMOS single-chip 8-bit microcontroller with on-chip
EEPROM
Philips Semiconductors
Product specification
80C851/83C851
1998 Jul 03
22
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 09-98
Document order number:
9397 750 04368
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.