Philips Semiconductors

Preliminary specification

82B715

C bus extender

1998 Jan 09

DESCRIPTION

The 82B715 is a bipolar integrated circuit intended for application in
I

C bus systems.

While retaining all the operating modes and features of the I

system it permits extension of the practical separation distance
between components on the I

C bus by buffering both the data

(SDA) and the clock (SCL) lines.

The I

C bus capacitance limit of 400pF restricts practical

communication distances to a few meters. Using one 82B715 at
each end of longer cables reduces the cable loading capacitance on
the I

C bus by a factor of 10 times and may allow the use of low

cost general purpose wiring to extend bus lengths.

FEATURES

Dual, bi-directional, unity voltage gain buffer

C bus compatible

Logic signal levels may include both supply and ground

X10 impedance transformation

Wide supply voltage range

PIN CONFIGURATIONS

N.C.

GND

N.C.

VCC

8-Pin Dual In-Line or SO

82B715

SU00290

PINNING

PIN

SYMBOL

FUNCTION

N.C.

Buffered Bus, LDA or LCL

C Bus, SDA or SCL

GND

Negative Supply

N.C.

C Bus, SCL or SDA

Buffered Bus, LCL or LDA

Positive Supply

QUICK REFERENCE DATA

LIMITS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply voltage

4.5

Quiescent current

line

Output sink capability

Input voltage range

out

Output voltage range

out

Impedance transformation

amb

Temperature range

+85

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

DRAWING NUMBER

8-pin plastic dual In-line package

P82B715P N

SOT97-1

8-pin plastic small outline package

P82B715T D

SOT96-1

NOTE:
1. For applications requiring, 3V operation and additional buffer performance, see P82B96 Data Sheet.

Philips Semiconductors

Preliminary specification

82B715

C bus extender

1998 Jan 09

FUNCTIONAL DESCRIPTION

The 82B715 bipolar integrated circuit contains two identical buffer
circuits which enable I

C and similar bus systems to be extended

over long distances without degradation of system performance or
requiring the use of special cables.

The buffer has an effective current gain of ten from I

C bus to

Buffered bus. Whatever current is flowing out of the I

C bus side,

ten times that current will be flowing into the Buffered bus side (see
Figure 2).

As a consequence of this amplification the system is able to drive
capacitive loads up to ten times the standard limit on the Buffered
bus side. This current based buffering approach preserves the
bi-directional, open-collector/open-drain characteristic of the I

SDA/SCL lines.

To minimize interference and ensure stability, current rise and fall
rates are internally controlled.

APPLICATION NOTES

By using two (or more) 82B715 ICs, a sub-system can be built which
retains the interface characteristics of an I

C device so that it may

be included in, or optionally added to, any I

C or related system.

The sub-system features a low impedance or "Buffered" bus,
capable of driving large wiring capacities (see Figure 3).

C Systems

As with the standard I

C system, pull-up resistors are required to

aprovide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I

C bus). The size and number of

these pull-up resistors depends on the system.

If the buffer is to be permanently connected into the system, the
circuit should be configured with only one pull-up resistor on the
Buffered bus and none on the I

C bus.

Alternatively a buffer may be connected to an existing I

C system. In

this case the Buffered bus pull-up will act in parallel with the I

C bus

pull-up.

CURRENT

SENSE

VCC

10 (IB)

BUFFERED BUS
LX

I2C BUS

GND

SU00292

Figure 2. Equivalent Circuit: One Half 82B715

1/2

SDA

SCL

STANDARD

I2C

INTERFACE

BUFFERED

INTERFACE

VCC

LONG

CABLE

1/2

BUFFERED

INTERFACE

LDA

82B715

LCL

SDA

SCL

STANDARD

I2C

INTERFACE

I2C

DEVICE

SU00293

Figure 3. Minimum Sub-System with 82B715

Philips Semiconductors

Preliminary specification

82B715

C bus extender

1998 Jan 09

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND (DIL-8 pin 4).

LIMITS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

to GND

Supply voltage range V

0.3

+12

bus

Voltage range I

C Bus, SCL or SDA

buff

Voltage range Buffered Bus

DC current (any pin)

tot

Power dissipation

300

stg

Storage temperature range

+125

amb

Operating ambient temperature range

+85

CHARACTERISTICS

At T

amb

= +25

C and V

= 5 Volts, unless otherwise specified.

LIMITS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Power Supply

Supply voltage (operating)

4.5

Supply current

Supply current at V

= 12V

Supply current, both I

C inputs LOW,

both buffered outputs sinking 30mA.

Drive Currents

, I

Output sink on I

C bus

, V

LOW = 0.4V

, V

LOW on Buffered bus = 0.3V

, I

Output sink on Buffered bus

, V

LOW = 0.4V

, V

LOW on I

C bus = 0.3V

Input Currents

, I

Input current from I

C bus when

, I

sink on Buffered bus = 30mA

, I

Input current from Buffered bus when

, I

sink on I

C bus = 3mA

, I

Leakage current on Buffered bus

, V

= V

, and V

, V

= V

200

Impedance Transformation

out

Input/Output impedance

Pull-Up Resistance Calculation
In calculating the pull-up resistance values, the gain of the buffer
introduces scaling factors which must be applied to the system
components. Viewing the system from the Buffered bus, all I

C bus

capacitances have effectively 10 times their I

C bus value.

In practical systems the pull-up resistance is determined by the rise
time limit for I

C systems. As an approximation this limit will be

satisfied if the time constant (product of the net resistance and net
capacitance) of the total system is set to 1 microsecond.

The total time constant may either be set by considering each bus
node individually (i.e., the I

C nodes, and the Buffered bus node)

and choosing pull-up resistors to give time constants of 1
microsecond for each node; or by combining the capacitances into
an equivalent capacitive loading on the Buffered bus, and

calculating the Buffered bus pull-up resistor required by this
equivalent capacitance.

For each separate bus the pull-up resistor may be calculated as
follows:

sec

device

)

wiring

Where: C

device

= sum of device capacitances connected to each

bus,

and C

wiring

= total wiring and stray capacitance on each bus.

If these capacitances are not known then a good approximation is to
assume that each device presents 10pF of load capacitance and
10pF of wiring capacitance.

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