Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM

1992 Jan 08

8531463 05128

DESCRIPTION

The 80C562/83C562 (hereafter generically
referred to as 8XC562) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C562/83C562 has the same instruction set
as the 80C51.

The 8XC562 contains a non-volatile 256

read-only program memory, a volatile 256

read/write data memory (83C562) (the
80C562 is ROMless), a volatile 256

read/write data memory, six 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare
latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC,
two pulse width modulated outputs, standard
80C51 UART, a "watchdog" timer and on-chip
oscillator and timing circuits. For systems that
require extra capability, the 83C562 can be
expanded using standard TTL compatible
memories and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 12MHz crystal, 58% of the
instructions are executed in 1

s and 40% in

s. Multiply and divide instructions require

FEATURES

80C51 instruction set

8 ROM expandable externally to

64k bytes

256

8 RAM, expandable externally to

64k bytes

Two standard 16-bit timer/counters

An additional 16-bit timer/counter coupled
to four capture registers and three compare
registers

Capable of producing eight synchronized,
timed outputs

An 8-bit ADC with eight multiplexed analog
inputs

Two 8-bit resolution, pulse width modulated
outputs

Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs

Full-duplex UART compatible with the
standard 80C51

On-chip watchdog timer

Three temperature ranges

0 to +70

40 to +85

40 to +125

PIN CONFIGURATION

Pin

Function

P5.0/ADC0

STADC

PWM0

PWM1

P4.0/CMSR0

P4.1/CMSR1

P4.2/CMSR2

P4.3/CMSR3

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

RST

P1.0/CT0I

P1.1/CT1I

P1.2/CT2I

P1.3/CT3I

P1.4/T2

P1.5/RT2

P1.6

P1.7

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

Pin

Function

XTAL1

P2.0/A08

P2.1/A09

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

AVref

AVref+

P5.7/ADC7

P5.6/ADC6

P5.5/ADC5

P5.4/ADC4

P5.3/ADC3

P5.2/ADC2

P5.1/ADC1

SU00224

PLASTIC

LEADED

CHIP CARRIER

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

ORDERING INFORMATION

PHILIPS PART

ORDER NUMBER

PART MARKING

PHILIPS NORTH AMERICA

PART ORDER NUMBER

TEMPERATURE

RANGE

ROMless

ROM

ROMless

ROM

Drawing

Number

EPROM

Drawing

Number

AND PACKAGE

FREQ

MHz

PCB80C562-
16WP

PCB83C562-
16WP/xxx

S80C562-4A68

S83C562-4A68

SOT188

S87C552-4A68

SOT188-3

0 to +70, Plastic

Leaded Chip Carrier

S87C552-4K68

1473A

0 to +70, Plastic

Leaded Chip Carrier

w/Window

PCF80C562-
12WP

PCF83C562-
12WP/xxx

S80C562-2A68

S83C562-2A68

SOT188

S87C552-5A68

SOT188-3

40 to +85, Plastic

Leaded Chip

Carrier

S87C552-5K68

1473A

40 to +85, Plastic

Leaded Chip Carrier

w/Window

PCA80C562-
12WP

PCA83C562-
12WP/xxx

S80C562-6A68

S83C562-6A68

SOT188

40 to +125, Plastic

Leaded Chip Carrier

NOTES:
1. 80C562 and 83C562 frequency range is 1.2MHz12MHz or 1.2MHz16MHz.
2. 87C552 frequency range is 3.5MHz16MHz. For full specification, see the 87C552 data sheets.
3. xxx denotes the ROM code number.

LOGIC SYMBOL

POR

ADC0-7

CMT0
CMT1

CMSR0-5

RST

XTAL1
XTAL2

ALE

PSEN

AVref+
AVref

STADC

PWM0
PWM1

POR

LOW ORDER

ADDRESS AND

DATA BUS

POR

CT0I
CT1I
CT2I
CT3I
T2
RT2

RxD
TxD

INT0
INT1
T0
T1
WR
RD

VSS
VDD

AVSS

AVDD

HIGH ORDER

ADDRESS AND

DATA BUS

SU00225

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

BLOCK DIAGRAM

CPU

DUAL

PWM

ADC

8-BIT
PORT

80C51 CORE

EXCLUDING

ROM/RAM

8-BIT INTERNAL BUS

TxD

RxD

CT0ICT3I

RT2

CMSR0CMSR5

CMT0, CMT1

RST

XTAL1

XTAL2

ALE

PSEN

INT0

INT1

VDD

VSS

PWM0

PWM1

AVSS

AVDD

AVREF

STADC

ADC07

ALTERNATE FUNCTION OF PORT 0

AD07

A815

PROGRAM

MEMORY

8k x 8 ROM

(83C562)

T0, T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

DATA

MEMORY

256 x 8 RAM

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART
PORT

FOUR

16-BIT

CAPTURE

LATCHES

16-BIT

TIMER/
EVENT

COUNTERS

16-BIT

COMPARATORS

WITH

REGISTERS

COMPARATOR

OUTPUT

SELECTION

WATCHDOG

TIMER

ALTERNATE FUNCTION OF PORT 1

ALTERNATE FUNCTION OF PORT 2

ALTERNATE FUNCTION OF PORT 3

ALTERNATE FUNCTION OF PORT 4

ALTERNATE FUNCTION OF PORT 5

SU00226

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

PIN DESCRIPTION

MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode.

STADC

Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started
by software).

PWM0

Pulse Width Modulation: Output 0.

PWM1

Pulse Width Modulation: Output 1.

Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.

P0.0P0.7

5750

I/O

Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In this application it uses strong internal
pull-ups when emitting 1s.

P1.0P1.7

1623

I/O

Port 1: 8-bit I/O port. Alternate functions include:

1623

I/O

(P1.0P1.7): Quasi-bidirectional port pins.

1619

I/O

CT0ICT3I (P1.0P1.3): Capture timer input signals for timer T2.

T2 (P1.4): T2 event input

RT2 (P1.5): T2 timer reset signal. Rising edge triggered.

P2.0P2.7

3946

I/O

Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08A15).

P3.0P3.7

2431

I/O

Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

RxD(P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0 (P3.2): External interrupt.

INT1 (P3.3): External interrupt.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

P4.0P4.7

714

I/O

Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

712

CMSR0CMSR5 (P4.0P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.

13, 14

CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

P5.0P5.7

6862,

Port 5: 8-bit input port.

ADC0ADC7 (P5.0P5.7): Alternate function: Eight input channels to ADC.

RST

I/O

Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.

XTAL1

Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock signal when an external oscillator is used.

XTAL2

Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left opencircuit when an
external clock is used.

36, 37

Digital ground.

PSEN

Program Store Enable: Active-low read strobe to external program memory.

ALE

Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is
activated every six oscillator periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up.

External Access: When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float.

REF

Analog to Digital Conversion Reference Resistor: Low-end.

REF+

Analog to Digital Conversion Reference Resistor: High-end.

Analog Ground

Analog Power Supply

NOTE:
1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than V

+0.5V or V

0.5V,

respectively.

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To ensure a good power-on reset,
the RST pin must be high long enough to
allow the oscillator time to start up (normally
a few milliseconds) plus two machine cycles.
At power-on, the voltage on V

and RST

must come up at the same time for a proper
start-up.

IDLE MODE

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers

remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. the
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.

Table 1.

External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PWM0/

PWM1

Idle

Internal

Data

High

Idle

External

Float

Data

Address

Data

High

Power-down

Internal

Data

High

Power-down

External

Float

Data

High

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Voltage on any other pin to V

0.5 to +6.5

Input, output DC current on any single I/O pin

5.0

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.0

Storage temperature range

65 to +150

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

DC ELECTRICAL CHARACTERISTICS

, AV

= 0V

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

PCB8XC562

4.0

6.0

PCF8XC562

4.0

6.0

PCA8XC562

4.5

5.5

Supply current operating:

See notes 1 and 2

PCB8XC562

OSC

= 16MHz

PCF8XC562

OSC

= 12MHz

PCA8XC562

OSC

= 12MHz

Idle mode:

See notes 1 and 3

PCB8XC562

OSC

= 16MHz

PCF8XC562

OSC

= 12MHz

PCA8XC562

OSC

= 12MHz

Power-down current:

See notes 1 and 4;

2V < V

< V

max

PCB8XC562

PCF8XC562

PCA8XC562

100

Inputs

Input low voltage, except EA

0.5

0.2V

0.1

IL1

Input low voltage to EA

0.5

0.2V

0.3

Input high voltage, except XTAL1, RST

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

Logical 0 input current, ports 1, 2, 3, 4

= 0.45V

Logical 1-to-0 transition current, ports 1, 2, 3, 4

See note 5

650

IL1

Input leakage current, port 0, EA, STADC, EW

0.45V < V

< V

Outputs

Output low voltage, ports 1, 2, 3, 4

= 1.6mA

0.45

OL1

Output low voltage, port 0, ALE, PSEN, PWM0, PWM1

= 3.2mA

0.45

Output high voltage, ports 1, 2, 3, 4

+ 5V+10%

= 60

2.4

= 25

0.75V

= 10

0.9V

OH1

Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)

+ 5V+10%

= 400

2.4

= 150

0.75V

= 40

0.9V

OH2

Output high voltage (RST)

= 400

2.4

= 120

0.8V

RST

Internal reset pull-down resistor

150

Pin capacitance

Test freq = 1MHz,

amb

= 25

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Analog Inputs

Analog supply voltage:

PCB8XC562

= V

0.2V

4.0

6.0

PCF8XC562

= V

0.2V

4.0

6.0

PCA8XC562

= V

0.2V

4.5

5.5

Analog supply current: operating:

Port 5 = 0 to AV

1.2

Idle mode:

PCB8XC562

PCF8XC562

PCA8XC562

100

Power-down mode:

2V < AV

< AV

max

PCB8XC562

PCF8XC562

PCA8XC562

100

Analog input voltage

0.2

+0.2

REF

Reference voltage:
AV

REF

0.2

REF+

+0.2

REF

Resistance between AV

REF+

and AV

REF

Analog input capacitance

ADS

Sampling time

ADC

Conversion time (including sampling time)

24t

Differential non-linearity

8, 9, 10

LSB

Integral non-linearity

8, 11

LSB

Offset error

8, 12

LSB

Gain error

8, 13

0.4

CTC

Channel to channel matching

LSB

Crosstalk

between inputs of port 5

0100kHz

NOTES:
1. See Figures 8 through 12 for I

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V

; STADC = V

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; Port 0 = EW = V

; EA = RST = STADC = V

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V

;

EA = RST = STADC = XTAL1 = V

5. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

7. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

8. Conditions: AV

REF

= 0V; AV

= 5.0V, AV

REF+

= 5.12V. ADC is monotonic with no missing codes.

9. The differential non-linearity (DL

) is the difference between the actual step width and the ideal step width. (See Figure 1.)

10. The ADC is monotonic; there are no missing codes.
11. The integral non-linearity (IL

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset error. (See Figure 1.)

12. The offset error (OS

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

a straight line which fits the ideal transfer curve. (See Figure 1.)

13. The gain error (G

) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

14. This should be considered when both analog and digital signals are simultaneously input to port 5.

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

AC ELECTRICAL CHARACTERISTICS

1, 2

12MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

1.2

MHz

LHLL

ALE pulse width

127

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

234

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

205

CLCL

PLIV

PSEN low to valid instruction in

145

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

312

CLCL

105

PLAZ

PSEN low to address float

Data Memory

AVLL

3, 4

Address valid to ALE low

CLCL

RLRH

RD pulse width

400

CLCL

100

WLWH

WR pulse width

400

CLCL

100

RLDV

RD low to valid data in

252

CLCL

165

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE low to valid data in

517

CLCL

150

AVDV

Address to valid data in

585

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

200

300

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

203

CLCL

130

QVWX

Data valid to WR transition

CLCL

Data before WR

433

CLCL

150

WHQX

Data hold after WR

CLCL

RLAZ

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

123

CLCL

+40

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always `t' (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN

Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid

to ALE low.

LLPL

= Time for ALE low to

PSEN low.

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0A15

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

SU00006

PLIV

Figure 2. External Program Memory Read Cycle

LLAX

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A0A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

SU00007

Figure 3. External Data Memory Read Cycle

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

LLAX

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA OUT

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A8A15 FROM PCH

WHLH

LLWL

WLWH

AVLL

AVWL

QVWX

WHQX

SU00213

Figure 4. External Data Memory Write Cycle

0.8V

LOW

HIGH

IH1

0.8V

IH1

0.8V

SU00228

Figure 5. External Clock Drive XTAL1

2.4V

0.45V

2.0V

0.8V

NOTE:
AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'.
Timing measurements are made at 2.0V for a logic `1' and 0.8V for a logic `0'.

Test Points

2.0V

0.8V

SU00215

Figure 6. AC Testing Input/Output

2.4V

NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400

A at the voltage test levels.

2.4V

0.45V

Float

2.0V

0.8V

2.0V

0.8V

SU00216

Figure 7. AC Testing Input, Float Waveform

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

f (MHz)

(1)

NOTE:
These values are valid only within the frequency
specifications of the device under test.

IDD mA

(2)

(3)

(4)

(1) Maximum operating mode; VDD = 6V
(2) Maximum operating mode; VDD = 4V
(3) Maximum idle mode; VDD = 6V
(4) Maximum idle mode; VDD = 4V

SU00229

Figure 8. Supply Current (I

) as a Function of Frequency at XTAL1 (f

OSC

)

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

STADC

SU00230

Figure 9. I

Test Condition, Active Mode

All other pins are disconnected

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

STADC

AVSS

AVref

SU00231

Figure 10. I

Test Condition, Idle Mode

All other pins are disconnected

Philips Semiconductors

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

1992 Jan 08

1473A

68-PIN CERQUAD J-BEND (K) PACKAGE

NOTES:

All dimensions and tolerances to conform

UV window is optional.

Dimensions do not include glass protrusion.

Glass protrusion to be 0.005 inches maximum

Controlling dimension millimeters.

All dimensions and tolerances include

lead trim of

fset and lead plating finish.

Backside solder relief is optional and

dimensions are for reference only

1.02 (0.040) X 45

24.51 (0.965)

23.62 (0.930)

25.27 (0.995)

25.02 (0.985)

CHAMFER

24.51 (0.965)

23.62 (0.930)

25.27 (0.995)

25.02 (0.985)

on each side.

to ANSI

Y14.51982.

3 X 0.63 (0.025) R MIN.

3.05 (0.120)

2.29 (0.090)

4.83 (0.190)

3.94 (0.155)

SEA

TING

PLANE

0.38 (0.015)

0.51 (0.02) X 45

25.27 (0.995)

25.02 (0.985)

1.27 (0.050)

20.32 (0.800) NOMINAL

1.94 (0.470)

1.18 (0.440)

1.94 (0.470)

1.18 (0.440)

64X

4.83 (0.190)

3.94 (0.155)

SEA

TING

PLANE

0.15 (0.006) MIN.

0.25 (0.010) R MIN.

0.508 (0.020) R MIN.

0.25 (0.010)

0.15 (0.006)

+ 5

°°

0.076 (0.003) MIN.

DET

AIL

mm/(inch)

SEE DET

AIL

SEE DET

AIL

DET

AIL

TYP

. ALL

SIDES

mm/(inch)

1.52 (0.060) REF

0.482 (0.019 + 0.002)

SEA

TING

PLANE

1.02 + 0.25 (0.040 + 0.010)

BASE PLANE

TYP

4 PLACES

0.73 + 0.08 (0.029 + 0.003)

1.27 (0.050)

TYP

853-1473A 05854

Philips Semiconductors Microcontroller Products

Product specification

80C562/83C562

Single-chip 8-bit microcontroller

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 83C562

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 83C562