Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

853-1690 19336

DESCRIPTION

The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51. Three versions of the derivative exist:

83C552--8k bytes mask programmable ROM

80C552--ROMless version of the 83C552

87C552--8k bytes EPROM

The 87C552 contains a 8k

8 a volatile 256

8 read/write data

memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I

C-bus), a "watchdog" timer and on-chip

oscillator and timing circuits. For systems that require extra
capability, the 87C552 can be expanded using standard TTL
compatible memories and logic.

In addition, the 87C552 has two software selectable modes of power
reduction--idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.

The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75

s and 40% in 1.5

Multiply and divide instructions require 3

FEATURES

80C51 central processing unit

8 EPROM expandable externally to 64k bytes

An additional 16-bit timer/counter coupled to four capture registers
and three compare registers

Two standard 16-bit timer/counters

256

8 RAM, expandable externally to 64k bytes

Capable of producing eight synchronized, timed outputs

A 10-bit ADC with eight multiplexed analog inputs

Two 8-bit resolution, pulse width modulation outputs

Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs

C-bus serial I/O port with byte oriented master and slave

functions

Full-duplex UART compatible with the standard 80C51

On-chip watchdog timer

16MHz speed

Extended temperature ranges

OTP package available

ORDERING INFORMATION

EPROM

TEMPERATURE

C AND PACKAGE

FREQ

MHz

DRAWING NUMBER

S87C552-4A68

0 to +70, Plastic Leaded Chip Carrier

SOT188-3

S87C552-4BA

0 to +70, Plastic Quad Flat Pack

SOT318-2

S87C552-5A68

40 to +85, Plastic Leaded Chip Carrier

SOT188-3

NOTE:
1. For ROM and ROMless see data sheet 80C552/83C552

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

BLOCK DIAGRAM

CPU

ADC

8-BIT INTERNAL BUS

TxD

RxD

CT0I-CT3I

RT2

CMSR0-CMSR5

CMT0, CMT1

RST

XTAL1

XTAL2

ALE

PSEN

INT0

INT1

VDD

VSS

PWM0

PWM1

AVSS

AVDD

AVREF

STADC

ADC0-7 SDA

SCL

ALTERNATE FUNCTION OF PORT 0

AD0-7

A8-15

T0, T1

TWO 16-BIT

TIMER/EVENT

COUNTERS

PROGRAM

MEMORY

8k x 8

EPROM

DATA

MEMORY

256 x 8 RAM

DUAL

PWM

SERIAL

I2C PORT

80C51 CORE

EXCLUDING

ROM/RAM

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART
PORT

8-BIT

PORT

FOUR

16-BIT

CAPTURE

LATCHES

16-BIT

TIMER/
EVENT

COUNTERS

16-BIT

COMPARA-

TORS
WITH

REGISTERS

COMPARA-

TOR

OUTPUT

SELECTION

WATCHDOG

TIMER

ALTERNATE FUNCTION OF PORT 1

ALTERNATE FUNCTION OF PORT 2

ALTERNATE FUNCTION OF PORT 3

ALTERNATE FUNCTION OF PORT 4

ALTERNATE FUNCTION OF PORT 5

SU00211

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

LOGIC SYMBOL

POR

ADC0-7

CMT0
CMT1

CMSR0-5

RST

XTAL1
XTAL2

EA/VPP

ALE/PROG

PSEN

AVref+
AVref

STADC

PWM0
PWM1

POR

LOW ORDER

ADDRESS AND

DATA BUS

POR

CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA

RxD/DATA

TxD/CLOCK

INT0
INT1
T0
T1
WR
RD

VSS
VDD

AVSS

AVDD

HIGH ORDER

ADDRESS AND

DATA BUS

SU00210

PIN CONFIGURATIONS

Pin

Function

P5.0/ADC0

STADC

PWM0

PWM1

P4.0/CMSR0

P4.1/CMSR1

P4.2/CMSR2

P4.3/CMSR3

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

RST

P1.0/CT0I

P1.1/CT1I

P1.2/CT2I

P1.3/CT3I

P1.4/T2

P1.5/RT2

P1.6/SCL

P1.7/SDA

Pin

Function

P3.0/RxD

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

P2.0/A08

P2.1/A09

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

Pin

Function

PSEN

ALE/PROG

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

AVref

AVref+

P5.7/ADC7

P5.6/ADC6

P5.5/ADC5

P5.4/ADC4

P5.3/ADC3

P5.2/ADC2

P5.1/ADC1

SU00208

PLASTIC

LEADED

CHIP CARRIER

PLASTIC QUAD FLAT PACK PIN FUNCTIONS

Pin

Function

P4.1/CMSR1

P4.2/CMSR2

P4.3/CMSR3

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

RST

P1.0/CT0I

P1.1/CT1I

P1.2/CT2I

P1.3/CT3I

P1.4/T2

P1.5/RT2

P1.6/SCL

P1.7/SDA

P3.0/RxD

P3.1/TxD

P3.2/INT0

Pin

Function

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

P2.0/A08

P2.1/A09

P2.2/A10

Pin

Function

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

AVref

AVref+

Pin

Function

P5.7/ADC7

P5.6/ADC6

P5.5/ADC5

P5.4/ADC4

P5.3/ADC3

P5.2/ADC2

P5.1/ADC1

P5.0/ADC0

STADC

PWM0

PWM1

P4.0/CMSR0

SU00209

PQFP

NC = Not Connected
IC = Internally Connected (do not use)

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

PIN DESCRIPTION

PIN NO.

MNEMONIC

PLCC

QFP

TYPE

NAME AND FUNCTION

Digital Power Supply: +5V power supply pin during normal operation, idle and
power-down mode.

STADC

Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
be started by software).

PWM0

Pulse Width Modulation: Output 0.

PWM1

Pulse Width Modulation: Output 1.

Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.

P0.0-P0.7

57-50

58-51

I/O

Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.

P1.0-P1.7

16-23

10-17

I/O

Port 1: 8-bit I/O port. Alternate functions include:

16-21

10-15

I/O

(P1.0-P1.5): Quasi-bidirectional port pins.

22-23

16-17

I/O

(P1.6, P1.7): Open drain port pins.

16-19

10-13

CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

T2 (P1.4): T2 event input.

RT2 (P1.5): T2 timer reset signal. Rising edge triggered.

I/O

SCL (P1.6): Serial port clock line I

C-bus.

I/O

SDA (P1.7): Serial port data line I

C-bus.

Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.

P2.0-P2.7

39-46

38-42,

45-47

I/O

Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.

P3.0-P3.7

24-31

18-20,

23-27

I/O

Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

RxD(P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0 (P3.2): External interrupt.

INT1 (P3.3): External interrupt.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

P4.0-P4.7

7-14

80, 1-2

4-8

I/O

Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

7-12

80, 1-2

4-6

CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.

13, 14

7, 8

CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

P5.0-P5.7

68-62,

71-64,

Port 5: 8-bit input port.

ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.

RST

I/O

Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
overflows.

XTAL1

Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external clock signal when an external oscillator is
used.

XTAL2

Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
when an external clock is used.

36, 37

34-36

Digital ground.

PSEN

Program Store Enable: Active-low read strobe to external program memory.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC

PLCC

QFP

TYPE

NAME AND FUNCTION

ALE/PROG

Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG)
during EPROM programming.

EA/V

External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
This pin also receives the 12.75V programming supply voltage (V

) during EPROM

programming.

REF

Analog to Digital Conversion Reference Resistor: Low-end.

REF+

Analog to Digital Conversion Reference Resistor: High-end.

Analog Ground

Analog Power Supply

NOTE:
1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than V

+ 0.5V or V

0.5V,

respectively.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V

and RST must come up at the same time for a proper start-up.

IDLE MODE

In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.

Table 1. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PWM0/

PWM1

Idle

Internal

Data

High

Idle

External

Float

Data

Address

Data

High

Power-down

Internal

Data

High

Power-down

External

Float

Data

High

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

Serial Control Register (S1CON) See Table 2

S1CON (D8H)

CR2

ENS1

STA

STO

CR1

CR0

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 2. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2

CR1

CR0

6MHz

12MHz

16MHz

OSC

DIVIDED BY

62.5

256

224

31.25

62.5

83.3

192

100

160

6.25

12.5

960

100

133

120

100

200

267

0.25 < 62.5

0.5 < 62.5

0.67 < 56

(256 (reload value Timer 1))

0 to 225

0 to 224

0 to 223

Timer 1 in Mode 2.

NOTE:
1. These frequencies exceed the upper limit of 100kHz of the I

C-bus specification and cannot be used in an I

C-bus application.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Storage temperature range

65 to +150

Voltage on EA/V

to V

0.5 to +13

Voltage on any other pin to V

0.5 to +6.5

Input, output DC current on any single I/O pin

5.0

Power dissipation (based on package heat transfer limitations, not device power
consumption)

1.0

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

TYPE

MIN

MAX

MIN

MAX

TEMPERATURE RANGE (

P87C552-4

4.5

5.5

3.5

0 to +70

P87C552-5

4.5

5.5

3.5

40 to +85

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

DC ELECTRICAL CHARACTERISTICS

, AV

= 0V

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply current operating:

See notes 1 and 2

PCA8XC552-5-16

OSC

= 16MHz

Idle mode:

See notes 1 and 3

87C552

OSC

= 16MHz

Power-down current:

See notes 1 and 4;

max

87C552

2V < V

< V

max

Inputs

Input low voltage, except EA, P1.6, P1.7

0.5

0.2V

0.1

IL1

Input low voltage to EA

0.5

0.2V

0.3

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

0.5

0.3V

Input high voltage, except XTAL1, RST

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

0.7V

6.0

Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7

= 0.45V

Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7

See note 6

650

IL1

Input leakage current, port 0, EA, STADC, EW

0.45V < V

< V

IL2

Input leakage current, P1.6/SCL, P1.7/SDA

0V < V

< 6V

0V < V

< 5.5V

IL3

Input leakage current, port 5

0.45V < V

< V

Outputs

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7

= 1.6mA

0.45

OL1

Output low voltage, port 0, ALE, PSEN, PWM0,
PWM1

= 3.2mA

0.45

OL2

Output low voltage, P1.6/SCL, P1.7/SDA

= 3.0mA

0.4

Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA

= 60

2.4

= 25

0.75V

= 10

0.9V

OH1

Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)

= 400

2.4

= 150

0.75V

= 40

0.9V

OH2

Output high voltage (RST)

= 400

2.4

= 120

0.8V

RST

Internal reset pull-down resistor

150

Pin capacitance

Test freq = 1MHz,

amb

= 25

Analog Inputs

Analog supply voltage:

87C552

= V

0.2V

4.5

5.5

Analog supply current: operating:

Port 5 = 0 to AV

1.2

Idle mode:

87C552

Power-down mode:

2V < AV

< AV

max

87C552

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Analog Inputs (Continued)

Analog input voltage

0.2

+0.2

REF

Reference voltage:

REF

0.2

REF+

+0.2

REF

Resistance between AV

REF+

and AV

REF

Analog input capacitance

ADS

Sampling time

ADC

Conversion time (including sampling time)

50t

Differential non-linearity

10, 11, 12

LSB

Integral non-linearity

10, 13

LSB

Offset error

10, 14

LSB

Gain error

10, 15

0.4

Absolute voltage error

10, 16

LSB

CTC

Channel to channel matching

LSB

Crosstalk

between inputs of port 5

0100kHz

NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V

; STADC = V

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; Port 0 = EW = V

; EA = RST = STADC = V

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V

;

EA = RST = STADC = XTAL1 = V

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

C specification, so an input voltage below 1.5V will be recognized as a logic

0 while an input voltage above 3.0V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

is approximately 2V.

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

9. The following condition must not be exceeded: V

0.2V < AV

< V

+ 0.2V.

10. Conditions: AV

REF

= 0V; AV

= 5.0V. Measurement by continuous conversion of AV

= 20mV to 5.12V in steps of 0.5mV, derivating

parameters from collected conversion results of ADC. AV

REF+

(87C552) = 4.977V. ADC is monotonic with no missing codes.

11. The differential non-linearity (DL

) is the difference between the actual step width and the ideal step width. (See Figure 1.)

12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset error. (See Figure 1.)

14. The offset error (OS

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

a straight line which fits the ideal transfer curve. (See Figure 1.)

15. The gain error (G

) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

16. The absolute voltage error (A

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve.

17. This should be considered when both analog and digital signals are simultaneously input to port 5.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

AC ELECTRICAL CHARACTERISTICS

1, 2

12MHz CLOCK

16MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

127

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

234

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

205

143

CLCL

PLIV

PSEN low to valid instruction in

145

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

312

208

CLCL

105

PLAZ

PSEN low to address float

Data Memory

AVLL

3, 4

Address valid to ALE low

CLCL

RLRH

RD pulse width

400

275

CLCL

100

WLWH

WR pulse width

400

275

CLCL

100

RLDV

RD low to valid data in

252

148

CLCL

165

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE low to valid data in

517

350

CLCL

150

AVDV

Address to valid data in

585

398

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

200

300

138

238

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

203

120

CLCL

130

QVWX

Data valid to WR transition

CLCL

Data before WR

433

288

CLCL

150

WHQX

Data hold after WR

CLCL

RLAZ

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

123

103

CLCL

+40

External Clock

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

Serial Timing Shift Register Mode

(Test Conditions: T

amb

= 0

C to +70

C; V

= 0V; Load Capaciatnce = 80pF)

XLXL

Serial port clock cycle time

1.0

0.75

12t

CLCL

QVXH

Output data setup to clock rising edge

700

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

700

492

10t

CLCL

133

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. t

CLCL

= 1/f

OSC

= one oscillator clock period.

CLCL

= 83.3ns at f

OSC

= 12MHz.

CLCL

= 62.5ns at f

OSC

= 16MHz.

4. These values are characterized but not 100% production tested.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

INPUT

OUTPUT

C Interface (Refer to Figure 9)

HD;STA

START condition hold time

14 t

CLCL

> 4.0

LOW

SCL low time

16 t

CLCL

> 4.7

HIGH

SCL high time

14 t

CLCL

> 4.0

SCL rise time

SCL fall time

0.3

< 0.3

SU;DAT1

Data set-up time

250ns

> 20 t

CLCL

SU;DAT2

SDA set-up time (before rep. START cond.)

250ns

> 1

SU;DAT3

SDA set-up time (before STOP cond.)

250ns

> 8 t

CLCL

HD;DAT

Data hold time

0ns

> 8 t

CLCL

SU;STA

Repeated START set-up time

14 t

CLCL

> 4.7

SU;STO

STOP condition set-up time

14 t

CLCL

> 4.0

BUF

Bus free time

14 t

CLCL

> 4.7

SDA rise time

SDA fall time

0.3

< 0.3

NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 62ns (42s) < t

CLCL

< 285ns (16MHz (24Hz) > f

OSC

> 3.5MHz) the SI01

interface meets the I

C-bus specification for bit-rates up to 100 kbit/s.

5. These values are guaranteed but not 100% production tested.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
`t' (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE

P PSEN
Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid to ALE low.

LLPL

= Time for ALE low to PSEN low.

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0A15

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

SU00006

PLIV

Figure 2. External Program Memory Read Cycle

LLAX

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A0A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

SU00007

Figure 3. External Data Memory Read Cycle

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

2.4V

0.45V

2.0V

0.8V

NOTE:
AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'.
Timing measurements are made at 2.0V for a logic `1' and 0.8V for a logic `0'.

Test Points

2.0V

0.8V

SU00215

Figure 7. AC Testing Input/Output

2.4V

NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400

A at the voltage test levels.

2.4V

0.45V

Float

2.0V

0.8V

2.0V

0.8V

SU00216

Figure 8. AC Testing Input, Float Waveform

tRD

tSU;STA

tBUF

tSU;STO

0.7 VCC

0.3 VCC

0.7 VCC

0.3 VCC

tFD

tRC

tFC

tHIGH

tLOW

tHD;STA

tSU;DAT1

tHD;DAT

tSU;DAT2

tSU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition

SU00107A

Figure 9. Timing SIO1 (I

C) Interface

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

f (MHz)

(1)

NOTE:
These values are valid only within the frequency
specifications of the device under test.

IDD mA

(2)

(3)

(4)

(1) Maximum operating mode; VDD = 6V
(2) Maximum operating mode; VDD = 4V
(3) Maximum idle mode; VDD = 6V
(4) Maximum idle mode; VDD = 4V

SU00217

Figure 10. 16MHz Version Supply Current (I

) as a Function of Frequency at XTAL1 (f

OSC)

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6

P1.7

STADC

AVSS

AVref

SU00218

Figure 11. I

Test Condition, Active Mode

All other pins are disconnected

1. Active Mode:

a. The following pins must be forced to V

: EA, RST, Port 0, and EW.

b. The following pins must be forced to V

: STADC, AV

, and AV

ref

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

VDD

P1.6

P1.7

STADC

AVSS

AVref

SU00219

Figure 12. I

Test Condition, Idle Mode

All other pins are disconnected

2. Idle Mode:

a. The following pins must be forced to V

: Port 0 and EW.

b. The following pins must be forced to V

: RST, STADC, AV

,, AV

ref

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

VDD0.5

0.5V

0.7VDD

0.2VDD0.1

CHCL

CLCL

CLCH

CLCX

CHCX

SU00220

Figure 13. Clock Signal Waveform for I

Tests in Active and Idle Modes

CLCH

= t

CHCL

= 5ns

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

VDD

P1.6

P1.7

STADC

AVSS

AVref

SU00221

Figure 14. I

Test Condition, Power Down Mode

All other pins are disconnected. V

= 2V to 5.5V

3. Power Down Mode:

a. The following pins must be forced to V

: Port 0 and EW.

b. The following pins must be forced to V

: RST, STADC, XTAL1, AV

,, AV

ref

, and EA.

c. Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins cannot

exceed the I

OL1

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

EPROM CHARACTERISTICS

The 87C552 is programmed by using a modified Quick-Pulse
Programming

algorithm. It differs from older methods in the value

used for V

(programming supply voltage) and in the width and

number of the ALE/PROG pulses.

The 87C552 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C552 manufactured by
Philips.

Table 3 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 15 and 16. Figure 17 shows the
circuit configuration for normal program memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in
Figure 15. Note that the 87C552 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 15. The code byte to be
programmed into that location is applied to port 0. RST, PSEN, and
pins of ports 2 and 3 specified in Table 3 are held at the "Program
Code Data" levels indicated in Table 3. The ALE/PROG is pulsed
low 25 times as shown in Figure 16.

To program the encryption table, repeat the 25-pulse programming
sequence for addresses 0 through 1FH, using the "Pgm Encryption
Table" levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.

To program the lock bits, repeat the 25-pulse programming
sequence using the "Pgm Lock Bit" levels. After one lock bit is

programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.

Note that the EA/V

pin must not be allowed to go above the

maximum specified V

level for any amount of time. Even a narrow

glitch above that voltage can cause permanent damage to the
device. The V

source should be well regulated and free of glitches

and overshoot.

Program Verification

If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be red is applied to ports 1 and 2 as shown in
Figure 17. The other pins are held at the "Verify Code Data" levels
indicated in Table 3. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.

If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.

Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:

(030H) = 15H indicates manufactured by Philips Components
(031H) = 94H indicates 87C552

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.

Table 3. EPROM Programming Modes

MODE

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

Read signature

Program code data

Verify code data

Pgm encryption table

Pgm lock bit 1

Pgm lock bit 2

NOTES:
1. 0 = Valid low for that pin; 1 = valid high for that pin.
2. V

= 12.75V

0.25V.

3. V

= 5V

10% during programming and verification.

ALE/PROG receives 25 programming pulses while V

is held at 12.75V. Each programming pulse is low for 100

s (

s) and high for a

minimum of 10

Trademark phrase of Intel Corporation.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

amb

= 21

C to +27

C, V

= 5V

10%, V

= 0V

SYMBOL

PARAMETER

MIN

MAX

UNIT

Programming supply voltage

12.5

13.0

Programming supply current

1/t

CLCL

Oscillator frequency

MHz

AVGL

Address setup to PROG low

48t

CLCL

GHAX

Address hold after PROG

48t

CLCL

DVGL

Data setup to PROG low

48t

CLCL

GHDX

Data hold after PROG

48t

CLCL

EHSH

P2.7 (ENABLE) high to V

48t

CLCL

SHGL

setup to PROG low

GHSL

hold after PROG

GLGH

PROG width

110

AVQV

Address to data valid

48t

CLCL

ELQZ

ENABLE low to data valid

48t

CLCL

EHQZ

Data float after ENABLE

48t

CLCL

GHGL

PROG high to PROG low

PROGRAMMING

VERIFICATION

ADDRESS

DATA IN

DATA OUT

LOGIC 1

LOGIC 0

AVQV

EHQZ

ELQV

SHGL

GHSL

GLGH

GHGL

AVGL

GHAX

DVGL

GHDX

P1.0P1.7
P2.0P2.4

PORT 0

ALE/PROG

EA/V

P2.7
ENABLE

SU00020

EHSH

FOR PROGRAMMING VERIFICATION SEE FIGURE 17.
FOR VERIFICATION CONDITIONS SEE TABLE 3.

Figure 18. EPROM Programming and Verification

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Philips Semiconductors

Product specification

87C552

80C51 8-bit microcontroller

8K/256 OTP, 8 channel 10 bit A/D, I

C, PWM, capture/compare, high I/O

1998 May 01

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 05-98

Document order number:

9397 750 05367

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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