Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

FEATURES

Operating power supply voltage range of 2.3 V-5.5 V

5 V tolerant I/Os

Polarity inversion register

Active LOW interrupt output

Low stand-by current

Noise filter on SCL/SDA inputs

No glitch on power-up

Internal power-on reset

16 I/O pins which default to 16 inputs

0 to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA

Offered in three different packages: SO24, TSSOP24, and
HVQFN24

DESCRIPTION

The PCA9535 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion for

C/SMBus applications and was developed to enhance the Philips

family of I

C I/O expanders. The improvements include higher drive

capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power
switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9535 consist of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active HIGH or
Active LOW operation) registers. The system master can enable the
I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding
Input or Output register. The polarity of the read register can be
inverted with the Polarity Inversion Register. All registers can be
read by the system master. Although pin-to-pin and I

C address

compatible with the PCF8575, software changes are required due to
the enhancements and are discussed in Application Note AN469.

The PCA9535 is identical to the PCA9555 except for the removal of
the internal I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW.

The PCA9535 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I

C address and

allow up to eight devices to share the same I

C/SMBus. The fixed

C address of the PCA9535 is the same as the PCA9554 allowing

up to eight of these devices in any combination to share the same
I

C/SMBus.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

24-Pin Plastic SO

-40 to +85

PCA9535D

SOT137-1

24-Pin Plastic TSSOP

-40 to +85

PCA9535PW

SOT355-1

24-Pin Plastic HVQFN

-40 to +85

PCA9535BS

9535

SOT616-1

Standard packing quantities and other packing data are available at www.philipslogic.com/packaging.
I

C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I

C patent.

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

PIN CONFIGURATION -- SO, TSSOP

SU01438

INT

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

SDA

SCL

I/O1.7

I/O1.6

I/O1.5

I/O1.3

I/O1.4

I/O1.2

I/O1.1

I/O1.0

Figure 1. Pin configuration -- SO, TSSOP

PIN CONFIGURATION --HVQFN

su01683

TOP VIEW

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

I/O0.6

I/O0.7

I/O1.0

I/O1.1

I/O1.2

INT

SDA

SCL

Figure 2. Pin configuration -- HVQFN

PIN DESCRIPTION

SO,

TSSOP

PIN

NUMBER

HVQFN

PIN

NUMBER

SYMBOL

FUNCTION

INT

Interrupt output (open drain)

Address input 1

Address input 2

4-1 1

1-8

I/O0.0-I/O0.7

I/O0.0 to I/O0.7

Supply ground

13-20

10-17

I/O1.0-I/O1.7

I/O1.0 to I/O1.7

Address input 0

SCL

Serial clock line

SDA

Serial data line

Supply voltage

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

SIMPLIFIED SCHEMATIC OF I/Os

WRITE PULSE

DATA FROM

SHIFT REGISTER

I/O PIN

WRITE CONFIGURATION

PULSE

INPUT PORT

POLARITY

INVERSION

OUTPUT

PORT

DATA FROM

SHIFT REGISTER

DATA FROM

SHIFT REGISTER

WRITE

POLARITY

PULSE

CONFIGURATION

OUTPUT PORT
REGISTER DATA

INPUT PORT
REGISTER DATA

POLARITY
REGISTER DATA

READ PULSE

SU01682

TO INT

NOTE:

At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input. The input voltage may be raised
above V

to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either V

or V

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

REGISTERS

Command Byte

Command

Register

Input port 0

Input port 1

Output port 0

Output port 1

Polarity inversion port 0

Polarity inversion port 1

Configuration port 0

Configuration port 1

The command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.

Registers 0 and 1 -- Input Port Registers

This register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.

Registers 2 and 3 -- Output Port Registers

bit

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

default

bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

default

This register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.

Registers 4 and 5 -- Polarity Inversion Registers

bit

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

default

bit

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

default

This register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with `1'), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a `0'), the Input Port data polarity is retained.

Registers 6 and 7 -- Configuration Registers

bit

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

default

bit

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

default

This register configures the directions of the I/O pins. If a bit in this
register is set (written with `1'), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with `0'), the corresponding port pin is enabled as
an output. At reset the device's ports are inputs.

POWER-ON RESET

When power is applied to V

, an internal power-on reset holds the

PCA9535 in a reset state until V

has reached V

POR

. At that point,

the reset condition is released and the PCA9535 registers and
SMBus state machine will initialize to their default states.

DEVICE ADDRESS

slave address

su01441

fixed

programmable

R/W

Figure 5. PCA9535 address

BUS TRANSACTIONS

Writing to the port registers

Data is transmitted to the PCA9535 by sending the device address
and setting the least significant bit to a logic 0 (see Figure 5 for
device address). The command byte is sent after the address and
determines which register will receive the data following the
command byte.

The eight registers within the PCA9535 are configured to operate
as four register pairs. The four pairs are Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. After sending data
to one register, the next data byte will be sent to the other register in
the pair (see Figures 6 and 7). For example, if the first byte is sent to
Output Port (register 3), then the next byte will be stored in Output
Port 0 (register 2). There is no limitation on the number of data bytes
sent in one write transmission. In this way, each 8-bit register may
be updated independently of the other registers.

Reading the port registers

In order to read data from the PCA9535, the bus master must first
send the PCA9535 address with the least significant bit set to a
logic 0 (see Figure 5 for device address). The command byte is sent
after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the
least significant bit is set to a logic 1. Data from the register defined
by the command byte will then be sent by the PCA9535 (see
Figures 8 , 9, and 10). Data is clocked into the register on the falling
edge of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data will now reflect the
information in the other register in the pair. For example, if you read
Input Port 1, then the next byte read would be Input Port 0. There is
no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not
acknowledge the data.

Interrupt Output

The open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read (see Figure 9). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read
independently, the interrupt caused by Port 0 will not be cleared by a
read of Port 1 or the other way around.

Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the Input Port register.

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

A1 A0

COMMAND BYTE

acknowledge
from slave

R/W

acknowledge
from slave

acknowledge
from master

DATA

R/W

first byte

at this moment master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter

last byte

SU01463

no acknowledge
from master

slave address

data from upper

or lower byte of

data from lower

or upper byte

of register

slave address

MSB

LSB

MSB

LSB

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8.

READ from register

I0.x

I1.x

I0.x

I1.x

R/W

ACKNOWLEDGE
FROM SLAVE

SCL

SDA

ACKNOWLEDGE
FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SU01464

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9.

READ input port register -- scenario 1

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

TYPICAL APPLICATION

SW02094

I/O

0.0

I/O

0.1

I/O

0.2

I/O

0.3

I/O

0.4

I/O

0.5

SCL

SDA

INT

RESET

MASTER

CONTROLLER

GND

SCL

SDA

PCA9535

SUBSYSTEM 3

(e.g. alarm system)

SUBSYSTEM 2

(e.g. counter)

SUBSYSTEM 1

(e.g. temp sensor)

INT

ALARM

Controlled Switch
(e.g. CBT device)

ENABLE

1.6 k

1.1 k

2 k

NOTE: Device address configured as 0100100 for this example

I/O

0.0

, I/O

0.1

, I/O

0.2

, configured as outputs

I/O

0.3

, I/O

0.4

, I/O

0.5

, configured as inputs

I/O

0.6

, I/O

0.7

, and I/O

1.0

to I/O

1.7

configured as inputs

2 k

INT

I/O

0.6

I/O

0.7

I/O

1.0

I/O

1.1

I/O

1.2

I/O

1.3

I/O

1.4

I/O

1.5

I/O

1.6

I/O

1.7

10 DIGIT

NUMERIC

KEYPAD

Figure 11. Typical application

Minimizing I

when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V

through a resistor as shown in Figure 11. Since the LED acts as a

diode, when the LED is off the I/O V

is about 1.2 V less than V

. The supply current, I

, increases as V

becomes lower than V

and is

specified as

in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or
equal to V

when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows V

less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V

at or above V

and prevents additional supply current consumption when

the LED is off.

LEDx

LED

100 k

SW02086

Figure 12. High value resistor in parallel with the LED

3.3 V

LEDx

LED

SW02087

5 V

Figure 13. Device supplied by a lower voltage

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".

DC CHARACTERISTICS

= 2.3 to 5.5 V; V

= 0 V; T

amb

= -40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

2.3

5.5

Supply current

Operating mode; V

= 5.5 V; no load;

SCL

= 100 kHz; I/O = inputs

135

200

stbl

Standby current

Standby mode; V

= 5.5 V; no load;

= V

; f

SCL

= 0 kHz; I/O = inputs

0.25

stbh

Standby current

Standby mode; V

= 5.5 V; no load;

= V

; f

SCL

= 0 kHz; I/O = inputs

0.25

POR

Power-on reset voltage

No load; V

= V

or V

1.5

1.65

input SCL; input/output SDA

LOW-level input voltage

-0.5

0.3 V

HIGH-level input voltage

0.7 V

5.5

LOW-level output current

= 0.4V

Leakage current

= V

-1

Input capacitance

= V

I/Os

LOW-level input voltage

-0.5

0.8

HIGH-level input voltage

2.0

5.5

= 0.5 V; V

= 2.3-5.5 V; Note 1

8-20

LOW-level output current

= 0.7 V; V

= 2.3-5.5 V; Note 1

10-24

= -8 mA; V

= 2.3 V; Note 2

1.8

= -10 mA; V

= 2.3 V; Note 2

1.7

= -8 mA; V

= 3.0 V; Note 2

2.6

HIGH-level output voltage

= -10 mA; V

= 3.0 V; Note 2

2.5

= -8 mA; V

= 4.75 V; Note 2

4.1

= -10 mA; V

= 4.75 V; Note 2

4.0

Input leakage current

= 5.5 V; V

= V

Input leakage current

= 5.5 V; V

= V

-1

Input capacitance

3.7

Output capacitance

3.7

Interrupt INT

LOW-level output current

= 0.4 V

Select Inputs A0, A1, A2

LOW-level input voltage

-0.5

0.8

HIGH-level input voltage

2.0

5.5

Input leakage current

-1

NOTES:
1. The total current sunk by all I/Os must be limited to 200 mA.
2. The total current sourced by all I/Os must be limited to 160 mA.

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

SDA

SCL

SU01469

HD;STA

LOW

HD;DAT

SU;DAT

HIGH

SU;STA

HD;STA

SU;STD

BUF

Figure 14. Definition of timing

AC CHARACTERISTICS

SYMBOL

PARAMETER

STANDARD MODE

C BUS

FAST MODE

C BUS

UNITS

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL

Operating frequency

100

400

kHz

BUF

Bus free time between STOP and START conditions

4.7

1.3

HD;STA

Hold time after (repeated) START condition

4.0

0.6

SU;STA

Repeated START condition setup time

4.7

0.6

SU;STO

Set-up time for STOP condition

4.0

0.6

VD;ACK

Valid time of ACK condition

0.3

3.45

0.1

0.9

HD;DAT

Data in hold time

VD;DAT

Data out valid time

300

SU;DAT

Data set-up time

250

100

LOW

Clock LOW period

4.7

1.3

HIGH

Clock HIGH period

4.0

0.6

Clock/Data fall time

300

20 + 0.1C

300

Clock/Data rise time

1000

20 + 0.1C

300

Pulse width of spikes that must be suppressed by the input
filters

Port Timing

Output data valid

200

Input data set-up time

150

Input data hold time

Interrupt Timing

Interrupt valid

Interrupt reset

NOTES:
1. C

= total capacitance of one bus line in pF.

2. t

VD;ACK

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

3. t

VD;DAT

= minimum time for SDA data out to be valid following SCL LOW.

4. t

measured from 0.7V

on SCL to 50% I/O output.

Philips Semiconductors

Product data

PCA9535

16-bit I

C and SMBus, low power I/O port with interrupt

2003 Jun 27

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com .

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com .

Koninklijke Philips Electronics N.V. 2003

Date of release: 06-03

Document order number:

9397 750 11681

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

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