Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

DESCRIPTION

The OM5232 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The OM5232 has the same instruction set as
the 80C51.

See also:
OM5202 -- ROMless version

OM5234 -- 16K bytes mask programmable ROM

OM5238 -- 32K bytes mask programmable ROM

This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The OM5232 contains a non-volatile 8k

8 read-only program

memory, a volatile 256

8 read/write data memory, four 8-bit I/O

ports, two 16-bit timer/event counters (identical to the timers of the
80C51), a multi-source, two-priority-level, nested interrupt structure,
UART and on-chip oscillator and timing circuits. For systems that
require extra capability, the OM5232 can be expanded using
standard TTL compatible memories and logic.

The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte and 17 three-byte. With a 16MHz crystal, 58%
of the instructions are executed in 0.75

s and 40% in 1.5

s. Multiply

and divide instructions require 3

FEATURES

80C51 central processing unit

8 ROM, expandable externally to 64k bytes

256

8 RAM, expandable externally to 64k bytes

Two standard 16-bit timer/counters

Four 8-bit I/O ports

Two open drain I/O's (P1.6, P1.7)

Full-duplex UART facilities

Power control modes

Idle mode

Power-down mode

ROM code protection

Extended frequency range: 1.2 to 16 MHz

Operating ambient temperature range: 0 to +70

PIN CONFIGURATIONS

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

P1.7

RD/P3.7

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VDD

DIP

SEE PAGE 2 FOR QFP PIN FUNCTIONS.

QFP

WR/P3.6

(SOT3072)

PART NUMBER SELECTION

PHILIPS PART

ORDER NUMBER

PART MARKING

PACKAGE NUMBER

TEMPERATURE RANGE

PACKAGE

FREQUENCY

MHz

OM5232/FBP/xxx

SOT129

0 to +70, Plastic Dual Inline Package, 40 leads

1.2 to 16

OM5232/FBB/xxx

SOT3072

0 to +70, Plastic Quad Flat Pack, 44 leads

1.2 to 16

NOTE:
1. xxx denotes the ROM code number.

EQUIVALENT TYPES

Details are as specified by the data sheet for the equivalent type:
OM5202 = P80C652 without I

C function.

OM5232 = P83C652 without I

C function.

OM5234 = P83C654 without I

C function.

OM5238 = P83C528 without I

C function.

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

QFP PIN FUNCTIONS

QFP

(SOT3072)

Pin

Function

Pin

Function

Pin

Function

P1.5

SS1

P0.6/AD6

P1.6

P0.5/AD5

P1.7

P2.0/A8

P0.4/AD4

RST

P2.1/A9

P0.3/AD3

P3.0/RxD

P2.2/A10

P0.2/AD2

SS4

P2.3/A11

P0.1/AD1

P3.1/TxD

P2.4/A12

P0.0/AD0

P3.2/INT0

P2.5/A13

P3.3/INT1

P2.6/A14

SS3

P3.4/T0

P2.7/A15

P1.0

P3.5/T1

PSEN

P1.1

P3.6/WR

ALE

P1.2

P3.7/RD

SS2

P1.3

XTAL2

EA/V

P1.4

XTAL1

P0.7/AD7

NOTE:
1. Due to EMC improvements, all V

pins (6, 16, 28, 39) must be

connected to V

LOGIC SYMBOL

POR

ADDRESS

AND

BUS

ADDRESS BUS

VSS

VDD

TERNA

FUNCTIONS

RST

XTAL1

XTAL2

ALE

PSEN

RxD

TxD

INT0
INT1

T0
T1

BLOCK DIAGRAM

64K BYTE BUS

EXPANSION

CONTRTOL

PROG SERIAL PORT
FULL DUPLEX UART

SYNCHRONOUS SHIFT

PROGRAMMABLE I/O

CPU

OSCILLATOR

AND

TIMING

PROGRAM

MEMORY

DATA

MEMORY

(256 x 8 RAM)

TWO 16-BIT

TIMER/EVENT

COUNTERS

XTAL2

XTAL1

FREQUENCY

REFERENCE

INTERNAL

INTERRUPTS

EXTERNAL

INTERRUPTS

CONTROL

PARALLEL PORTS,

ADDRESS/DATA BUS

AND I/O PINS

SERIAL IN

SERIAL OUT

SHARED WITH

PORT 3

(8K x 8 ROM)

INT0

INT1

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

QFP

TYPE

NAME AND FUNCTION

6, 16,

28, 39

Ground: 0V reference. With the QFP package all V

pins (V

SS1

to V

SS4

) must be connected.

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.00.7

3932

3730

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external program and data memory. In this application, it uses
strong internal pull-ups when emitting 1s.

P1.0P1.5

4044,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which
are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I

). Alternate functions

include:

P1.6

I/O

open drain output

P1.7

I/O

open drain output

P2.0P2.7

2128

1825

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
2 pins that are externally being pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I

). Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the
contents of the P2 special function register.

P3.0P3.7

1017

713

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port
3 pins that are externally being pulled low will source current because of the pull-ups. (See DC
Electrical Characteristics: I

). Port 3 also serves the special features of the 80C51 family, as

listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V

permits a power-on reset using only an external capacitor to

ALE

I/O

Address Latch Enable: Output pulse for latching the low byte of the address during an access
to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency. Note that one ALE pulse is skipped during each access to external data memory.

PSEN

Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is
activated twice each machine cycle during fetches from the external program memory. When
executing out of external program memory two activations of PSEN are skipped during each
access to external data memory. PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs
without external pullups.

External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the
internal program memory ROM provided the Program Counter is less than 16384. If during a
RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is
not allowed to float.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:
To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V

+ 0.5V or V

0.5V, respectively.

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

Table 1.

OM5232 Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB

LSB

RESET
VALUE

ACC*

Accumulator

E0H

00H

B Register

F0H

00H

DPTR:

DPH
DPL

Data Pointer
(2 bytes)
Data Pointer High
Data Pointer Low

83H
82H

00H
00H

IE*#

Interrupt Enable

A8H

ES1

ES0

ET1

EX1

ET0

EX0

0x000000B

IP*#

Interrupt Priority

B8H

PS1

PS0

PT1

PX1

PT0

PX0

xx000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*#

Port 1

90H

SDA

SCL

FFH

P2*

Port 2

A0H

A15

A14

A13

A12

A11

A10

FFH

P3*

Port 3

B0H

INT1

INT0

TXD

RXD

FFH

PCON

Power Control

87H

SMOD

GF1

GF0

IDL

0xxx0000B

S0CON*#

Serial 0 Port Control

98H

SM0

SM1

SM2

REN

TB8

RB8

00H

S0BUF#

Serial 0 Data Buffer

99H

xxxxxxxxB

PSW*

Program Status Word

D0H

RS1

RS0

00H

reserved (Note 1)

DAH

00H

Stack Pointer

81H

07H

reserved (Note 1)

DBH

00H

reserved (Note 1)

D9H

F8H

reserved (Note 1)

D8H

00000000B

TCON*

Timer Control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

TH1

Timer High 1

8DH

00H

TH0

Timer High 0

8CH

00H

TL1

Timer Low 1

8BH

00H

TL0

Timer Low 0

8AH

00H

TMOD

Timer Mode

89H

GATE

C/T

GATE

C/T

00H

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

NOTE
1. Reserved for I

C; not supported in OM5232

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

ROM CODE PROTECTION

The OM5232 has an additional security feature. ROM code
protection may be selected by setting a maskprogrammable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
protected and cannot be read out at any time by any test mode or by
any instruction in the external program memory space.

The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is "don't care" after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 2.

To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V

and RST must come up at the same time for a proper start-up.

Idle Mode

In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 2 shows the state of the I/O ports during low current
operating modes.

Table 2.

External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Serial Control Register (S1CON) See Table 3

CR2

ENS1

STA

STO

CR1

CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3.

Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2

CR1

CR0

6MHz

12MHz

16MHz

OSC

DIVIDED BY

62.5

256

224

31.25

62.5

83.3

192

100

160

6.25

12.5

960

100

133

120

100

200

267

0.24 < 62.5

0 to 255

0.49 < 62.5

0 to 254

0.65 < 55.6

0 to 253

(256 (reload value Timer 1))

reload value range Timer 1 (in mode 2)

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Storage temperature range

65 to +150

Voltage on any other pin to V

0.5 to + 6.5

Input, output current on any single pin

Power dissipation (based on package heat transfer limitations, not device power consumption)

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise

noted.

(1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax

fXTAL1 (MHz)

IDD

(mA)

Figure 1. I

vs. Frequency

(2)

(1)

These values are valid within the specified
frequency range.

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

DC ELECTRICAL CHARACTERISTICS

= 0V, V

= 5.0V

10%. Operating temperature range 0 to 70

TEST

LIMITS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Input low voltage,
except EA, P1.6, P1.7

0.5

0.2V

0.1

IL1

Input low voltage to EA

0.5

0.2V

0.3

IL2

Input low voltage to P1.6, P1.7

0.5

0.3V

Input high voltage, except XTAL1, RST, P1.6, P1.7

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

IH2

Input high voltage, P1.6, P1.7

0.7V

6.0

Output low voltage, ports 1, 2, 3, except P1.6, P1.7

= 1.6mA

7), 8)

0.45

OL1

Output low voltage, port 0, ALE, PSEN

= 3.2mA

7), 8)

0.45

OL2

Output low voltage, P1.6, P1.7

= 3.0mA

0.4

Output high voltage, ports 1, 2, 3, ALE, PSEN

= 60

2.4

= 25

0.75V

= 10

0.9V

OH1

Output high voltage; port 0 in external bus mode

= 800

2.4

= 300

0.75V

= 80

0.9V

Logical 0 input current, ports 1, 2, 3, except P1.6, P1.7

= 0.45V

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6, P1.7

See note 6)

650

Input leakage current, port 0, EA

0.45V < V

< V

Input leakage current, P1.6, P1.7

0V < V

< 6.0V

0V < V

< 6.0V

Power supply current:

See note 1)

Active mode @ 16MHz

2), 10)

=6.0V

26.5

Idle mode @ 16MHz

3), 10)

Power down mode

4), 5)

RST

Internal reset pull-down resistor

150

Pin capacitance

Freq.=1MHz

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 9 through 11 for I

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 5ns;

= V

+ 0.5V; V

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V

. See Figure 9.

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 5ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

; EA = RST = V

. See Figure 10.

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

;

EA = RST = V

. See Figure 11.

5. 2V

max.

6. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

8. Under steady state (non-transient) conditions, I

must be externally limited as follows: Maximum I

= 10mA per port pin; Maximum

= 26mA total for Port 0; Maximum I

= 15mA total for Ports 1, 2, and 3; Maximum I

= 71mA total for all output pins. If I

exceeds the

test conditions, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

9. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

10. I

DDMAX

for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I

DDMAX

is given in mA.

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

AC ELECTRICAL CHARACTERISTICS

1, 2

16MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

1.2

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

143

CLCL

PLIV

PSEN low to valid instruction in

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

208

CLCL

105

PLAZ

PSEN low to address float

Data Memory

RLRH

3, 4

RD pulse width

275

CLCL

100

WLWH

3, 4

WR pulse width

275

CLCL

100

RLDV

3, 4

RD low to valid data in

148

CLCL

165

RHDX

3, 4

Data hold after RD

RHDZ

3, 4

Data float after RD

CLCL

LLDV

3, 4

ALE low to valid data in

350

CLCL

150

AVDV

3, 4

Address to valid data in

398

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

138

238

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

120

CLCL

130

QVWX

3, 4

Data valid to WR transition

CLCL

3, 4

Data setup time before WR

288

CLCL

150

WHQX

3, 4

Data hold after WR

CLCL

RLAZ

3, 4

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

103

CLCL

+40

Shift Register

XLXL

Serial port clock cycle time

0.75

12t

CLCL

QVXH

Output data setup to clock rising edge

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

492

10t

CLCL

133

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
`t' (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN

Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid

to ALE low.

LLPL

= Time for ALE low

to PSEN low.

PXIZ

Figure 2. External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

PLIV

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

ALE

PSEN

PORT 0

PORT 2

Figure 3. External Data Memory Read Cycle

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A8A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

LLAX

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

Philips Semiconductors

Product specification

OM5232

CMOS single-chip 8-bit microcontroller

December 1994

VDD0.5

0.45V

0.2VDD+0.9

0.2VDD0.1

NOTE:

AC INPUTS DURING TESTING ARE DRIVEN AT VDD0.5 FOR A LOGIC '1' AND
0.45V FOR A LOGIC '0'. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A
LOGIC '1' AND VIL MAX FOR A LOGIC '0'.

Figure 7. AC Testing Input/Output

VLOAD

VLOAD+0.1V

VLOAD0.1V

VOH0.1V

VOL+0.1V

NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL

> +

20mA.

Figure 8. Float Waveform

TIMING

REFERENCE

POINTS

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

Figure 9. I

Test Condition, Active Mode

All other pins are disconnected

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

P1.6

P1.7

P1.6

P1.7

Figure 10. I

Test Condition, Idle Mode

All other pins are disconnected

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

Figure 11. I

Test Condition, Power Down Mode

All other pins are disconnected. V

= 2V to 5.5V

P1.6

P1.7

NOTE:
*

Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OM5232

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OM5232