1997 Apr 25
3
Philips Semiconductors
Preliminary specification
Matchbox global FM tuner
OM5610
PINNING
FUNCTIONAL DESCRIPTION
The OM5610 is an integrated FM stereo radio circuit
including digital tuning and control functions.
The radio
The radio circuit incorporates a tuned RF stage, a double
balanced mixer, a one-pin oscillator and is designed for
distributed IF ceramic filters. The FM quadrature detector
uses a ceramic resonator.
The PLL stereo decoder incorporates a signal dependent
stereo-blend circuit and a soft-mute circuit.
Tuning
The tuning-concept of Self Tuned Radio (STR) is based on
FUZZY LOGIC: it mimics hand tuning (hand tuning is a
combination of coarse and fine tuning to the qualitatively
best frequency position). As a consequence the tuning
system is very fast.
The tuning algorithm, which is controlled by a sequential
circuit, is completely integrated; so there are only a few
external components needed.
The bus and the microcontroller can be kept very simple.
The bus only consists of three wires (CLCK, DATA and
WREN). The microcontroller must basically give two
instructions:
Preset operation
Search operation.
PIN
DESCRIPTION
1
ground
2
ground
3
WREN
4
CLCK
5
STEREO
6
DATA
7
supply voltage (+5 V)
8
supply voltage (+12 V)
9
audio right output
10
ground
11
audio left output
12
MPX-RDS
P
RESET OPERATION
In preset mode, the microcontroller has to load information
such as frequency band, frequency and mono/stereo. This
information has to be sent via the bus to the tuner.
The internal algorithm controls the tuning sequence as
follows:
1. The information is loaded into a shift register, a
last-station memory and the counter.
2. The Automatic Frequency Control (AFC) is
switched-off.
3. The counter starts counting the frequency and the
tuning voltage is varied until the real frequency roughly
equals the desired frequency.
4. The AFC is then switched on and the real frequency is
more precisely tuned to the actual IF frequency.
5. After the AFC has tuned the real frequency to the
desired frequency an in-lock signal is generated; then
the counter is switched off. In order to get a reliable
in-lock signal, there are two parameters measured: the
field strength and the S-curve.
6. The field strength indicates the strength of the station
and by looking at the S-curve the system can detect an
in-lock situation.
In the event of fading or pulling the in-lock signal becomes
logic 0 and the synthesizer will be switched on again
(maintaining last station) and the algorithm will be
repeated.
S
EARCH OPERATION
During a search operation, the only action the
microcontroller has to take is: sending the desired band
plus the direction and the search sensitivity level to the
tuner. The search operation is performed by the charge
pump until an in-lock signal is generated (combination of
measuring the field strength and the S-curve). By looking
at the S-curve the system can distinguish false in-locks
from real in-locks (false in-locks occur on the wrong slope
of the S-curve). The AFC then fine tunes to the station.
The frequency of the found station will be counted by the
counter and written into the last-station memory and the
shift register of the counter. At this time the frequency is
available in the shift register and can be read by the
microcontroller. The microcontroller decides whether the
frequency is within the desired frequency band. If so, this
frequency can be stored under a preset and if not, a new
search action should be started.
1997 Apr 25
4
Philips Semiconductors
Preliminary specification
Matchbox global FM tuner
OM5610
Description of the bus
The OM5610 radio has a bus which consists of three
wires, as shown in Table 1.
Table 1
Bus signals
These three signals, together with the mono/stereo pin
(STEREO; pin 5), communicate with the microcontroller.
The mono/stereo indicator has two functions, which are
controlled by the CLCK, as shown in Table 2.
SIGNAL
DESCRIPTION
PIN
CLCK
software driven clock input
4
DATA
data input/output
6
WREN
write/read-input
3
Table 2
Bus-clock functions
The OM5610 has a 25-bit shift register; see Table 3 for an
explanation of the shift register bits.
If in search mode no transmitter can be found, all
frequency bits of the shift register are set to logic 0.
The bus protocol is depicted in Figs 2 and 3 and 4.
CLCK
STEREO (PIN 5)
RESULT
LOW
LOW
stereo
LOW
HIGH
mono
HIGH
LOW
tuned
HIGH
HIGH
not tuned
Table 3
Explanation of the shift register bits
BIT
DESCRIPTION
LOGIC STATE
RESULT
S.24 (MSB)
search start/end
0
after a search when a station is found or after a preset
1
during the search action
D.23
search up/down
0
indicates if the radio has to search down
1
indicates if the radio has to search up
M.22
mono/stereo
0
stereo is allowed
1
mono is required (radio switched to forced mono)
B0.21
band
0
selects FM band
B1.20
band
0
selects FM band
P0.19
local/DX
0
local
1
DX
P1.18
not used
0
S0.17
search-level of station
see Table 4
determines the locking field strength during a search
operation
S1.16
15
dummy
0
buffer
F.14 to F.0 (LSB)
frequency
-
determine the tuning frequency of the radio;
see Table 5 for the bit values
1997 Apr 25
5
Philips Semiconductors
Preliminary specification
Matchbox global FM tuner
OM5610
Table 4
Truth table for bits 16 and 17
Table 5
Values for bits F.14 to F.0
Note
1. FM value of the affected oscillators:
a) FM VALUE = FM-RF + FM-IF.
S0.17
S1.16
SEARCH LEVEL FM
(
V)
0
0
>15
1
0
>35
0
1
>75
1
1
>300
BIT
BIT VALUE
FM VALUE
(1)
(kHz)
F.14
2
14
-
F.13
2
13
102400
F.12
2
12
51200
F.11
2
11
25600
F.10
2
10
12800
F.9
2
9
6400
F.8
2
8
3200
F.7
2
7
1600
F.6
2
6
800
F.5
2
5
400
F.4
2
4
200
F.3
2
3
100
F.2
2
2
50
F.1
2
1
25
F.0
2
0
12.5
R
EADING DATA
While WREN is LOW data can be read by the
microcontroller. At a rising edge of the CLCK, data is
shifted out of the register. This data is available from the
point where the CLCK is HIGH until the next rising edge of
the CLCK occurs (see Fig.2).
To read the entire shift register 24 clock pulses are
necessary.
W
RITING DATA
While WREN is HIGH the microcontroller can transmit
data to the OM5610 (hard mute is active). At a rising edge
of the CLCK, the register shifts and accepts one bit into
LSB. At CLCK LOW the microcontroller writes data
(see Fig.3).
To write the entire shift register 25 clock pulses are
necessary.
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