1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

FEATURES

Normal and loop (test) modes

1.2 V GTL (Gunning Transceiver Logic) level compatible
data and clock outputs (low speed interface)

Differential CML (Current-Mode Logic) data and clock
inputs

High input sensitivity (100 mV for the high speed inputs)

Boundary Scan Test (BST) at low speed interface, in
accordance with

"IEEE Std 1149.1-1990"

Low power dissipation (typically 1.45 W).

DESCRIPTION

The OQ2536HP is a 32-channel demultiplexer intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32

78 Mbits/s output

channels. The data and clock outputs on the low speed
interface are GTL compatible, while the high speed data
and clock inputs are CML compatible.

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

OQ2536HP

HLQFP100

plastic heat-dissipating low profile quad flat package; 100 leads; body
14

1.4 mm

SOT470-1

Fig.1 Block diagram.

(1) See Chapter "Pinning" for D0 to D31 pin numbers.

(2) Pins 1, 8, 17, 22, 25, 29, 33, 35, 40 to 50, 52, 55, 58, 61, 64, 67, 78, 82, 91 and 96.

handbook, full pagewidth

ENL

TRST

TMS

TCK

TDI

TDO

CDIV

DIN

DINQ

CIN

CINQ

DLOOP

DLOOPQ

CLOOP

CLOOPQ

DIOA

DIOC

1 : 4 DMUX

DIVIDE BY 4

622 MHz

OQ2536HP

78 MHz

2.5 GHz

BAND GAP

REFERENCE 1

DIVIDE BY 8

BST LOGIC

1 : 8 DMUX

622

Mbits/s

2.5 Gbits/s

Mbits/s

26, 27, 28,
76, 77

13, 14, 36,
37, 63, 85,
86

11, 38, 39,
62, 88

VDD

VCC1

VEE

VCC2

BGCAP1

(2)

(1)

GND

BAND GAP

REFERENCE 2

BGCAP2

REFC

D31

MGK346

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

PINNING

SYMBOL

PIN

TYPE

(1)

DESCRIPTION

GND

ground

D29

78 Mbits/s data output channel for D29

D25

78 Mbits/s data output channel for D25

D21

78 Mbits/s data output channel for D21

D17

78 Mbits/s data output channel for D17

D13

78 Mbits/s data output channel for D13

78 Mbits/s data output channel for D9

GND

ground

78 Mbits/s data output channel for D5

78 Mbits/s data output channel for D1

supply voltage (

4.5 V)

CDIV

78 MHz clock output

CC2

supply voltage (+1.5 V)

CC2

supply voltage (+1.5 V)

D28

78 Mbits/s data output channel for D28

D24

78 Mbits/s data output channel for D24

GND

ground

D20

78 Mbits/s data output channel for D20

D16

78 Mbits/s data output channel for D16

D12

78 Mbits/s data output channel for D12

78 Mbits/s data output channel for D8

GND

ground

78 Mbits/s data output channel for D4

78 Mbits/s data output channel for D0

GND

ground

supply voltage (+3.3 V)

GND

ground

i.c.

internally connected, to be left open-circuit

DIOC

cathode of temperature diode array

DIOA

anode of temperature diode array

GND

ground

BGCAP2

pin for connecting external band gap decoupling capacitor (4

1 : 8 DMUX)

GND

ground

CC2

supply voltage (+1.5 V)

CC2

supply voltage (+1.5 V)

supply voltage (

4.5 V)

supply voltage (

4.5 V)

GND

ground

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

GND

ground

BGCAP1

pin for connecting external band gap decoupling capacitor (1 : 4 DMUX)

GND

ground

DINQ

inverted data input in normal mode

DIN

data input in normal mode

GND

ground

CIN

clock input in normal mode

CINQ

inverted clock input in normal mode

GND

ground

CLOOPQ

inverted clock input from multiplexer IC OQ2535 (loop mode)

CLOOP

clock input from multiplexer IC OQ2535 (loop mode)

GND

ground

supply voltage (

4.5 V)

CC2

supply voltage (+1.5 V)

GND

ground

DLOOP

data input from multiplexer IC OQ2535 (loop mode)

DLOOPQ

inverted data input from multiplexer IC OQ2535 (loop mode)

GND

ground

TRST

test RESET input for BST mode (active LOW)

TMS

test mode select input for BST

TCK

test clock input for BST mode

TDO

serial test data output for BST mode

TDI

serial test data input for BST mode

REFC

pin for connecting external reference decoupling capacitor (for standard TTL
reference)

CC1

supply voltage (+5.0 V)

ENL

loop mode enable input (active LOW)

supply voltage (+3.3 V)

GND

ground

D31

78 Mbits/s data output channel for D31

D27

78 Mbits/s data output channel for D27

SYMBOL

PIN

TYPE

(1)

DESCRIPTION

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

Note

1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.

D23

78 Mbits/s data output channel for D23

GND

ground

D19

78 Mbits/s data output channel for D19

D15

78 Mbits/s data output channel for D15

CC2

supply voltage (+1.5 V)

CC2

supply voltage (+1.5 V)

D11

78 Mbits/s data output channel for D11

supply voltage (

4.5 V)

78 Mbits/s data output channel for D7

78 Mbits/s data output channel for D3

GND

ground

D30

78 Mbits/s data output channel for D30

D26

78 Mbits/s data output channel for D26

D22

78 Mbits/s data output channel for D22

D18

78 Mbits/s data output channel for D18

GND

ground

D14

78 Mbits/s data output channel for D14

D10

78 Mbits/s data output channel for D10

78 Mbits/s data output channel for D6

100

78 Mbits/s data output channel for D2

SYMBOL

PIN

TYPE

(1)

DESCRIPTION

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

FUNCTIONAL DESCRIPTION

The OQ2536HP is a 32-channel demultiplexer, intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32

78 Mbits/s output

channels.

The demultiplexing is performed in two stages.
The 2.5 Gbits/s data channel is first demultiplexed to four
622 Mbits/s data channels. Each of these channels is then
fed to a 1 : 8 demultiplexer to generate 32

78 Mbits/s

output channels.

The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled
(ENL = LOW), inputs DLOOP, DLOOPQ, CLOOP and
CLOOPQ are selected. In normal mode (ENL = HIGH),
inputs DIN, DINQ, CIN and CINQ are selected.

The signal applied to CIN and CINQ is a 2.5 GHz
recovered clock signal, e.g. coming from the OQ2541 data
and clock recovery IC. The clock is divided down to
78 MHz, which is used for receive logic timing and is
available as a GTL compatible output at pin CDIV.

High bit rate stage: 1 : 4 DMUX

The 2.5 Gbits/s data stream is fed into a 1 : 4
demultiplexer to generate four 622 Mbits/s channels.

The input pins DIN, DINQ, DLOOP, DLOOPQ, CIN, CINQ,
CLOOP and CLOOPQ are terminated internally with 50

resistors to GND.

Low bit rate part: 4

1 : 8 DMUX

The four 622 Mbits/s output channels coming from the
high bit rate stage are loaded into four 8-bit shift registers.
The 622 MHz clock for these shift registers comes from the
preceding stage.

The 32 bits contained in the shift registers are loaded into
latches and made available on outputs D0 to D31. These
outputs are 1.2 V GTL compatible and have internal 100

pull up resistors. The 78 MHz clock output, CDIV, has an
internal 50

pull up resistor.

The first serial data bit coming in at DIN or DLOOP is given
out at pin D31 (MSB) and so on.

The data outputs may not always represent four STM
bytes. This is because the internal load pulse for the output
latches is not synchronized to the STM16 frame.

Power supply connections

The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the

IC. If multiple decoupling capacitors are used for a single
supply node, large distance between the capacitances
should be avoided in order to avoid resonance.

To minimize low frequency switching noise in the vicinity of
the OQ2536HP, all power supply lines should be filtered
once by an LC-circuit with a low cutoff frequency
(as shown in the application diagram, Fig.7).

Ground connection

The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
low inductance.

RF connections

A coupled stripline or microstrip with an odd mode
characteristic impedance of 50

(nominal value) should

be used for the RF connections on the PCB.
The connections should be kept as short as possible. This
applies to the CML differential line pairs CIN and CINQ,
DIN and DINQ, CLOOP and CLOOPQ, and DLOOP and
DLOOPQ. In addition, the following lines should not vary in
length by more than 5 mm:

CIN, CINQ, DIN and DINQ

DLOOP, DLOOPQ, CLOOP and CLOOPQ.

Interface to receive logic

The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not exceed 50 mm in length. The parasitic
capacitance of these lines should be as small as possible
(less than 3 pF is desirable).

ESD protection

All pads are protected by ESD protection diodes, with the
exception of the high frequency inputs DIN, DINQ,
DLOOP, DLOOPQ, CIN, CINQ, CLOOP and CLOOPQ.

Cooling

In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
junction to case, R

th j-c

and from junction to ambient, R

th j-a

are given in Chapter "Thermal characteristics". Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.

To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance R is calculated as:

(1)

amb

tot

------------------------

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

where:

= total thermal resistance from junction to ambient

in the application

= junction temperature

amb

= ambient temperature.

As long as R

is greater than R

th j-a

of the OQ2536HP

including environmental conditions like air flow and board
layout, no heatsink is necessary. For example if
T

= 120

C, T

amb

= 70

C and P

tot

= 1.45 W, then:

(2)

which is more than the worst case R

th j-a

= 33 K/W, so no

heatsink is necessary.

Another example; if for safety reasons T

should stay as

low as 110

C, while T

amb

= 85

C and P

tot

= 2 W, then:

(3)

In this case extra cooling is needed. The thermal
resistance of the heatsink is calculated as follows:

(4)

where:

th h-a

= thermal resistance from heatsink to ambient

th c-h

= thermal resistance from case to heatsink

th j-c

= thermal resistance from junction to case,

see Chapter "Thermal characteristics".

120

(

)

1.45

-----------------------------

34.4

K W

[

]

110

(

)

2.0

-----------------------------

12.5

K W

[

]

thh

--------

thj

-----------------

thj

thc

If for instance R

th c-h

= 0.5 K/W and R

th j -a

= 33 K/W then:

(5)

Built in temperature sensor

Three series-connected diodes have been integrated for
measuring junction temperature. The diode array,
accessed by means of the DIOA (anode) and DIOC
(cathode) pins, has a temperature dependency of
approximately

6 mV/

C. With a diode current of 1 mA,

the voltage will be somewhere in the range 1.7 to 2.5 V,
depending on temperature.

Boundary Scan Test (BST) interface

Boundary scan test logic has been implemented for all
digital inputs and outputs on the low frequency interface, in
accordance with

"IEEE Std 1149.1-1990". All scan tests

other than SAMPLE mode are available. The boundary
scan test logic consists of a TAP controller, a BYPASS
register, a 2-bit instruction register, a 32-bit identification
register and a 36-bit boundary scan register (the last two
are combined). The architecture of the TAP controller and
the BYPASS register is in accordance with IEEE
recommendations.
The four command modes, selected be means of the
instruction register, are: EXTEST (00), PRELOAD (01),
IDCODE (10) and BYPASS (11).
All boundary scan test inputs, TDI, TMS, TCK and TRST,
have internal pull up resistors. The maximum test clock
frequency at TCK is 12 MHz.

thh

12.5

-----------

------

3.1

17.0

K W

[

]

Table 1

BST identifier code

Notes

1. LSB is shifted out first on the TDO pin.

2. The manufacturer's code was implemented incorrectly. It should have been 0000 0010 101.

VERSION

2536 (BINARY)

PHILIPS SEMICONDUCTORS

LSB

(1)

0001

00 1001 1110 1000

0000 0011 101

(2)

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

Note

1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values

given in the table are typical values and are measured on a single sided test board with dimensions of
76

114

1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CC1

supply voltage

0.5

+6.0

supply voltage

6.0

+0.5

supply voltage

0.5

+5.0

CC2

supply voltage

0.5

+2.0

DC voltage

pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89,
90, 92 to 95 and 97 to 100

0.0

2.0

pins 53, 54, 56, 57, 59, 60, 65 and 66

1.0

+0.5

pins 68, 69, 70, 72, 73 and 75

0.5

CC1

+ 0.5

pins 30, 34 and 51

0.5

pins 31and 32

0.5

CC1

+ 0.5

DC current

pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89,
90, 92 to 95, and 97 to 100

pin 12

pins 31 and 32

pin 71

tot

total power dissipation

2.6

junction temperature

120

stg

storage temperature

+150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th j-c

thermal resistance from junction to case

2.6

K/W

th j-a

thermal resistance from junction to
ambient

see note 1

airflow = 0 ft/min

K/W

airflow = 100 ft/min

K/W

airflow = 200 ft/min

K/W

airflow = 400 ft/min

K/W

airflow = 600 ft/min

K/W

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

DC CHARACTERISTICS

Typical values at T

amb

= 25

C and at typical supply voltages; minimum and maximum values are valid over the entire

ambient temperature range and supply voltage range.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

General

CC1

supply voltage

4.75

5.0

5.25

supply voltage

4.75

4.5

4.25

supply voltage

3.14

3.3

3.47

CC2

supply voltage

1.1

1.5

1.6

CC1

supply current

170

215

supply current

100

185

CC2

supply current

note 1

190

525

tot

total power dissipation

note 1

1.45

2.6

junction temperature

+120

amb

ambient temperature

+85

TTL input: ENL

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

LOW-level input current

HIGH-level input current

210

TTL inputs: TDI, TCK, TMS and TRST; note 2

LOW-level input voltage

0.4

HIGH-level input voltage

2.0

CML inputs: CIN, CINQ, DIN, DINQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 3

i(p-p)

input voltage (peak-to-peak value)

measurement

system

100

250

500

permitted input offset voltage

+25

I,IQ

input voltages

600

+250

single ended input impedance

for DC signal

TTL output: TDO; note 4

LOW-level output voltage

= 4 mA

0.3

0.5

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

Notes

1. Maximum current I

CC2

and maximum power dissipation P

tot

are worst case figures i.e. data outputs D0 to D31 remain

in LOW state.

2. TDI, TCK, TMS and TRST are connected via 90 k

to V

3. See Fig.3 for symbol definitions.

4. TDO is switched to high impedance state if BST is inactive.

5. Output CDIV has an internal pull-up resistor of 50

to V

CC2

. Outputs D0 to D31 have internal pull-up resistors of

100

to V

CC2

6. The first serial data bit coming in at DIN or DLOOP is given out at D31 (MSB) and so on.

7. The HIGH-level output voltage depends on the supply voltage V

CC2

8. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of

this voltage is approximately

6 mV/K.

HIGH-level output voltage

400

2.4

4.0

output current in high impedance state

Outputs: CDIV and D0 to D31; notes 5 and 6

LOW-level output voltage

Open outputs

0.3

0.4

HIGH-level output voltage; note 7

1.1

1.5

1.6

Temperature diode array

DIOA-DIOC

diode voltage range

(8)

I(d)

= 1 mA

2.1

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fig.3 Logic level symbol definitions for CML.

handbook, full pagewidth

MGK144

VIO

VI(max)

VIQH

VIH

VIQL

VIL

VI(min)

Vi (p-p)

GND

CML INPUT

VOO

VO(max)

VOQH

VOH

VOQL

VOL

VO(min)

Vo (p-p)

GND

CML OUTPUT

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

TIMING

Typical values at T

amb

= 25

C and at typical supply voltages; minimum and maximum values are valid over the entire

ambient temperature range and supply voltage range.

Notes

1. The specified timing characteristics are applicable in both normal and loop modes.

2. A capacitive load of 15 pF was connected at all outputs. An input reference level of 1 V was used.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CML input timing; note 1; Fig.5

clk(CIN)

input clock frequency

2.488

GHz

input data set-up time

140

input data hold time

CIN

clock slew rate

V/ns

TTL output timing; note 2; Fig.6

clk(CDIV)

output clock frequency

clk(CDIV)

= 2.488 GHz

77.76

MHz

CDIV

output clock duty factor

r(CDIV)

output clock rise time

Measured between
10% and 90% levels
of full output swing

2700

f(CDIV)

output clock fall time

1000

r(D0 to D31)

data out rise time

5100

f(D0 to D31)

data out fall time

1000

CDV

clock edge to data valid time

2700

data invalid time

2850

Fig.4 GTL output circuits.

handbook, halfpage

MBK756

VCC2

D0 to D31

GND

100

handbook, halfpage

MBK757

VCC2

CDIV

GND

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

APPLICATION INFORMATION

Fig.7 Application diagram.

(1) V

CC2

pins 13, 14, 36, 37, 63, 85 and 86 should be connected together, and to the filter network.

(2) V

pins 26, 27, 28, 76 and 77 should be connected together, and to the filter network.

(3) V

pins 11, 38, 39, 62 and 8 should be connected together, and to the filter network.

(4) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly

to the PCB ground plane.

handbook, full pagewidth

MGK349

ferrite

bead

ferrite

bead

ferrite

bead

ferrite

bead

100

TMS

TCK

TDO

TDI

DIN

DINQ

CIN

CINQ

DIOA

DLOOP

DLOOPQ

CLOOP

VCC2

CLOOPQ

DLOOP

DLOOPQ

CLOOP

CLOOPQ

RECEIVE LOGIC

BOUNDARY SCAN
TEST EQUIPMENT

micro-

controller

OQ2535

MUX

OQ2541

OQ2536

VEE

GND

DATA AND CLOCK RECOVERY

CLQ

ENL

TRST

(3)

100

VDD

(2)

(1)

100

DIOC

REFC

BGCAP2

33 nF

10 nF

VCC1

VEE

BGCAP1

CDIV

10 nF

D0 to D31

C78

D0 to D31

VEE

(4)

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1998 Mar 10

Philips Semiconductors

Product specification

SDH/SONET STM16/OC48 demultiplexer

OQ2536HP

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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SCA57

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Printed in The Netherlands

425102/200/01/pp20

Date of release: 1998 Mar 10

Document order number:

9397 750 01623

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