2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

FEATURES

Data and clock recovery up to 2.5 Gbits/s

Multirate configurable (155, 622, 1250 or 2500 Mbits/s)

Full ITU-T jitter compliance (G.958 and G.813)

Full Bellcore jitter compliance

Differential data input with 2.5 mV (p-p) typical
sensitivity

Differential Current-Mode Logic (CML) data and clock
outputs with 50

driving capability

Adjustable CML output level

Bypass mode for non SDH/SONET or Gigabit
Ethernet (GE) bit rates

Loop mode for system testing

Bit Error Rate (BER) related Loss Of Signal (LOS)
detection

Few external components needed

Single supply voltage

Power dissipation 400 mW (typical value)

LQFP48 plastic package.

APPLICATIONS

Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems

Data and clock recovery in GE transmission systems

Regenerator and repeater applications

Wavelength conversion regenerator in Dense
Wavelength Division Multiplexing (D)WDM applications.

DESCRIPTION

The OQ2541B is a data and clock recovery IC intended for
use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems. The
circuit recovers data and extracts the clock signal from an
incoming bitstream up to 2.5 Gbits/s.

The OQ2541B can be configured for use in STM1/OC3,
STM4/OC12, STM16/OC48 and GE systems, with full
ITU-T G.958 and G.813 jitter compliance, or Bellcore jitter
compliance, whichever is applicable. The OQ2541B also
features a bypass mode, for non SDH/SONET or
GE bit rates, in which the clock recovery function is
bypassed.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

OQ2541BHP

LQFP48

plastic low profile quad flat package; 48 leads; body 7

1.4 mm

SOT313-2

OQ2541BU

bare die; 2360

2360

380

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

PINNING

SYMBOL

PIN

DESCRIPTION

ENL

loop mode enable input (active LOW)

GND

ground; note 1

CLOOP

clock output in loop mode (differential)

CLOOPQ

inverted clock output in loop mode (differential)

GND

ground; note 1

DLOOP

data output in loop mode (differential)

DLOOPQ

inverted data output in loop mode (differential)

GND

ground; note 1

DREF19

reference frequency select input 1 (see Table 2)

BYPASS

data recovery and clock extraction bypass mode input

GND

ground; note 1

LOCK

phase lock detection output

i.c.

internally connected; note 2

GND

ground; note 1

CAPUPQ

external loop filter capacitor connection

CAPDOQ

external loop filter capacitor return connection

GND

ground; note 1

i.c.

internally connected; note 2

i.c.

internally connected; note 2

GND

ground; note 1

CREF

reference clock input (differential)

CREFQ

inverting reference clock input (differential)

GND

ground; note 1

ALLON

enable all outputs (input active LOW)

EE1

negative supply voltage (

3.3 V); note 3

GND

ground; note 1

DOUT1250

STM mode select input 1 (see Table 3)

DOUT622

STM mode select input 2 (see Table 3)

GND

ground; note 1

DOUT155

STM mode select input 3 (see Table 3)

EE2

negative supply voltage (

3.3 V); note 3

GND

ground; note 1

DIN

data input (differential)

DINQ

inverting data input (differential)

GND

ground; note 1

i.c.

internally connected; note 2

control output for negative power supply

GND

ground; note 1

LOS

loss of signal detection output

i.c.

internally connected; note 2

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Notes

1. All GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected.

2. All pins or pads denoted `i.c.' should not be connected. Connections to these pins or pads degrade device

performance.

3. All V

pins or pads must be bonded; do not leave one single V

pin or pad unconnected.

GND

ground; note 1

DOUT

data output in normal mode (differential)

DOUTQ

inverted data output in normal mode (differential)

GND

ground; note 1

COUT

clock output in normal mode (differential)

COUTQ

inverted clock output in normal mode (differential)

GND

ground; note 1

AREF

reference voltage input for controlling voltage swing on data and clock outputs

SYMBOL

PIN

DESCRIPTION

handbook, full pagewidth

OQ2541BHP

MGT204

i.c.

GND

DINQ

DIN

VEE2

DOUT155

GND

DOUT622

DOUT1250

GND

VEE1

GND

COUTQ

COUT

GND

DOUTQ

DOUT

i.c.

LOS

GND

AREF

GND

CLOOP

CLOOPQ

GND

DLOOP

GND

DREF19

GND

LOCK

DLOOPQ

BYPASS

GND

CAPUPQ

CAPDOQ

GND

i.c.

GND

CREFQ

GND

i.c.

CREF

ENL

ALLON

Fig.2 Pin configuration.

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

FUNCTIONAL DESCRIPTION

The OQ2541B recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuit (see Fig.1). The signal is then fed into the Alexander
phase detector, where the phase of the incoming data
signal is compared with that of the internal clock. If the
signals are out of phase, the phase detector generates
correction pulses (up or down) that shift the phase of the
Voltage Controlled Ring Oscillator (VCRO) output in
discrete amounts (

) until the clock and data signals are

in phase. The technique used is based on principles first
proposed by J.D.H. Alexander, hence the name of the
phase detector.

Data sampling

The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked):

A is the centre of the data bit

T is in the vicinity of the next transition

B is in the centre of the bit following the transition.

If the same level is recorded at both A and B, a transition
has not occurred and no action is taken, regardless of
level T. However, if levels A and B are different, a
transition has occurred and the phase detector uses
level T to determine whether the clock was too early or too
late with respect to the data transition.

If levels A and T are the same but different from level B,
the clock was too early and needs to be slowed down a
little. The Alexander phase detector then generates a
down pulse which stretches a single output pulse from the
ring oscillator by approximately 0.25% which is 1 ps of the
400 ps bit period in the STM16/OC48 mode. This forces
the VCRO to run at a slightly lower frequency for one bit
period. The phase of the clock signal is thus shifted
fractionally with respect to the data signal.

If, on the other hand, levels B and T are the same but
different from level A, the clock was too late and needs to
be speeded up for synchronization. The phase detector
generates an up pulse, forcing the VCRO to run at a
slightly higher frequency (+0.25%) for one bit period. The
phase of the clock signal is shifted with respect to the data
signal (as above, but in the opposite direction). While
making these phase adjustments, only the proportional
path is active. Because the instantaneous frequency of the
VCRO can be changed in one of two discrete steps only
(

0.25%), this type of loop is also known as a Bang/Bang

Phase-Locked Loop (PLL).

If not only the phase but also the frequency of the VCRO
is incorrect, a long train of up or down pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, only the phase needs to be adjusted for
synchronization. The proportional path adjusts the phase
of the clock signal, whereas the integrating path adjusts
the centre frequency.

Frequency window detector

The frequency window detector checks the VCRO
frequency, which has to be within a 1000 ppm (parts per
million) window around the required frequency.

The detector compares the output of frequency divider 2
with the reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz; see Table 2). If the VCRO frequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window. Then,
the phase detector starts acquiring lock again. Due to the
loose coupling of 1000 ppm, the reference frequency does
not need to be highly accurate or stable. Any crystal-based
oscillator that generates a reasonably accurate frequency
(e.g. 100 ppm) will do.

Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers that are capable of driving a 50

load.

RF data and clock input circuit

The schematic of the input circuit is shown in Fig.4.

RF data and clock output circuit

The schematic of the output circuit is shown in Fig.5.

handbook, halfpage

MGK143

DATA

CLOCK

Fig.3 Data sampling.

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

MGL669

VEE

DINQ,
CREFQ

DIN,

CREF

Fig.4 RF data and clock input circuit.

handbook, halfpage

MGL670

VAREF

VEE

DOUTQ, COUTQ

100

DOUT, COUT

Fig.5 RF data and clock output circuit.

Power supply and power control loop

The OQ2541B contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit with a power supply of

4.5 V is illustrated

in Fig.6. Do not omit the 2

resistor in series with the

100 nF decoupling capacitor.

A different configuration could be used, as long as the
power supply rejection ratio is greater than 60 dB for all
frequencies. The inductor is an RF choke with an
impedance greater than 50

at frequencies higher than

2 MHz. Any transistor with a

of approximately 100 and

sufficient current sink capability can be used.

The OQ2541B can also be used with a power supply of

5.0 or

5.2 V. The only adaptation to be made to the

power control circuit is to change the emitter resistor R1
(see Table 1).

Table 1

Value of resistor R1

Output amplitude reference

The voltage swing at the CML compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500

and 16 k

connected between

ground and V

initially fixes this level.

In most applications, the outputs will be DC coupled to a
50

load. The output level regulation circuit will maintain

a 200 mV (p-p) single-ended swing across this load. The
voltage on pin AREF is half the single-ended peak-to-peak
value of the output signal (

100 mV). No adjustments are

necessary with DC coupling.

If the outputs are AC coupled, the voltage on pin AREF is
half the single-ended peak-to-peak value of the output

signal multiplied by a factor

where R

is the external load and R

is the output

impedance of the OQ2541B (100

The resulting output amplitude with the same voltage on
pin AREF is thus different for DC and AC coupled loads.

POWER SUPPLY

RESISTOR R1

4.5 V

6.8

5.0 V

8.2

5.2 V

10.0

--------------------

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

handbook, full pagewidth

R1
6.8

1 k

1
k

(1)

4.5 V

100

100 nF

3.3

MGT205

BAND GAP
REFERENCE

VEE

GND

off chip

on chip

Fig.6 Schematic diagram of OQ2541B power control loop.

(1) L1 = RF choke type Murata BLM21 or equivalent.

If the outputs are AC coupled, the formulae for calculating
the required voltage on pin AREF and the value of the
resistor connected between pins AREF and V

are as

follows:

and:

where R1 = 500

, R2 = 16 k

and V

3.3 V.

To maintain a single-ended swing of 200 mV (p-p) across
a 50

AC-coupled load, the voltage on pin AREF must be

This can be achieved by connecting a 7.3 k

resistor

between pins AREF and V

handbook, halfpage

MGL667

500

16 k

RAREF

VEE

AREF

off chip

on chip

VAREF

GND

Fig.7 Functionality of pin AREF.

AREF

---------------------

0.5V

swing

AREF

----------------

R1
R2

--------

AREF

----------------

------------------------------------------------------------

100 mV

50 + 100

(

)

---------------------------------

300 mV

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

External capacitor for loop filter

The loop filter is an integrator with a built-in capacitance of
2

130 pF. To ensure loop stability while the frequency

window detector is active, an external capacitance of
360 nF (2 times 180 nF parallel) must be connected
between pins CAPUPQ and CAPDOQ.

Loop mode enable

The loop mode is provided for system testing (see Fig.8).

The loop mode is enabled by applying a voltage between

0.8 and +0.8 V (LOW-level TTL) to pin ENL. This selects

the loop mode: the outputs on pins DLOOP, DLOOPQ,
CLOOP and CLOOPQ are switched on.

If a voltage higher than 2.0 V (HIGH-level TTL) or lower
than

2.0 V is applied to pin ENL, then pins DOUT,

DOUTQ, COUT and COUTQ are switched on while
pins DLOOP, DLOOPQ, CLOOP and CLOOPQ are
disabled to minimize power consumption.

All outputs active

All outputs (normal outputs DOUT, DOUTQ, COUT,
COUTQ and loop mode outputs DLOOP, DLOOPQ,
CLOOP and CLOOPQ) can be activated by applying a
voltage lower than

2.0 V or higher than +2.0 V to

pin ALLON. If the voltage on this pin is between

0.8 and +0.8 V, the active outputs can be selected by

pin ENL. The input has the same structure as the
ENL input (see Fig.8).

Bypass mode

The bypass mode is provided to use the OQ2541B at non
standard SDH/SONET or GE bit rates. The data recovery
and clock extraction function can be bypassed if no clock
extraction is needed, or when the bit rate is different from
155, 622, 1250 or 2488 Mbit/s. Here, the incoming data
from DIN and DINQ is directly fed to the RF outputs. Clock
outputs COUT, COUTQ, CLOOP, CLOOPQ and the
LOS detection have no meaning in this mode.

In the bypass mode, the data and clock recovery circuit is
disabled to reduce crosstalk. The bypass mode can be
activated by applying a voltage lower than

2.0 V or higher

than +2.0 V to pin BYPASS. If the voltage on this pin is
between

0.8 and +0.8 V, extracted data and recovered

clock are present on the RF outputs (normal
DCR operation). The input has the same structure as the
ENL input (see Fig.8).

Lock detection

Pin LOCK should be interpreted as an indication of the
presence of the reference clock on pin CREF and of the
proper functioning of the acquisition aid (frequency
window detector).

Pin LOCK is an open-collector TTL output and is to be
pulled up with a 10 k

resistor to a positive supply voltage.

If the VCO frequency is within a 1000 ppm window around
the desired frequency, pin LOCK will stay at a HIGH level.
If no reference clock is present, or the VCO is outside the
1000 ppm window, pin LOCK will be at a LOW level. The
logic level on pin LOCK does not indicate locking of the
PLL to the incoming data; this is indicated by the signal on
pin LOS.

Loss of signal detection

The LOS function is closely related to the functionality of
the Alexander phase detector; see Fig.3 for the meaning
of A, B and T in this section.

The functional description states that the phase detector
does not take any action if the value at sample points
A and B are the same, as there has not been any
transition. However, if levels A and B are the same but
different from level T, this still means there has not been
any transition, but level T has got the wrong level
somehow. This is probably due to noise or bad signal
integrity, which will lead to a bit error. Hence, the
occurrence of this particular situation is an indication of bit
errors. If too many of these bit errors occur per time and
the PLL is gradually losing lock, the LOS alarm is asserted.
The LOS alarm assert level is around BER = 5

and

the de-assert level is around BER = 1

handbook, halfpage

MGT206

DECODER

LOGIC

ENL,

GND

VEE

36 k

ALLON,

BYPASS

off chip

on chip

Fig.8

Input circuit of pins ENL, ALLON and
BYPASS.

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

The LOS function will only work properly if the input signal
is larger than the input offset of the OQ2541B. Otherwise,
the signal will be masked by the input offset and
interpreted as consecutive bits of the same sign, thus
obstructing a proper LOS detection. In practice, an optical
front-end device with a noise level (RMS value) larger than
the specified offset of the OQ2541B will ensure a proper
LOS indication.

The LOS detection is BER related, but neither dependent
on the data stream content nor protocol. Therefore, an
SDH/SONET data stream is not a prerequisite for a proper
LOS function. Since the LOS function of the OQ2541B is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.

Pin LOS is an open-collector TTL compatible output.
A pull-up resistor is to be connected to a positive supply
voltage.

The LOS pin will be at a HIGH level (TTL) if the data signal
is absent on pins DIN and DINQ or if BER > 5

Otherwise, pin LOS will be at a LOW level if
BER < 1

Reference frequency select

A reference clock signal of 19.44 or 38.88 MHz must be
connected to pins CREF and CREFQ. It should be noted
that the reference frequency should be either
39.0625 or 19.53125 MHz in a GE system. Pin DREF19 is
used to select the appropriate output frequency at
frequency divider 2 (see Table 2).

To minimize the adverse influence of reference clock
crosstalk, a differential signal with an amplitude from
75 to 150 mV (p-p) is advised.

Since the reference clock is only used as an acquisition aid
for the PLL of the frequency window detector, the quality
of the reference clock (i.e. phase noise) is not important.
There is no phase noise specification imposed on the
reference clock generator and even frequency stability
may be in the order of 100 ppm. In general, most
inexpensive crystal-based oscillators are suitable.

When the OQ2541B is used in an application with a fixed
reference clock frequency, it is best to connect
pin DREF19 through a short track or a via to the ground
plane or pin V

. If a selectable reference clock frequency

is required in the application, the pin can be controlled
through a low ohmic switching FET, e.g. BSH103 or
equivalent (low R

DSon

Table 2

Reference frequency selection

STM mode selection

The VCRO has a large tuning range. However, the
performance of the OQ2541B is optimized for
SDH/SONET, including GE bit rates.

Due to the nature of the PLL, the wide tuning range is a
necessity for proper lock behaviour over the guaranteed
temperature range, aging and batch to batch spread.

Though it might seem that the OQ2541B is capable of
recovering other bit rates than SDH/SONET and
GE bit rates (STM1/OC3, STM4/OC12, STM16/OC48 and
1250 Mbits/s), the behaviour cannot be guaranteed.

The required SDH/SONET bit rate is selected by
connecting pins DOUT155, DOUT622 and DOUT1250
to ground or to the supply voltage V

(see Table 3):

For STM16/OC48 (2488.32 Mbits/s) operation, all three
pins have to be connected to ground

For GE (1250 Mbits/s) operation, pin DOUT1250 has to
be connected to V

For STM4/OC12 (622.08 Mbits/s) operation,
pins DOUT1250 and DOUT622 have to be connected
to V

(the dividers are daisy chained)

For STM1/OC3 (155,52 Mbits/s) operation, all three pins
have to be connected to V

The connections to V

and ground carry a current of a

few mA and should have low resistance and inductance.
Therefore, short printed-circuit board tracks are
recommended. In some cases, a small decoupling
capacitor (approximately 100 pF) near the selection pins
might be necessary to provide a clean return path for
RF currents.

When the OQ2541B is used in an application with a fixed
data rate, it is best to connect pins DOUT155, DOUT622
and DOUT1250 through a short track or a via to the ground
plane or pin V

. If a selectable bit rate is required in the

application, the pins can be controlled through low-ohmic
switching FETs, e.g. BSH103 or equivalent (low R

DSon

FREQUENCY

(MHz)

DIVISION

FACTOR

LEVEL ON PIN

DREF19

38.88

ground

19.44

128

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Table 3

STM mode select

MODE

BIT RATE

(Mbits/s)

DIVISION

FACTOR

LEVEL ON PIN

DOUT155

DOUT622

DOUT1250

STM1/OC3

155.52

STM4/OC12

622.08

ground

Gigabit Ethernet

1250.00

ground

STM16/OC48

2488.32

ground

Application with positive supply voltage

The versatile design of the OQ2541B also allows it to
operate in a positive supply voltage application, although
some pins have a different mode of operation. This section
deals with these differences and supports the user with
achieving a successful application of the OQ2541B in a
5 V environment.

PPLICATION DIAGRAM

Fig.32 shows a sample application diagram. It should be
noted that all pins GND are now connected to V

and all

pins V

are connected to the regulated voltage from the

power controller.

UTPUT SELECTION

In a positive supply voltage application, the functions of
pins ENL, ALLON and BYPASS are different than in a
negative supply application, see also Table 4.
The functions can be activated by a voltage more than
2.0 V lower than 5.0 V (V

). Preferably, they should be

connected to V

(pin 25), which is approximately 3.3 V

below V

. If the pins do not differ by more than 0.8 V

of V

(5.0 V), the functions are deactivated.

If the pin is connected to GND (0 V) in the negative supply
application, it should now be connected to 5.0 V (the
voltage on pins GND). If the pin is connected to a positive
voltage >0.8 V in the negative supply application, then it
should be connected to V

(pin 25, approximately 3.3 V

below V

). Beware not to connect pins ENL, ALLON or

BYPASS to a voltage lower than that on pin 25, because
this causes serious damage to the OQ2541B.

OSS OF SIGNAL AND LOCK DETECTION

In the negative supply application, pins LOS and LOCK
are open-collector outputs that require pull-up resistors to
a positive supply voltage.

In the positive supply application, the pull-up voltage
needs to be higher than the positive supply voltage and the
signals on pins LOS and LOCK would no longer be
TTL compatible. However, the internal circuit on pins LOS
and LOCK can be used in a current mirror configuration
(see Fig.9). This requires only an external PNP transistor
(e.g. BC857 or equivalent) to mirror the current. A 10 k

pull-down resistor from the collector of the external
transistor to ground yields a TTL compatible signal again,
albeit inverted. Table 5 shows the meaning of the LOS and
LOCK flags, when used in the positive supply application.

CAUTION

Do not connect pins ENL, ALLON or BYPASS to ground,
because this will destroy the IC.

handbook, halfpage

MGL671

GND

BC857

5 V

signal out

LOS,
LOCK

10 k

off chip

on chip

Fig.9

Signal out for LOS and LOCK indications in
a positive supply voltage application.

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Table 4

Output selection in a positive supply voltage application

Table 5

LOS and LOCK indication in a positive supply voltage application

MODE

LEVEL ON PIN

OUTPUT

ENL

ALLON

BYPASS

DLOOP,

DLOOPQ,

CLOOP AND

CLOOPQ

DOUT, DOUTQ,

COUT AND

COUTQ

DCR loop

(5 V)

active

DCR all outputs

3.3 V) V

(5 V)

active

DCR normal

3.3 V) V

(5 V)

active

Bypass loop

(5 V)

3.3 V)

active

Bypass all outputs

3.3 V) V

3.3 V)

active

Bypass normal

3.3 V) V

(5 V)

3.3 V)

active

SIGNAL

DESCRIPTION

LEVEL

TTL

LOS active

loss of signal: BER > 5

0 V (ground)

LOW

LOS inactive

no loss of signal: BER < 1

5 V (V

)

HIGH

LOCK active

reference clock present and VCRO
inside 1000 ppm window

0 V (ground)

LOW

LOCK inactive

no reference clock present or VCRO
outside 1000 ppm window

5 V (V

)

HIGH

IVIDER SETTINGS

The reference frequency dividers and the STM mode
selectors still operate the same in a positive supply voltage
application. The only difference is that pins formerly
connected to ground should now be connected to
V

(5 V). Pins connected to V

should still be connected

to V

because connecting these pins to ground (0 V) will

damage the IC.

INPUT AND OUTPUTS

All RF inputs, outputs and internal signals of the OQ2541B
are referenced to pins GND. In the positive supply voltage
application, this means that all RF signals are referenced
to V

. Therefore, a clean V

rail is of utmost importance

for proper RF performance. The best performance is
obtained when the transmission line reference plane is
also decoupled to V

. Careful design of V

and good

decoupling schemes should be taken into account. While
designing the printed-circuit board, bear in mind that the
V

has become what was formerly ground.

While laying out the application, the return path is the most
important issue to be considered. It is always advised to
carefully examine the current carrying loops in the design.
Care should be taken that low ohmic and low inductance

return paths are available for all frequencies (both of
interest and not of interest). These return paths should
preferably have an enclosed area as small as possible,
both horizontally and vertically (by means of through-holes
or vias). The position of a decoupling capacitor is very
important. A decoupling capacitor at an unfavourable
position could do more damage than completely omitting
the capacitor, while at the right location it might mean the
difference between mediocre results and the ultimate
achievement.

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

HANDLING INSTRUCTIONS

Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the V

and GND pads first, the

remaining pads may then be bonded to their external connections in any order.

THERMAL CHARACTERISTICS

Note

1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided

1.6 mm FR4 epoxy PCB with 35

m thick copper tracks. The measurements are performed in still air.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

negative supply voltage

+0.5

DC voltage on pins

CLOOP, CLOOPQ, DLOOP, DLOOPQ, CREF, CREFQ, DIN, DINQ,
DOUT, DOUTQ, COUT and COUTQ

+0.5

ENL, ALLON, BYPASS, LOCK and LOS

0.5 +5.5

DREF19, DOUT1250, DOUT622, DOUT155, PC and AREF

0.5 +0.5

CAPUPQ and CAPDOQ

+ 0.5

0.5

input current on pins

ENL, ALLON and BYPASS

CREF, CREFQ, DIN and DINQ

+10

tot

total power dissipation

700

amb

ambient temperature

+85

junction temperature

+110

stg

storage temperature

+150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-s)

thermal resistance from junction to solder point

K/W

th(j-a)

thermal resistance from junction to ambient

in free air; note 1

K/W

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

CHARACTERISTICS
V

3.35 V; T

amb

10 to +85

C; typical values measured at T

amb

= 25

C; all voltages are measured with respect

to GND.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

negative supply voltage

see Fig.12; note 1

3.50

3.35

3.10

negative supply current

loaded; see Fig.13

125

160

tot

total power dissipation

400

560

Data and clock inputs: pins DIN, DINQ, CREF and CREFQ

i(p-p)

input voltage
(peak-to-peak value)

measurement system;

see Fig.10; notes 2 and 3

200

450

i(sens)(p-p)

input sensitivity
(peak-to-peak value)

measurement system;

notes 2 and 4

2.5

DC input offset voltage

measurement system

input voltage

measurement system

600

200

+250

input impedance

single-ended; see Fig.4; note 5

Data and clock outputs: pins DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ

o(p-p)

output voltage swing
(peak-to-peak value)

measurement system;

single-ended; see Fig.10

default adjustment; note 6

170

200

210

special adjustment; note 7

400

output voltage

600

output impedance

single-ended

100

r(C)

clock output rise time

differential; 20% to 80%

f(C)

clock output fall time

differential; 20% to 80%

r(D)

data output rise time

differential; 20% to 80%

120

f(D)

data output fall time

differential; 20% to 80%

120

d(D-C)

data-to-clock delay

see Figs. 11 and 14; note 8

220

260

300

Output amplitude adjustment: pin AREF

AREF

output amplitude reference
voltage

floating pin

110

100

Power control output: pin PC

transconductance

mA/V

output current

3.5

Loop mode enable input: pins ENL, ALLON and BYPASS

LOW-level input voltage

0.8

HIGH-level input voltage

see descriptions of ENL,
ALLON and BYPASS

3.3

2.0

5.0

Phase lock indicator: pin LOCK

LOW-level output voltage

note 9

0.6

HIGH-level output voltage

note 9

3.3

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Loss of signal indicator: pin LOS

LOW-level output voltage

note 9

0.6

HIGH-level output voltage

note 9

3.3

assert time

note 10

0.1

das

de-assert time

note 10

BER

assert bit error rate

note 10

BER

das

de-assert bit error rate

note 10

BER

PLL characteristics

acq

acquisition time

CREF = 19.44 MHz

100

200

CREF = 38.88 MHz

200

tol(p-p)

jitter tolerance
(peak-to-peak value)

STM1/OC3 mode; note 11

f = 6.5 kHz

1.5

>2.5

f = 65 kHz

0.15

0.8

f = 1 MHz

0.15

0.8

STM4/OC12 mode; note 11

f = 25 kHz

1.5

>2.5

f = 250 kHz

0.15

0.7

f = 5 MHz

0.15

0.7

STM16/OC48 mode; note 11

f = 100 kHz

1.5

>2.5

f = 1 MHz

0.15

0.4

f = 10 MHz

0.15

0.3

transfer

3 dB corner frequency for jitter
transfer

STM1/OC3 mode; note 11;
see Fig.17

125

180

kHz

STM4/OC12 mode; note 11;
see Fig.19

500

700

kHz

STM16/OC48 mode; note 11;
see Fig.21

1.8

2.8

MHz

gen(p-p)

jitter generation
(peak-to-peak value)

STM1/OC3 mode; note 12

f = 500 Hz to 1.3 MHz

0.04

0.50

f = 12 kHz to 1.3 MHz

0.025

0.10

f = 65 kHz to 1.3 MHz

0.02

0.10

STM4/OC12 mode; note 12

f = 1 kHz to 5 MHz

0.050

0.50

f = 12 kHz to 5 MHz

0.035

0.10

f = 250 kHz to 5 MHz

0.030

0.10

STM16/OC48 mode; note 12

f = 5 kHz to 20 MHz

0.06

0.50

f = 12 kHz to 20 MHz

0.05

0.10

f = 1 to 20 MHz

0.045

0.10

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Notes

1. Typical power supply voltage for the voltage regulator is

4.5 V (see Fig.6).

2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true

differential excitation).

3. The specified input voltage range is the guaranteed and tested range for proper operation; BER < 1

4. In DCR mode, an input sensitivity of 7 mV (p-p) for BER < 1

is guaranteed. The typical input sensitivity for

BER < 1

is 2.5 mV (p-p). In bypass mode, full clipping of the output signal occurs at about 25 mV (p-p),

see Fig.15.

5. CML inputs are terminated internally using on-chip resistors of 50

connected to ground.

6. Output voltage range with default reference voltage on pin AREF (floating).

7. Output voltage range with adjustment of voltage on pin AREF (see Section "Output amplitude reference").

8. Measured with `1010' data pattern, single-ended output signals and rising edges of the signals on

pins COUT to DOUT or pins CLOOP to DLOOP. It should be noted that small deviations of the specified value are
possible if measured differentially.

9. External pull-up resistor of 10 k

connected to supply voltage of 3.3 V.

10. LOS assert or de-assert timing and BER level are for indication only. The values are neither production tested nor

guaranteed.

11. Measured in accordance with ITU specification G.958. Measured with demoboard OM5801 for STM16/OC48,

STM4/OC12 and STM1/OC3. See for more information

"Application note AN96051".

12. Measured in accordance with ITU specification G.813 and 10 dB above the system input sensitivity power level.

Measured with demoboard OM5801 for STM16/OC48, STM4/OC12 and STM1/OC3.

13. TDR is bit rate independent.

gen(rms)

jitter generation (RMS value)

STM1/OC3 mode; note 12

f = 500 Hz to 1.3 MHz

0.005

f = 12 kHz to 1.3 MHz

0.0025

f = 65 kHz to 1.3 MHz

0.002

STM4/OC12 mode; note 12

f = 1 kHz to 5 MHz

0.006

f = 12 kHz to 5 MHz

0.004

f = 250 kHz to 5 MHz

0.004

STM16/OC48 mode; note 12

f = 5 kHz to 20 MHz

0.008

f = 12 kHz to 20 MHz

0.007

f = 1 to 20 MHz

0.0065

TDR

transitionless data run

note 13

2000

bits

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

BONDING PAD LOCATIONS

Table 6

Bonding pad locations.

Note

1. All x and y coordinates represent the position of the

centre of the pad in

m with respect to the centre of the

die (see Fig.33).

SYMBOL

PAD

COORDINATES

(1)

ENL

1017.5

+852.5

GND

1017.5

+697.5

CLOOP

1017.5

+542.5

CLOOPQ

1017.5

+387.5

GND

1017.5

+232.5

DLOOP

1017.5

+77.5

DLOOPQ

1017.5

77.5

GND

1017.5

232.5

DREF19

1017.5

387.5

BYPASS

1017.5

542.5

GND

1017.5

697.5

LOCK

1017.5

852.5

i.c.

852.5

1017.5

GND

697.5

1017.5

CAPUPQ

542.5

1017.5

CAPDOQ

387.5

1017.5

GND

232.5

1017.5

i.c.

77.5

1017.5

i.c.

+77.5

1017.5

GND

+232.5

1017.5

CREF

+387.5

1017.5

CREFQ

+542.5

1017.5

GND

+697.5

1017.5

ALLON

+852.5

1017.5

EE1

+1017.5

852.5

GND

+1017.5

697.5

DOUT1250

+1017.5

542.5

DOUT622

+1017.5

387.5

GND

+1017.5

232.5

DOUT155

+1017.5

77.5

EE2

+1017.5

+77.5

GND

+1017.5

+232.5

DIN

+1017.5

+387.5

DINQ

+1017.5

+542.5

GND

+1017.5

+697.5

i.c.

+1017.5

+852.5

+1017.5

GND

+697.5

+1017.5

LOS

+542.5

+1017.5

i.c.

+387.5

+1017.5

GND

+232.5

+1017.5

DOUT

+77.5

+1017.5

DOUTQ

77.5

+1017.5

GND

232.5

+1017.5

COUT

387.5

+1017.5

COUTQ

542.5

+1017.5

GND

697.5

+1017.5

AREF

852.5

+1017.5

SYMBOL

PAD

COORDINATES

(1)

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Table 7

Physical characteristics of bare die

Thermal considerations

To improve heat transfer away from the product, a large area fill is recommended as a die pad. The die should be
mounted on this with a heat conductive glue. All supply and ground pads must be bonded to ensure good electrical
performance; this also improves heat transfer to the die pad or other copper area fills. The more copper leading away
from the die, the better the heat transport. In turn, this copper should be able to lose its heat to the environment through
radiation, natural convection (unforced airflow over the printed-circuit board) or forced cooling.

NAME

DESCRIPTION

Glass passivation

0.8

m silicon nitride on top of 0.9

m PSG (PhosphoSilicate Glass)

Bonding pad dimension

minimum dimension of exposed metallization is 90

m (pad size = 100

100

Metallization

1.8

m AlCu (1% Cu)

Thickness

380

m nominal

Size

2.360

2.360 mm (5.5696 mm

)

Backing

silicon; electrically connected to V

potential through substrate contacts

Attach temperature

<440

C; recommended die attach is glue

Attach time

<15 s

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction. The

package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 Sep 18

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541BHP; OQ2541BU

DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification

Development

This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.

Preliminary specification

Qualification

This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification

Production

This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all
data sheet limits up to the point of wafer sawing for a
period of ninety (90) days from the date of Philips' delivery.
If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post
packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in
the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability
for device functionality or performance of the die or
systems after third party sawing, handling, packing or
assembly of the die. It is the responsibility of the customer
to test and qualify their application in which the die is used.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825

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South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553

Printed in The Netherlands

403510/300/01/pp

Date of release:

2000 Sep 18

Document order number:

9397 750 06952

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