1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

FEATURES

Data and clock recovery up to 2.5 Gbits/s

Multirate configurable (155, 622, 1250 or 2500 Mbits/s)

Differential data input with 2.5 mV (p-p) typical
sensitivity

Differential Current-Mode Logic (CML) data and clock
outputs with 50

driving capability

Adjustable CML output level

Loop mode for system testing

Bit error rate related loss of signal detection

Few external components needed

Single supply voltage

Power dissipation 350 mW (typical value)

LQFP48 plastic package.

APPLICATIONS

Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems

Data and clock recovery in Gigabit Ethernet (GE)
transmission systems.

DESCRIPTION

The OQ2541 is a data and clock recovery IC intended for
use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems.
The circuit recovers data and extracts the clock signal
from an incoming bitstream up to 2.5 Gbits/s. It can be
configured for use in STM1/OC3, STM4/OC12,
STM16/OC48 and Gigabit Ethernet systems.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

OQ2541HP

LQFP48

plastic low profile quad flat package; 48 leads; body 7

1.4 mm

SOT313-2

OQ2541U

bare die; 2360

2360

380

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

PINNING

SYMBOL

PIN

DESCRIPTION

ENL

loop mode enable input (active LOW)

GND

ground; note 1

CLOOP

clock output in loop mode (differential)

CLOOPQ

inverted clock output in loop mode (differential)

GND

ground; note 1

DLOOP

data output in loop mode (differential)

DLOOPQ

inverted data output in loop mode (differential)

GND

ground; note 1

DREF19

reference frequency select input 1 (see Table 2)

GND

ground; note 1

GND

ground; note 1

LOCK

phase lock detection output

i.c.

internally connected; note 2

GND

ground; note 1

CAPUPQ

external loop filter capacitor connection

CAPDOQ

external loop filter capacitor return connection

GND

ground; note 1

i.c.

internally connected; note 2

i.c.

internally connected; note 2

GND

ground; note 1

CREF

reference clock input (differential)

CREFQ

inverting reference clock input (differential)

GND

ground; note 1

DREF39

reference frequency select input 2 (see Table 2)

EE1

negative supply voltage (

3.3 V); note 3

GND

ground; note 1

DOUT1250

STM mode select input 1 (see Table 3)

DOUT622

STM mode select input 2 (see Table 3)

GND

ground; note 1

DOUT155

STM mode select input 3 (see Table 3)

EE2

negative supply voltage (

3.3 V); note 3

GND

ground; note 1

DIN

data input (differential)

DINQ

inverting data input (differential)

GND

ground; note 1

i.c.

internally connected; note 2

control output for negative power supply

GND

ground; note 1

LOS

loss of signal detection output

i.c.

internally connected; note 2

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Notes

1. ALL GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected.

2. ALL pins or pads denoted `i.c.' should not be connected. Connections to these pins or pads degrade device

performance.

3. ALL V

pins or pads must be bonded; do not leave one single V

pin or pad unconnected.

GND

ground; note 1

DOUT

data output in normal mode (differential)

DOUTQ

inverted data output in normal mode (differential)

GND

ground; note 1

COUT

clock output in normal mode (differential)

COUTQ

inverted clock output in normal mode (differential)

GND

ground; note 1

AREF

reference voltage input for controlling voltage swing on data and clock outputs

SYMBOL

PIN

DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

OQ2541HP

MBH971

i.c.

GND

DINQ

DIN

VEE2

DOUT155

GND

DOUT622

DOUT1250

GND

VEE1

GND

COUTQ

COUT

GND

DOUTQ

DOUT

i.c.

LOS

GND

AREF

GND

ENL

GND

CLOOP

CLOOPQ

GND

DLOOP

GND

DREF19

GND

LOCK

DLOOPQ

GND

CAPUPQ

CAPDOQ

GND

i.c.

GND

CREFQ

GND

DREF39

i.c.

CREF

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

FUNCTIONAL DESCRIPTION

The OQ2541 recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuitry (see Fig.1). The signal is then fed to the Alexander
phase detector where the phase of the incoming data
signal is compared with that of the internal clock. If the
signals are out of phase, the phase detector generates
correction pulses (up or down) that shift the phase of the
Voltage Controlled Ring Oscillator (VCRO) output in
discrete amounts (

) until the clock and data signals are

in phase. The technique used is based on principles first
proposed by J.D.H. Alexander, hence the name of the
phase detector.

Data sampling

The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked):

A is the centre of the data bit

T is in the vicinity of the next transition

B is in the centre of the bit following the transition.

If the same level is recorded at both A and B, a transition
has not occurred and no action is taken regardless of the
level T. However, if levels A and B are different a transition
has occurred and the phase detector uses level T to
determine whether the clock was too early or too late with
respect to the data transition.

If levels A and T are the same, but different from level B,
the clock was too early and needs to be slowed down a
little. The Alexander phase detector then generates a
down pulse which stretches a single output pulse from the
ring oscillator by approximately 0.25% which is 1 ps of the
400 ps bit period in the STM16/OC48 mode. This forces
the VCRO to run at a slightly lower frequency for one bit
period. The phase of the clock signal is thus shifted
fractionally with respect to the data signal.

Fig.3 Data sampling.

handbook, halfpage

MGK143

DATA

CLOCK

If, on the other hand, levels B and T are the same but
different from level A, the clock was too late and needs to
be speeded up for synchronization. The phase detector
generates an up pulse forcing the VCRO to run at a slightly
higher frequency (+0.25%) for one bit period. The phase of
the clock signal is shifted with respect to the data signal (as
above, but in the opposite direction). Only the proportional
path is active while these phase adjustments are being
made. Because the instantaneous frequency of the VCRO
can be changed only in one of two discrete steps
(

0.25%), this type of loop is also known as a Bang/Bang

Phase-Locked Loop (PLL).

If not only the phase but also the frequency of the VCRO
is incorrect, a long train of up or down pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, only the phase will need to be adjusted for
synchronization. The proportional path adjusts the phase
of the clock signal, whereas the integrating path adjusts
the centre frequency.

Frequency window detector

The frequency window detector checks the VCRO
frequency which must be within a 1000 ppm (parts per
million) window around the required frequency.

It compares the output of frequency divider 2 with the
reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz; see Table 2). If the VCRO frequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window.
The phase detector then starts acquiring lock again.
Because of the loose coupling of 1000 ppm, the reference
frequency does not need to be highly accurate or stable.
Any crystal based oscillator that generates a reasonably
accurate frequency (e.g. 100 ppm) will do.

Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers, which are capable of driving a
50

load.

RF data and clock input circuit

The schematic of the input circuit is shown in Fig.4.

RF data and clock output circuit

The schematic of the output circuit is shown in Fig.5.

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Fig.4 RF data and clock input circuit.

MGL669

VEE

DINQ,
CREFQ

DIN,

CREF

Fig.5 RF data and clock output circuit.

handbook, halfpage

MGL670

VAREF

VEE

DOUTQ, COUTQ

100

DOUT, COUT

Power supply and power control loop

The OQ2541 contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit with a power supply of

4.5 V is illustrated

in Fig.6.

A different configuration could be used, as long as the
power supply rejection ratio is greater than 60 dB for all
frequencies. The inductor is a RF choke with an
impedance greater than 50

at frequencies higher than

2 MHz. Any transistor with a

> 100 and enough current

sink capability can be used.

The OQ2541 can also be used with a power supply of

5.0 or

5.2 V. The only adaptation to be made to the

power control circuit is to change the emitter resistor R1
(see Table 1).

Table 1

Value of resistor R1.

POWER SUPPLY

RESISTOR R1

4.5 V

2.0

5.0 V

6.8

5.2 V

8.2

Output amplitude reference

The voltage swing at the CML compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500

and 16 k

connected between

ground and V

initially fixes this level.

In most applications the outputs will be DC-coupled to a
load of 50

. The output level regulation circuit will

maintain a 200 mV (p-p) single-ended swing across this
load. The voltage on pin AREF is half the single-ended
peak-to-peak value of the output signal (

100 mV).

No adjustments are necessary with DC-coupling.

If the outputs are AC-coupled, the voltage on pin AREF is
half the single-ended peak-to-peak value of the output

signal multiplied by a factor

where R

is the external load and R

is the output

impedance of the OQ2541 (100

--------------------

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Fig.6 Schematic diagram of OQ2541 power control loop.

(1) L1 = RF choke type Murata BLM21 or equivalent.

handbook, full pagewidth

R1
2

1 k

1
k

(1)

4.5 V

> 100

100 nF

3.3

MGL732

BAND GAP
REFERENCE

VEE

GND

off chip

on chip

Fig.7 Functionality of pin AREF.

handbook, halfpage

MGL667

500

16 k

RAREF

VEE

AREF

off chip

on chip

VAREF

GND

If the outputs are AC-coupled, the formulae for calculating
the required voltage on pin AREF and the value of the
resistor connected between pins AREF and V

follows:

(1)

and:

(2)

where R1 = 500

, R2 = 16 k

and V

3.3 V.

To maintain a single-ended swing of 200 mV (p-p) across
a 50

AC-coupled load, the voltage on pin AREF must be

This can be achieved by connecting a 7.3 k

resistor

between pins AREF and V

AREF

--------------------

0.5V

swing

AREF

-----------------

R1
R2

--------

AREF

-----------------

----------------------------------------------------------------

100 mV

50 + 100

(

)

-----------------------------------

300 mV

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

External capacitor for loop filter

The loop filter is an integrator with a built-in capacitance of
2

130 pF. An external capacitance of 200 nF must be

connected between pins CAPUPQ and CAPDOQ to
ensure loop stability while the frequency window detector
is active.

Loop mode enable

The loop mode is provided for system testing (see Fig.8).

The loop mode is enabled by applying a voltage lower than
0.8 V (TTL LOW-level) to pin ENL. This selects the loop
mode: the outputs on pins DLOOP, DLOOPQ, CLOOP
and CLOOPQ are switched on.

If a voltage higher than 2.0 V (TTL HIGH-level) is applied
to pin ENL, then pins DOUT, DOUTQ, COUT and COUTQ
are switched on while pins DLOOP, DLOOPQ, CLOOP
and CLOOPQ are disabled to minimize power
consumption.

If pin ENL is connected to V

(

3.3 V), all outputs are

enabled.

Lock detection

Pin LOCK should be interpreted as an indication for the
presence of the reference clock on pin CREF and for
properly functioning of the acquisition aid (frequency
window detector).

Fig.8 Input circuit of pin ENL.

handbook, halfpage

MGL668

DECODER

LOGIC

ENL

GND

VEE

36 k

off chip

on chip

Pin LOCK is an open-collector TTL output and should be
pulled up with a 10 k

resistor to a positive supply voltage.

If the VCO frequency is within a 1000 ppm window around
the desired frequency, pin LOCK will remain at a
HIGH-level. If no reference clock is present, or the VCO is
outside the 1000 ppm window, pin LOCK will be at a
LOW-level. The logic level on pin LOCK does not indicate
locking of the PLL to the incoming data; this is indicated by
the signal on pin LOS.

Loss of signal detection

The Loss Of Signal (LOS) function is closely related to the
functionality of the Alexander phase detector; see Fig.3 for
the meaning of A, B and T in this section.

In the functional description it is described that the phase
detector does not take any action if the value at sample
points A and B are the same, because there has not been
any transition. However, if levels A and B are the same but
different from level T, this still means there has not been
any transition, but level T has got the wrong level
somehow. This is probably due to noise or bad signal
integrity, which will lead to a bit error. Hence the
occurrence of this particular situation is an indication for bit
errors. If too many of these bit errors occur per time and
the PLL is gradually losing lock, the LOS alarm is asserted.
The LOS alarm assert level is around a Bit Error Rate
(BER) for BER = 5

and the de-assert level is around

BER = 1

The LOS function will only work properly if the input signal
is larger than the input offset of the OQ2541; otherwise,
the signal will be masked by the input offset and
interpreted as consecutive bits of the same sign, thus
obstructing a proper LOS detection. In practice an optical
front-end device with a noise level (RMS value) larger than
the specified offset of the OQ2541 will ensure a proper
LOS indication.

The LOS detection is BER related, but neither dependent
on the data stream content, nor protocol. Therefore, an
SDH/SONET data stream is no prerequisite for a proper
LOS function. Since the LOS function of the OQ2541 is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.

Pin LOS is an open-collector TTL compatible output.
A pull-up resistor should be connected to a positive supply
voltage.

Pin LOS will be at a HIGH-level (TTL) if the data signal is
absent on pins DIN and DINQ or if BER > 5

;

otherwise pin LOS will be at a LOW-level if BER < 1

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Reference frequency select

A reference clock signal of 19.44 or 38.88 MHz must be
connected to pins CREF and CREFQ. It should be noted
that the reference frequency should be either
39.0625 MHz or 19.53125 MHz in a Gigabit Ethernet
system. Pins DREF19 and DREF39 are used to select the
appropriate output frequency at frequency divider 2
(see Table 2).

To minimize the adverse influence of reference clock
crosstalk, a differential signal with an amplitude from
75 to 150 mV (p-p) is advised.

Since the reference clock is only used as an acquisition aid
for the PLL of the frequency window detector, the quality
of the reference clock (i.e. phase noise) is not important.
There is no phase noise specification imposed on the
reference clock generator and even frequency stability
may be in the order of 100 ppm. In general, most
inexpensive crystal based oscillators are suitable.

When the OQ2541 is used in an application with a fixed
reference clock frequency, it is best to connect the planes
of pins DREF19 and DREF39 with a short trace or a via to
the plane of pin GND or pin V

. If a selectable reference

clock frequency is required in the application, the pins can
be controlled through low ohmic switching FETs,
e.g. BSH103 or equivalent (low R

DSon

Table 2

Reference frequency selection

STM mode selection

The VCRO has a very large tuning range. However, the
performance of the OQ2541 is optimized for SDH/SONET
bit rates.

FREQUENC

Y (MHz)

DIVISION

FACTOR

LEVEL ON PIN

DREF19

DREF39

38.88

ground

19.44

128

Due to the nature of the PLL, the very wide tuning range is
a necessity for proper lock behaviour over the guaranteed
temperature range, aging and batch to batch spread.

Though it might seem that the OQ2541 is capable of
recovering other bit rates than SDH/SONET and Gigabit
Ethernet rates (STM1/OC3, STM4/OC12, STM16/OC48
and 1250 Mbits/s), the behaviour can not be guaranteed.

The required SDH/SONET bit rate is selected by
connecting pins DOUT155, DOUT622 and DOUT1250
to ground or to the supply voltage V

(see Table 3):

For STM16/OC48 (2488.32 Mbits/s) operation:
all three pins must be connected to ground

For Gigabit Ethernet (1250 Mbits/s) operation:
pin DOUT1250 must be connected to V

For STM4/OC12 (622.08 Mbits/s) operation:
pins DOUT1250 and DOUT622 must be connected to
V

(the dividers are daisy chained)

For STM1/OC3 (155,52 Mbits/s) operation:
all three pins must be connected to V

The connections to V

and ground carry a current of a few

milliamperes and should have low resistance and
inductance, so short printed-circuit board tracks are
recommended. In some cases a decoupling capacitor near
the selection pins can be necessary to provide a clean
return path for RF signals.

When the OQ2541 is used in an application with a fixed
data rate, it is best to connect the planes of
pins DOUT155, DOUT622 and DOUT1250 with a short
trace or a via to the plane of pin GND or pin V

. If a

selectable reference clock frequency is required in the
application, the pins can be controlled through low-ohmic
switching FETs, e.g. BSH103 or equivalent (low R

DSon

Table 3

STM mode select

MODE

BIT RATE

(Mbits/s)

DIVISION

FACTOR

LEVEL ON PIN

DOUT155

DOUT622

DOUT1250

STM1/OC3

155.52

STM4/OC12

622.08

ground

Gigabit Ethernet

1250.00

ground

STM16/OC48

2488.32

ground

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Application with positive supply voltage

Due to the versatile design of the OQ2541 the device can
also operate in a positive supply voltage application,
although some pins have a different mode of operation.

This section deals with these differences and supports the
user with achieving a successful application of the
OQ2541 in a +5 V environment.

PPLICATION DIAGRAM

A sample application diagram can be found in Fig.29.
It should be noted that all pins GND are now connected to
V

and all pins V

are connected to the regulated

voltage from the power controller.

UTPUT SELECTION

In a positive supply voltage application, the loop mode is
the default RF output. Due to the decoding logic on
pin ENL, it is only possible to select the loop mode outputs
or enable all the outputs.

If pin ENL is connected to V

(+5 V), only the loop mode

outputs are active (see Table 4). When pin ENL is
connected to V

(the voltage is approximately 3.3 V

below V

) all outputs become active. In the positive

supply voltage application the normal mode outputs can
not be selected, unless the voltage on pin ENL is 2 V
above the positive supply voltage (V

CAUTION

Do not to connect pin ENL to ground, because this will
destroy the IC.

OSS OF SIGNAL AND LOCK DETECTION

In the negative supply application, pins LOS and LOCK
are open-collector outputs that require pull-up resistors to
a positive supply voltage.

In the positive supply application, the pull-up voltage would
need to be higher then the positive supply voltage and the
signals on pins LOS and LOCK would not be TTL
compatible any more. However, the internal circuit on
pins LOS and LOCK can be used in a current mirror
configuration (see Fig.9). This requires only an external
PNP transistor (e.g. BC857 or equivalent) to mirror the
current. A 10 k

pull-down resistor from the collector of the

external transistor to ground yields a TTL compatible
signal again, albeit inverted. Table 5 shows the meaning of
the LOS and LOCK flag, when used in the positive supply
application.

Fig.9

Signal out for LOS and LOCK indication in a
positive supply voltage application.

handbook, halfpage

MGL671

GND

BC857

5 V

signal out

LOS,
LOCK

10 k

off chip

on chip

Table 4

Output selection in a positive supply voltage application

Table 5

LOS and LOCK indication in a positive supply voltage application

MODE

LEVEL ON PIN ENL

OUTPUT

DLOOP, DLOOPQ,

CLOOP AND CLOOPQ

DOUT, DOUTQ,

COUT AND COUTQ

Loop

(+5 V)

active

Loop and normal

3.3 V)

active

Normal

+ 2 V

active

SIGNAL

DESCRIPTION

LEVEL

TTL

LOS active

loss of signal: BER > 5

0 V (ground)

LOW

LOS inactive

no loss of signal: BER < 1

+5 V (V

)

HIGH

LOCK active

reference clock present and VCRO inside 1000 ppm window

0 V (ground)

LOW

LOCK inactive

no reference clock present or VCRO outside 1000 ppm window

+5 V (V

)

HIGH

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

IVIDER SETTINGS

The reference frequency dividers and the STM mode
selectors still operate the same in a positive supply voltage
application. The only difference is that pins formerly
connected to ground should now be connected to V

(+5 V). Pins connected to V

should still be connected to

because connecting these pins to ground (0 V) will

damage the IC.

INPUT AND OUTPUTS

All RF inputs, outputs and internal signals of the OQ2541
are referenced to pins GND. In the positive supply voltage
application, this means that all RF signals are referenced
to V

. Therefore a clean V

rail is of ultimate importance

for proper RF performance. The best performance is
obtained when the transmission line reference plane is
also decoupled to V

. Careful design of V

and good

decoupling schemes should be taken into account. While
designing the printed-circuit board, bear in mind that the
V

has become what was formerly ground.

While laying out the application, the return path is the most
important issue to be considered. It is always advised to
examine carefully the current carrying loops in the design.
Care should be taken that for all frequencies (both of
interest and not of interest) low ohmic and low inductance
return paths are available. These return paths should
preferably have an enclosed area as small as possible,
both horizontally and vertically (by means of through-holes
or vias). The position of a decoupling capacitor is very
important. A decoupling capacitor on an unfavourable
position could do more damage than completely omitting
the capacitor, while on the right location it can mean the
difference between mediocre results and the ultimate
achievement.

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING INSTRUCTIONS

Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the V

and GND pads first, the

remaining pads may then be bonded to their external connections in any order.

THERMAL CHARACTERISTICS

Note

1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided

1.6 mm FR4 epoxy PCB with 35

m thick copper traces. The measurements are performed in still air.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

negative supply voltage

+0.5

DC voltage on pins

CLOOP, CLOOPQ, DLOOP, DLOOPQ, CREF, CREFQ, DIN, DINQ,
DOUT, DOUTQ, COUT and COUTQ

+0.5

ENL, LOCK and LOS,

0.5 +5.5

DREF19, DREF39, DOUT1250, DOUT622, DOUT155, PC and AREF V

0.5 +0.5

CAPUPQ and CAPDOQ

+ 0.5

0.5

input current on pins

ENL

CREF, CREFQ, DIN and DINQ

+10

tot

total power dissipation

700

amb

ambient temperature

+85

junction temperature

+110

stg

storage temperature

+150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-s)

thermal resistance from junction to solder point

K/W

th(j-a)

thermal resistance from junction to ambient

in free air; note 1

K/W

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

CHARACTERISTICS

3.3 V; T

amb

40 to +85

C; typical values measured at T

amb

= 25

C; all voltages are measured with respect

to GND.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

negative supply voltage

see Fig.12; note 1

3.50

3.30

3.10

negative supply current

open outputs; see Fig.13

105

155

tot

total power dissipation

350

550

Data and clock inputs: pins DIN, DINQ, CREF and CREFQ

i(p-p)

input voltage
(peak-to-peak value)

measurement system;

see Fig.10; notes 2 and 3

200

450

i(sens)(p-p)

input sensitivity
(peak-to-peak value)

measurement system;

notes 2 and 4

2.5

DC input offset voltage

measurement system

input voltage

measurement system

600

200

+250

input impedance

single-ended; see Fig.4; note 5

Data and clock outputs: pins DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ

o(p-p)

output voltage swing
(peak-to-peak value)

measurement system;

single-ended; see Fig.10

default adjustment; note 6

170

200

210

special adjustment; note 7

400

output voltage

600

output impedance

single-ended

100

r(C)

clock output rise time

differential; 20% to 80%

f(C)

clock output fall time

differential; 20% to 80%

r(D)

data output rise time

differential; 20% to 80%

116

f(D)

data output fall time

differential; 20% to 80%

116

d(D-C)

data-to-clock delay

see Fig.11; note 8

250

280

310

Output amplitude adjustment: pin AREF

AREF

output amplitude reference
voltage

floating pin

110

100

Power control output: pin PC

transconductance

mA/V

output current

3.5

Loop mode enable input: pin ENL

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

Phase lock indicator: pin LOCK

LOW-level output voltage

note 9

0.6

HIGH-level output voltage

note 9

3.3

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Loss of signal indicator: pin LOS

LOW-level output voltage

note 9

0.6

HIGH-level output voltage

note 9

3.3

assert time

note 10

0.1

das

de-assert time

note 10

BER

assert bit error rate

note 10

BER

das

de-assert bit error rate

note 10

BER

PLL characteristics

acq

acquisition time

CREF = 19.44 MHz

100

200

CREF = 38.88 MHz

200

tol(p-p)

jitter tolerance
(peak-to-peak value)

STM1/OC3 mode; note 11

f = 6.5 kHz

1.5

>10

f = 65 kHz

0.15

1.3

f = 1 MHz

0.15

0.8

STM4/OC12 mode; note 11

f = 25 kHz

1.5

>10

f = 100 kHz

0.7

f = 250 kHz

0.15

1.3

f = 1 MHz

0.15

0.50

f = 5 MHz

0.15

0.35

STM16/OC48 mode; note 11

f = 100 kHz

1.5

>10

f = 1 MHz

0.15

1.1

f = 10 MHz

0.15

0.23

gen(p-p)

jitter generation
(peak-to-peak value)

STM1/OC3 mode; note 12

f = 500 Hz to 1.3 MHz

0.039

0.50

f = 12 kHz to 1.3 MHz

0.032

0.10

f = 65 kHz to 1.3 MHz

0.032

0.10

STM4/OC12 mode; note 12

f = 1 kHz to 5 MHz

0.050

0.50

f = 12 kHz to 5 MHz

0.040

0.10

f = 250 kHz to 5 MHz

0.052

0.10

STM16/OC48 mode; note 12

f = 5 kHz to 20 MHz

0.079

0.50

f = 12 kHz to 20 MHz

0.063

0.10

f = 1 to 20 MHz

0.053

0.10

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Notes

1. Typical power supply voltage for the voltage regulator is

4.5 V (see Fig.6).

2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true

differential excitation).

3. The specified input voltage range is the guaranteed and tested range for proper operation; BER < 1

4. An input sensitivity of 7 mV (p-p) for BER < 1

is guaranteed. The typical input sensitivity for BER < 1

is 2.5 mV (p-p).

5. CML inputs are terminated internally using on-chip resistors of 50

connected to ground.

6. Output voltage range with default reference voltage on pin AREF (floating).

7. Output voltage range with adjustment of voltage on pin AREF (see Section "Output amplitude reference").

8. Measured with 1010 data pattern, single-ended output signals and rising edges of the signals on

pins COUT to DOUT or pins CLOOP to DLOOP. It should be noted that small deviations of the specified value are
possible if measured differentially.

9. External pull-up resistor of 10 k

connected to supply voltage of +3.3 V.

10. LOS assert or de-assert timing and BER level are for indication only. The values are neither production tested nor

guaranteed.

11. Measured in accordance with ITU specification G.958. Measured on demoboard OM5801 for STM16/OC48 and

demoboard OM5802 for STM1/OC3 and STM4/OC12. See for more information

"Application note AN96051" and

"Application note AN97065".

12. Measured in accordance with ITU specification G.813 and 1 dB above the system input sensitivity power level.

Measured on demoboard OM5801 for STM16/OC48 and on demoboard OM5802 for STM1/OC3 and STM4/OC12.

13. TDR is bit rate independent.

gen(rms)

jitter generation (RMS value)

STM1/OC3 mode; note 12

f = 500 Hz to 1.3 MHz

0.0060

f = 12 kHz to 1.3 MHz

0.0046

f = 65 kHz to 1.3 MHz

0.0041

STM4/OC12 mode; note 12

f = 1 kHz to 5 MHz

0.0093

f = 12 kHz to 5 MHz

0.0079

f = 250 kHz to 5 MHz

0.0081

STM16/OC48 mode; note 12

f = 5 kHz to 20 MHz

0.0143

f = 12 kHz to 20 MHz

0.0139

f = 1 to 20 MHz

0.0079

TDR

transitionless data run

note 13

2000

bits

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Fig.29 Application diagram showing the OQ2541 configured for the STM16/OC48 mode (2488.32 Mbits/s) with

a positive supply voltage application.

(1) (1) All pins GND must be connected directly to V

on the PCB plane of +5 V (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).

(2) L1 = RF choke type Murata BLM21.

(3) The loop mode outputs are used as main outputs:

pin ENL = HIGH-level selects loop mode outputs

pin ENL = LOW-level selects loop mode and normal mode outputs simultaneously.

handbook, full pagewidth

(2)

> 100

100

3.3

MGL663

VEE2

VEE1

GND

(1)

OQ2541

normal

output

unused
output

loop

output

select

DINQ

DIN

PRE-

AMP

DOUT1250

COUTQ

COUT

DOUTQ

DOUT

LOCK

AREF

VCC

CLOOP

CLOOPQ

DLOOP

DREF19

39 MHz

system clock

DLOOPQ

CAPUPQ

CAPDOQ

CREFQ

DREF39

CREF

ENL

DOUT155

DOUT622

LOS

10 k

100 nF

main
output

(3)

VCC

10 k

13, 18, 19,
36, 40

i.c.

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Table 6

Bonding pad locations.

SYMBOL

PAD

COORDINATES

(1)

ENL

1017.5

+852.5

GND

1017.5

+697.5

CLOOP

1017.5

+542.5

CLOOPQ

1017.5

+387.5

GND

1017.5

+232.5

DLOOP

1017.5

+77.5

DLOOPQ

1017.5

77.5

GND

1017.5

232.5

DREF19

1017.5

387.5

GND

1017.5

542.5

GND

1017.5

697.5

LOCK

1017.5

852.5

i.c.

852.5

1017.5

GND

697.5

1017.5

CAPUPQ

542.5

1017.5

CAPDOQ

387.5

1017.5

GND

232.5

1017.5

i.c.

77.5

1017.5

i.c.

+77.5

1017.5

GND

+232.5

1017.5

CREF

+387.5

1017.5

CREFQ

+542.5

1017.5

GND

+697.5

1017.5

DREF39

+852.5

1017.5

EE1

+1017.5

852.5

GND

+1017.5

697.5

DOUT1250

+1017.5

542.5

DOUT622

+1017.5

387.5

GND

+1017.5

232.5

DOUT155

+1017.5

77.5

EE2

+1017.5

+77.5

GND

+1017.5

+232.5

DIN

+1017.5

+387.5

DINQ

+1017.5

+542.5

GND

+1017.5

+697.5

i.c.

+1017.5

+852.5

+1017.5

GND

+697.5

+1017.5

Note

1. All x and y coordinates represent the position of the

centre of the pad in

m with respect to the centre of the

die (see Fig.30).

LOS

+542.5

+1017.5

i.c.

+387.5

+1017.5

GND

+232.5

+1017.5

DOUT

+77.5

+1017.5

DOUTQ

77.5

+1017.5

GND

232.5

+1017.5

COUT

387.5

+1017.5

COUTQ

542.5

+1017.5

GND

697.5

+1017.5

AREF

852.5

+1017.5

SYMBOL

PAD

COORDINATES

(1)

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Table 7

Physical characteristics of bare die

Thermal considerations

To improve heat transfer away from the product, a large area fill is recommended as a die pad. The die should be
mounted on this with a heat conductive glue. Bonding ALL supply and ground pads is essential for the electrical
performance, but also improves heat transfer to the die pad or other copper area fills. The more copper is leading away
from the die, the better the heat transport. On its turn, this copper should be able to loose its heat to the environment
through radiation, natural convection (non forced airflow over the printed-circuit board) or forced cooling.

NAME

DESCRIPTION

Glass passivation

0.8

m silicon nitride on top of 0.9

m PSG (PhosphoSilicate Glass)

Bonding pad dimension

minimum dimension of exposed metallization is 90

m (pad size = 100

100

Metallization

1.8

m AlCu (1% Cu)

Thickness

380

m nominal

Size

2.360

2.360 mm (5.5696 mm

)

Backing

silicon; electrically connected to V

potential through substrate contacts

Attache temperature

<440

C; recommended die attache is glue

Attache time

<15 s

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

1999 May 27

Philips Semiconductors

Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

OQ2541HP; OQ2541U

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Printed in The Netherlands

465012/150/03/pp36

Date of release: 1999 May 27

Document order number:

9397 750 05019

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OQ2541HP

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OQ2541HP