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Philips
Semiconductors
P3Z22V10
3V zero power, TotalCMOS
TM
, universal
PLD device
Product specification
Supersedes data of 1997 May 15
IC27 Data Handbook
1997 Jul 18
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
2
1997 Jul 18
8532004 18193
FEATURES
Industry's first TotalCMOS
TM
22V10 both CMOS design and
process technologies
Fast Zero Power (FZP
TM
) design technique provides ultra-low
power and high speed
Static current of less than 45
A
Dynamic current 1/10 to 1/1000 that of competitive devices
Pin-to-pin delay of only 10ns
True Zero Power device with no turbo bits or power down
schemes
Function/JEDEC map compatible with
Bipolar, UVCMOS, EECMOS 22V10s
Multiple packaging options featuring PCB-friendly flow-through
pinouts (SOL and TSSOP)
24-pin TSSOP--uses 93% less in-system space than a 28-pin
PLCC
24-pin SOL
28-pin PLCC with standard JEDEC pin-out
Available in commercial and industrial operating ranges
Supports mixed voltage systems5V tolerant I/Os
Advanced 0.5
E
2
CMOS process
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Varied product term distribution with up to 16 product terms per
output for complex functions
Programmable output polarity
Synchronous preset/asynchronous reset capability
Security bit prevents unauthorized access
Electronic signature for identification
Design entry and verification using industry standard CAE tools
Reprogrammable using industry standard device programmers
DESCRIPTION
The P3Z22V10 is the first SPLD to combine high performance with
low power, without the need for "turbo bits" or other power down
schemes. To achieve this, Philips Semiconductors has used their
FZP
TM
design technique, which replaces conventional sense
amplifier methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cascaded chain
of pure CMOS gates. This results in the combination of low power
and high speed that has previously been unattainable in the PLD
arena. For 5V operation, Philips Semiconductors offers the
P5Z22V10 that offers high speed and low power in a 5V
implementation.
The P3Z22V10 uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
This device has a programmable AND array which drives a fixed OR
array. The OR sum of products feeds an "Output Macro Cell"
(OMC), which can be individually configured as a dedicated input, a
combinatorial output, or a registered output with internal feedback.
ORDERING INFORMATION
ORDER CODE
PACKAGE
PROPAGATION
DELAY
TEMPERATURE
RANGE
OPERATING RANGE
DRAWING
NUMBER
P3Z22V10-DA
28-pin PLCC
10ns
0 to +70
C
V
CC
= 3.3V
10%
SOT261-3
P3Z22V10-DD
24-pin SOL
10ns
0 to +70
C
V
CC
= 3.3V
10%
SOT137-1
P3Z22V10-DDH
24-pin TSSOP
10ns
0 to +70
C
V
CC
= 3.3V
10%
SOT355-1
P3Z22V10-BA
28-pin PLCC
15ns
0 to +70
C
V
CC
= 3.3V
10%
SOT261-3
P3Z22V10-BD
24-pin SOL
15ns
0 to +70
C
V
CC
= 3.3V
10%
SOT137-1
P3Z22V10-BDH
24-pin TSSOP
15ns
0 to +70
C
V
CC
= 3.3V
10%
SOT355-1
P3Z22V10IBA
28-pin PLCC
15ns
40 to +85
C
V
CC
= 3.3V
10%
SOT261-3
P3Z22V10IBD
24-pin SOL
15ns
40 to +85
C
V
CC
= 3.3V
10%
SOT137-1
P3Z22V10IBDH
24-pin TSSOP
15ns
40 to +85
C
V
CC
= 3.3V
10%
SOT355-1
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
3
PIN CONFIGURATIONS
28-Pin PLCC
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
NC
IO/CLK
I1
I2
F7
F6
F5
NC
F4
F3
F2
I3
I4
I5
NC
I6
I7
I8
I9
I10
GND
NC
I1
1
F0
F1
F8
F9
V
CC
SP00474
24-Pin SOL and 24-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IO/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
V
CC
F9
F8
F7
F6
F5
F4
F2
F3
F1
F0
I11
GND
AP00475
PIN DESCRIPTIONS
PIN LABEL
DESCRIPTION
I1 I11
Dedicated Input
NC
Not Connected
F0 F9
Macrocell Input/Output
I0/CLK
Dedicated Input/Clock Input
V
CC
Supply Voltage
GND
Ground
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
4
LOGIC DIAGRAM
NOTE:
Programmable connection.
1
1
0
0
0
1
0
1
DAR
Q
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
Q
1
1
0
0
0
1
0
1
DAR
Q
SP
0
1
AR
SP
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39 40
43
0
3
4
7
8
11 12
15 16
19 20
23 24
27 28
31 32
35 36
39 40
43
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I10
I8
I9
GND
I11
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
VCC
0
1
9
10
20
21
33
34
48
49
65
66
82
83
97
98
110
111
121
122
130
131
SP00059
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
5
OUTPUT
MACRO
CELL
CLK/I0
I1 I11
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
PROGRAMMABLE AND ARRAY
(44
132)
1
11
8
10
12
14
16
16
14
12
10
8
SP00060A
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
RESET
PRESET
Figure 1.
Functional Diagram
FUNCTIONAL DESCRIPTION
The P3Z22V10 implements logic functions as sum-of-products
expressions in a programmable-AND/fixed-OR logic array.
User-defined functions are created by programming the connections
of input signals into the array. User-configurable output structures in
the form of I/O macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The P3Z22V10 architecture is illustrated in Figure 1. Twelve
dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs
for creation of logic functions. At the core of the device is a
programmable electrically-erasable AND array which drives a
fixed-OR array. With this structure, the P3Z22V10 can implement up
to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an I/O macrocell
which can be independently programmed to one of 4 different
configurations. The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions with either
Active-High or Active-Low polarity.
AND/OR Logic Array
The programmable AND array of the P3Z22V10 (shown in the Logic
Diagram) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
44 input lines:
24 input lines carry the True and Complement of the signals
applied to the 12 input pins
20 additional lines carry the True and Complement values of
feedback or input signals from the 10 I/Os
132 product terms:
120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16)
used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous preset product term
1 global asynchronous clear product term
At each input-line/product-term intersection there is an EEPROM
memory cell which determines whether or not there is a logical
connection at that intersection. Each product term is essentially a
44-input AND gate. A product term which is connected to both the
True and Complement of an input signal will always be FALSE, and
thus will not affect the OR function that it drives. When all the
connections on a product term are opened, a Don't Care state exists
and that term will always be TRUE.
Variable Product Term Distribution
The P3Z22V10 provides 120 product terms to drive the 10 OR
functions. These product terms are distributed among the outputs in
groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic
Diagram). This distribution allows optimum use of device resources.
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
6
F
0
1
1
0
0
1
0
0
1
CLK
1
AR
SP
S1
S0
S
1
S
0
OUTPUT CONFIGURATION
0 = Unprogrammed fuse
1 = Programmed fuse
D
Q
Q
0
0
1
1
0
1
0
1
Registered/Active-LOW/Macrocell feedback
Registered/Active-HIGH/Macrocell feedback
Combinatorial/Active-LOW/Pin feedback
Combinatorial/Active-HIGH/Pin feedback
SP00484
Figure 2.
Output Macro Cell Logic Diagram
F
CLK
AR
SP
S0 = 0
S1 = 0
D
Q
Q
a. Registered/Active-LOW
F
CLK
AR
SP
S0 = 1
S1 = 0
D
Q
Q
b. Registered/Active-HIGH
F
S0 = 0
S1 = 1
c. Combinatorial/Active-LOW
d. Combinatorial/Active-HIGH
F
S0 = 1
S1 = 1
SP00376
Figure 3.
Output Macro Cell Configurations
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. the ability to configure each output
independently permits users to tailor the configuration of the
P3Z22V10 to the precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 2, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of each
macrocell of the P3Z22V10 is determined by the two EEPROM bits
controlling these multiplexers. These bits determine output polarity,
and output type (registered or non-registered). Equivalent circuits for
the macrocell configurations are illustrated in Figure 3.
Output type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (registered
function). The D-type flip-flop latches data on the rising edge of the
clock and is controlled by the global preset and clear terms. When
the synchronous preset term is satisfied, the Q output of the register
will be set HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear term will set Q LOW, regardless of the clock
state. If both terms are satisfied simultaneously, the clear will
override the preset.
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
7
Program/Erase Cycles
The P3Z22V10 is 100% testable, erases/programs in seconds, and
guarantees 1000 program/erase cycles.
Output Polarity
Each macrocell can be configured to implement Active-High or
Active-Low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under
the control of its associated programmable output enable product
term. When the logical conditions programmed on the output enable
term are satisfied, the output signal is propagated to the I/O pin.
Otherwise, the output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can function
as a dedicated input, a dedicated output, or a bi-directional I/O.
Opening every connection on the output enable term will
permanently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will always
be logically FALSE and the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a registered
function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND
array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial
function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken
from the I/O pin. In this case, the pin can be used as a dedicated
input, a dedicated output, or a bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset
condition and the Q output will be low. The actual output of the
P3Z22V10 will depend on the programmed output polarity. The V
CC
rise must be monotonic.
Design Security
The P3Z22V10 provides a special EEPROM security bit that
prevents unauthorized reading or copying of designs programmed
into the device. The security bit is set by the PLD programmer,
either at the conclusion of the programming cycle or as a separate
step, after the device has been programmed. Once the security bit is
set, it is impossible to verify (read) or program the P3Z22V10 until
the entire device has first been erased with the bulk-erase function.
TotalCMOS
TM
Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS
TM
SPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer SPLDs which are both high performance and low
power, breaking the paradigm that to have low power, you must accept
low performance. Refer to Figure 4 and Table 1 showing the I
DD
vs.
Frequency of our P3Z22V10 TotalCMOS
TM
SPLD.
0
5
10
15
20
25
30
0
10
20
30
40
50
60
70
80
90
100
110
120
130
TYPICAL
I
DD
(mA)
FREQUENCY (MHz)
SP00443
1
Figure 4.
Typical I
DD
vs. Frequency @ V
DD
= 3.3V, 25
C (10-bit counter)
Table 1. Typical I
DD
vs. Frequency
V
DD
= 3.3V@25
C
FREQ (MHz)
1
10
20
30
40
50
60
70
80
90
100
110
120
130
Typical I
DD
(mA)
0.2
1.5
3.0
4.5
6.0
7.4
8.9
10.4
11.8
13.2
14.5
15.8
17.0
18.2
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
8
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
Supply voltage
0.5
4.6
V
V
I
Input voltage
0.5
5.5
2
V
V
OUT
Output voltage
0.5
5.5
2
V
I
IN
Input current
30
30
mA
I
OUT
Output current
100
100
mA
T
R
Allowable thermal rise ambient to junction
0
75
C
T
J
Junction temperature range
40
150
C
T
STG
Storage temperature range
65
150
C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. Except F7, where max = V
DD
+ 0.5V.
OPERATING RANGE
PRODUCT GRADE
TEMPERATURE
VOLTAGE
Commercial
0 to +70
C
3.3
10% V
Industrial
40 to +85
C
3.3
10% V
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
9
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
C
T
amb
+70
C; 3.0
V
DD
3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
V
IL
Input voltage low
V
DD
= 3.0V
0.8
V
V
IH
Input voltage high
V
DD
= 3.6V
2
V
V
I
Input clamp voltage
V
DD
= 3.0V; I
IN
= 18mA
1.2
V
V
OL
Output voltage low
V
DD
= 3.0V; I
OL
= 8mA
0.5
V
V
OH
Output voltage high
V
DD
= 3.0V; I
OH
= 4mA
2.4
V
I
I
Input leakage current
V
IN
= 0 to V
DD
10
10
A
I
I
In ut leakage current
V
IN
= V
DD
to 5.5V
2
10
10
I
OZ
3-Stated output leakage current
V
IN
= 0 to V
DD
10
10
A
I
OZ
3-Stated out ut leakage current
V
IN
= V
DD
to 5.5V
2
10
10
I
DDQ
Standby current
V
DD
= 3.6V; T
amb
= 0
C
25
45
A
I
DDD
1
Dynamic current
V
DD
= 3.6V; T
amb
= 0
C @ 1MHz
.5
2
mA
I
DDD
1
Dynamic current
V
DD
= 3.6V; T
amb
= 0
C @ 50MHz
10
15
mA
I
SC
Short circuit output current
1 pin/time for no longer than 1 se-
cond
15
100
mA
C
IN
Input pin capacitance
T
amb
= 25
C; f = 1MHz
8
pF
C
CLK
Clock input capacitance
T
amb
= 25
C; f = 1MHz
5
12
pF
C
I/O
I/O pin capacitance
T
amb
= 25
C; f = 1MHz
10
pF
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0
C
T
amb
+70
C; 3.0
V
DD
3.6V
SYMBOL
PARAMETER
B
D
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
MIN.
MAX.
UNIT
t
PD
Input or feedback to non-registered output
15
10
ns
t
SU
Setup time from input, feedback or SP to Clock
4.5
3.5
ns
t
CO
Clock to output
10
9
ns
t
CF
Clock to feedback
1
6
4.5
ns
t
H
Hold time
0
0
ns
t
AR
Asynchronous Reset to registered output
17
17
ns
t
ARW
Asynchronous Reset width
5
5
ns
t
ARR
Asynchronous Reset recovery time
6
6
ns
t
SPR
Synchronous Preset recovery time
6
6
ns
t
WL
Width of Clock LOW
3
3
ns
t
WH
Width of Clock HIGH
3
3
ns
t
R
Input rise time
20
20
ns
t
F
Input fall time
20
20
ns
f
MAX1
Maximum internal frequency
2
(1/t
SU
+ t
CF
)
95
125
MHz
f
MAX2
Maximum external frequency
1
(1/t
SU
+ t
CO
)
69
80
MHz
f
MAX3
Maximum clock frequency
1
(1/t
WL
+ t
WH
)
167
167
MHz
t
EA
Input to Output Enable
9
9
ns
t
ER
Input to Output Disable
9
9
ns
Capacitance
C
IN
Input pin capacitance
10
10
pF
C
OUT
Output capacitance
10
10
pF
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
10
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: 40
C
T
amb
+85
C; 3.0
V
DD
3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
V
IL
Input voltage low
V
DD
= 3.0V
0.8
V
V
IH
Input voltage high
V
DD
= 3.6V
2
V
V
I
Input clamp voltage
V
DD
= 3.0V; I
IN
= 18mA
1.2
V
V
OL
Output voltage low
V
DD
= 3.0V; I
OL
= 8mA
0.5
V
V
OH
Output voltage high
V
DD
= 3.0V; I
OH
= 4mA
2.4
V
I
I
Input leakage current
V
IN
= 0 to V
DD
10
10
A
I
I
In ut leakage current
V
IN
= V
DD
to 5.5V
2
10
10
A
I
OZ
3-Stated output leakage current
V
IN
= 0 to V
DD
10
10
A
I
OZ
3-Stated out ut leakage current
V
IN
= V
DD
to 5.5V
2
10
10
A
I
DDQ
Standby current
V
DD
= 3.6V; T
amb
= 40
C
30
45
A
I
DDD
1
Dynamic current
V
DD
= 3.6V; T
amb
= 40
C @
1MHz
.5
3
mA
I
DDD
1
Dynamic current
V
DD
= 3.6V; T
amb
= 40
C @
50MHz
10
20
mA
I
SC
Short circuit output current
1 pin/time for no longer than 1 se-
cond
15
100
mA
C
IN
Input pin capacitance
T
amb
= 25
C; f = 1MHz
8
pF
C
CLK
Clock input capacitance
T
amb
= 25
C; f = 1MHz
5
12
pF
C
I/O
I/O pin capacitance
T
amb
= 25
C; f = 1MHz
10
pF
NOTES:
1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be
affected.
2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: 40
C
T
amb
+85
C; 3.0
V
DD
3.6V
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
t
PD
Input or feedback to non-registered output
15
ns
t
SU
Setup time from input, feedback or SP to Clock
5
ns
t
CO
Clock to output
10.5
ns
t
CF
Clock to feedback
1
6
ns
t
H
Hold time
0
ns
t
AR
Asynchronous Reset to registered output
17
ns
t
ARW
Asynchronous Reset width
5
ns
t
ARR
Asynchronous Reset recovery time
6
ns
t
SPR
Synchronous Preset recovery time
6
ns
t
WL
Width of Clock LOW
3
ns
t
WH
Width of Clock HIGH
3
ns
t
R
Input rise time
20
ns
t
F
Input fall time
20
ns
f
MAX1
Maximum internal frequency
2
(1/t
SU
+ t
CF
)
91
MHz
f
MAX2
Maximum external frequency
1
(1/t
SU
+ t
CO
)
65
MHz
f
MAX3
Maximum clock frequency
1
(1/t
WL
+ t
WH
)
167
MHz
t
EA
Input to Output Enable
11
ns
t
ER
Input to Output Disable
11
ns
Capacitance
C
IN
Input pin capacitance
10
pF
C
OUT
Output capacitance
12
pF
NOTES:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to V
DD
or ground. These
parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be
affected.
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
11
TEST LOAD CIRCUIT
+3.3V
C
L
R
1
R
2
S
1
C
2
C
1
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
R
1
= 300
, R
2
= 300
, C
L
= 35pF.
V
CC
GND
CK
I
n
I
0
F
0
F
n
DUT
OE
INPUTS
SP00478
THEVENIN EQUIVALENT
35pF
150
DUT OUTPUT
VL = 1.65V
SP00479A
VOLTAGE WAVEFORM
90%
10%
1.5ns
1.5ns
+3.0V
0V
t
R
t
F
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD device
1997 Jul 18
12
SWITCHING WAVEFORMS
tS
NOTES:
1. V
T
= 1.5V.
2. Input pulse amplitude 0V to 3.0V.
3. Input rise and fall times 2.0ns max.
Combinatorial Output
Clock Width
Input to Output Disable/Enable
Asynchronous Reset
Synchronous Preset
tPD
VT
VT
INPUT OR
FEEDBACK
COMBINATORIAL
OUTPUT
VT
VT
VT
INPUT OR
FEEDBACK
CLOCK
REGISTERED
OUTPUT
tS
tH
tCO
VT
tWH
CLOCK
tWL
tER
tEA
VOH 0.5V
VOL + 0.5V
INPUT
OUTPUT
VT
VT
VT
VT
VT
tARW
tAR
tARR
CLOCK
REGISTERED
OUTPUT
INPUT ASSERTING
ASYNCHRONOUS
RESET
tH
VT
VT
VT
VT
tSPR
INPUT ASSERTING
SYNCHRONOUS
PRESET
CLOCK
REGISTERED
OUTPUT
tCO
SP00065
Registered Output
"AND" ARRAY (I, B)
I, B
P, D
CODE
O
STATE
INACTIVE1
CODE
STATE
CODE
STATE
CODE
STATE
TRUE
H
L
--
P, D
I, B
I, B
P, D
I, B
I, B
P, D
I, B
I, B
I, B
COMPLEMENT
DON'T CARE
SP00008
I, B
I, B
I, B
I, B
NOTE:
1. This is the initial state.
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD
device
1997 Jul 18
13
PLCC28:
plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD
device
1997 Jul 18
14
SO24:
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD
device
1997 Jul 18
15
TSSOP24:
plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
Philips Semiconductors
Product specification
P3Z22V10
3V zero power, TotalCMOS
TM
, universal PLD
device
1997 Jul 18
16
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Philips
Semiconductors