PORT 0

PORT 1

PORT 2

PORT 3

ADDRESS AND

BUS

ADDRESS BUS

VSS

VDD

TERNA

FUNCTIONS

RST

XTAL1

XTAL2

ALE

PSEN

RxD

TxD

INT0
INT1

T0
T1

SCL
SDA

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

DESCRIPTION

The P80C652/83C652 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
80C652/83C652 has the same instruction set
as the 80C51. Three versions of the
derivative exist:

83C652 -- 8k bytes mask programmable

ROM

80C652 -- ROMless version

87C652 -- EPROM version (described in a

separate chapter)

This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 8XC652 contains a non-volatile
8k

8 read-only program memory, a volatile

256

8 read/write data memory, four 8-bit I/O

ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
interrupt structure, an I

C interface, UART

and on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC652 can be expanded using standard
TTL compatible memories and logic.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)

and 40% in 1.5(1)

s. Multiply and divide

instructions require 3(2)

LOGIC SYMBOL

FEATURES

80C51 central processing unit

8 ROM expandable externally to

64k bytes

256

8 RAM, expandable externally to

64k bytes

Two standard 16-bit timer/counters

Four 8-bit I/O ports

C-bus serial I/O port with byte oriented

master and slave functions

Full-duplex UART facilities

Power control modes

Idle mode

Power-down mode

ROM code protection

Extended frequency range: 3.5 to 24 MHz

Three operating ambient temperature
ranges:

0 to +70

40 to +85

40 to +125

PIN CONFIGURATIONS

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

SCL/P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

SDA/P1.7

RD/P3.7

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VDD

WR/P3.6

PLASTIC

DUAL

IN-LINE

PACKAGE

PLASTIC

LEADED

CHIP

CARRIER

PLASTIC

QUAD

FLAT

PACK

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS

PLASTIC

LEADED CHIP

CARRIER

Pin

Function

Pin

Function

NC*

P1.0

P2.0/A8

P1.1

P2.1/A9

P1.2

P2.2/A10

P1.3

P2.3/A11

P1.4

P2.4/A12

P1.5

P2.5/A13

P1.6/SCL

P2.6/A14

P1.7/SDA

P2.7/A15

RST

PSEN

P3.0/RxD

ALE

NC*

P3.1/TxD

P3.2/INT0

P0.7/AD7

P3.3/INT1

P0.6/AD6

P3.4/T0

P0.5/AD5

P3.5/T1

P0.4/AD4

P3.6/WR

P0.3/AD3

P3.7/RD

P0.2/AD2

XTAL2

P0.1/AD1

XTAL1

P0.0/AD0

*DO NOT CONNECT

PLASTIC QUAD FLAT PACK
PIN FUNCTIONS

PLASTIC

QUAD

FLAT

PACK

Pin

Function

Pin

Function

P1.5

P2.5/A13

P1.6/SCL

P2.6/A14

P1.7/SDA

P2.7/A15

RST

PSEN

P3.0/RxD

ALE

SS4

SS2

P3.1/TxD

EA/VPP

P3.2/INT0

P0.7/AD7

P3.3/INT1

P0.6/AD6

P3.4/T0

P0.5/AD5

P3.5/T1

P0.4/AD4

P3.6/WR

P0.3/AD3

P3.7/RD

P0.2/AD2

XTAL2

P0.1/AD1

XTAL1

P0.0/AD0

SS1

NC*

SS3

P2.0/A8

P1.0

P2.1/A9

P1.1

P2.2/A10

P1.2

P2.3/A11

P1.3

P2.4/A12

P1.4

*DO NOT CONNECT

NOTES TO QFP ONLY:
1. Due to EMC improvements, all V

pins

(6, 16, 28, 39) must be connected to V

on the 80C652/83C652.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

ORDER INFORMATION

PHILIPS

PART ORDER NUMBER

PART MARKING

PHILIPS NORTH AMERICA

PART ORDER NUMBER

TEMPERATURE RANGE

(

FREQ

1 2

ROMless

ROM

Drawing

Number

ROMless

ROM

EPROM

(

)

AND PACKAGE

MHz

1,2

P80C652EBP

P83C652EBP/xxx

SOT129-1

P80C652EBPN

P83C652EBPN

S87C652-4N40

0 to +70,

Plastic Dual In-line Package

P80C652EBA

P83C652EBA/xxx

SOT187-2

P80C652EBAA

P83C652EBAA

S87C652-4A44

0 to +70,

Plastic Leaded Chip Carrier

P80C652EBB

P83C652EBB/xxx

SOT307-2

P80C652EBBB

P83C652EBBB

S87C652-4B44

0 to +70,

Plastic Quad Flat Pack

P80C652EFP

P83C652EFP/xxx

SOT129-1

P80C652EFPN

P83C652EFPN

S87C652-5N40

40 to +85,

Plastic Dual In-line Package

P80C652EFA

P83C652EFA/xxx

SOT187-2

P80C652EFAA

P83C652EFAA

S87C652-5A44

40 to +85,

Plastic Leaded Chip Carrier

P80C652EFB

P83C652EFB/xxx

SOT307-2

P80C652EFBB

P83C652EFBB

S87C652-5B44

40 to +85,

Plastic Quad Flat Pack

P80C652EHP

P83C652EHP/xxx

SOT129-1

P80C652EHPN

P83C652EHPN

40 to +125,

Plastic Dual In-line Package

P80C652EHA

P83C652EHA/xxx

SOT187-2

P80C652EHAA

P83C652EHAA

40 to +125,

Plastic Leaded Chip Carrier

P80C652EHB

P83C652EHB/xxx

SOT307-2

P80C652EHBB

P83C652EHBB

40 to +125,

Plastic Quad Flat Pack

P80C652IBP

P83C652IBP/xxx

SOT129-1

P80C652IBPN

P83C652IBPN

0 to +70,

Plastic Dual In-line Package

P80C652IBA

P83C652IBA/xxx

SOT187-2

P80C652IBAA

P83C652IBAA

0 to +70,

Plastic Leaded Chip Carrier

P80C652IBB

P83C652IBB/xxx

SOT307-2

P80C652IBBB

P83C652IBBB

0 to +70,

Plastic Quad Flat Pack

P80C652IFP

P83C652IFP/xxx

SOT129-1

P80C652IFPN

P83C652IFPN

40 to +85,

Plastic Dual In-line Package

P80C652IFA

P83C652IFA/xxx

SOT187-2

P80C652IFAA

P83C652IFAA

40 to +85,

Plastic Leaded Chip Carrier

P80C652IFB

P83C652IFB/xxx

SOT307-2

P80C652IFBB

P83C652IFBB

40 to +85,

Plastic Quad Flat Pack

NOTES:
1. 80C652 and 83C652 frequency range is 3.5MHz16MHz or 3.5MHz24MHz.
2. For specification of the EPROM version, see the 87C652 data sheet.
3. xxx denotes the ROM code number.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

PLCC

QFP

TYPE

NAME AND FUNCTION

6, 16,

28, 39

Ground: 0V reference. With the QFP package all V

pins (V

SS1

to V

SS4

) must be

connected.

Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.

P0.00.7

3932

4336

3730

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.

P1.0P1.7

4044,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
I

). Alternate functions include:

P1.6

I/O

SCL: I

C-bus serial port clock line.

P1.7

I/O

SDA: I

C-bus serial port data line.

P2.0P2.7

2128

2431

1825

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I

). Port 2 emits the high-order

address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.

P3.0P3.7

1017

11,

1319

713

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I

). Port 3 also serves the special features of

the 80C51 family, as listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V

permits a power-on reset using only an external

capacitor to V

ALE

I/O

Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to external
data memory.

PSEN

Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It
is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH) during
no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can
drive CMOS inputs without external pullups.

External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:
To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than V

+ 0.5V or V

0.5V, respectively.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

Table 1.

8XC652/654 Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB

LSB

RESET
VALUE

ACC*

Accumulator

E0H

00H

B register

F0H

00H

DPTR:

DPH
DPL

Data pointer
(2 bytes)
Data pointer high
Data pointer low

83H
82H

00H
00H

IE*#

Interrupt enable

A8H

ES1

ES0

ET1

EX1

ET0

EX0

0x000000B

IP*#

Interrupt priority

B8H

PS1

PS0

PT1

PX1

PT0

PX0

xx000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*#

Port 1

90H

SDA

SCL

FFH

P2*

Port 2

A0H

A15

A14

A13

A12

A11

A10

FFH

P3*

Port 3

B0H

INT1

INT0

TXD

RXD

FFH

PCON

Power control

87H

SMOD

GF1

GF0

IDL

0xxx0000B

S0CON*#

Serial 0 port control

98H

SM0

SM1

SM2

REN

TB8

RB8

00H

S0BUF#

Serial 0 data buffer

99H

xxxxxxxxB

PSW*

Program status word

D0H

RS1

RS0

00H

S1DAT#

Serial 1 data

DAH

00H

Stack pointer

81H

07H

S1ADR#

Serial 1 address

DBH

SLAVE ADDRESS

00H

S1STA#

Serial 1 status

D9H

SC4

SC3

SC2

SC1

SC0

F8H

S1CON*#

Serial 1 control

D8H

CR2

ENS1

STA

STO

CR1

CR0

00000000B

TCON*

Timer control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

TH1

Timer high 1

8DH

00H

TH0

Timer high 0

8CH

00H

TL1

Timer low 1

8BH

00H

TL0

Timer low 0

8AH

00H

TMOD

Timer mode

89H

GATE

C/T

GATE

C/T

00H

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

ROM CODE PROTECTION
(83C652)

The 8XC652 has an additional security
feature. ROM code protection may be
selected by setting a maskprogrammable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code is
protected and cannot be read out at any time
by any test mode or by any instruction in the
external program memory space.

The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is "don't care" after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
page 2.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

Reset

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on V

and RST must

come up at the same time for a proper
start-up.

Idle Mode

In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any

enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

Power-Down Mode

In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.

C Serial Communication--SIO1

The I

C serial port is identical to the I

serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.

Note that in both the 8XC652/4 and the
8XC552 the I

C pins are alternate functions

to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.

Table 2.

External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Serial Control Register (S1CON) See Table 3

CR2

ENS1

STA

STO

CR1

CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 3.

Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

CR2

CR1

CR0

6MHz

12MHz

16MHz

24MHz

OSC

DIVIDED BY

62.5

256

107

224

31.25

62.5

83.3

125

192

100

150

160

6.25

12.5

960

100

133

200

120

100

200

267

400

0.24 < 62.5

0 to 255

0.49 < 62.5

0 to 254

0.65 < 55.6

0 to 253

0.98 < 50.0

0 to 251

(256 (reload value Timer 1))

reload value range Timer 1 (in mode 2)

NOTES:
1. These frequencies exceed the upper limit of 100kHz of the I

C-bus specification and cannot be used in an I

C-bus application.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Storage temperature range

65 to +150

Voltage on any other pin to V

0.5 to + 6.0

Input, output current on any single pin

Power dissipation (based on package heat transfer
limitations, not device power consumption)

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices

from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All

voltages are with respect to V

unless otherwise noted.

DEVICE SPECIFICATIONS

TYPE

SUPPLY VOLTAGE

(V)

FREQUENCY

(MHz)

TEMPERATURE

RANGE

MIN.

MAX.

MIN.

MAX.

(

P8XC652EBx

4.5

5.5

3.5

0 to +70

P8XC652EFx

4.5

5.5

3.5

40 to +85

P8XC652EHx

4.5

5.5

3.5

40 to +125

P8XC652IBx

4.5

5.5

3.5

0 to +70

P83X652IFx

4.5

5.5

3.5

40 to +85

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

DC ELECTRICAL CHARACTERISTICS

= 0V; V

= 5V

10%

TEST

LIMITS

SYMBOL

PARAMETER

PART TYPE

CONDITIONS

MIN.

MAX.

UNIT

Input low voltage,
except EA, P1.6/SCL, P1.7/SDA

0 to +70

0.5

0.2V

0.1

40 to +85

0.5

0.2V

0.15

40 to +125

0.5

0.2V

0.25

IL1

Input low voltage to EA

0 to +70

0.5

0.2V

0.3

40 to +85

0.5

0.2V

0.35

40 to +125

0.5

0.2V

0.45

IL2

Input low voltage to P1.6/SCL, P1.7/SDA

0.5

0.3V

Input high voltage, except XTAL1, RST,
P1.6/SCL, P1.7/SDA

0 to +70

0.2V

+0.9

+0.5

40 to +85

0.2V

+1.0

+0.5

40 to +125

0.2V

+1.0

+0.5

IH1

Input high voltage, XTAL1, RST

0 to +70

0.7V

+0.5

40 to +85

0.7V

+0.1

+0.5

40 to +125

0.7V

+0.1

+0.5

IH2

Input high voltage, P1.6/SCL, P1.7/SDA

0.7V

6.0

Output low voltage, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

= 1.6mA

8, 9

0.45

OL1

Output low voltage, port 0, ALE, PSEN

= 3.2mA

8, 9

0.45

OL2

Output low voltage, P1.6/SCL, P1.7/SDA

= 3.0mA

0.4

Output high voltage, ports 1, 2, 3, ALE, PSEN

= 60

2.4

= 25

0.75V

= 10

0.9V

OH1

Output high voltage; port 0 in external bus mode

= 800

2.4

= 300

0.75V

= 80

0.9V

Logical 0 input current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

0 to +70

= 0.45V

40 to +85

40 to +125

Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA

0 to +70

See note 7

650

40 to +85

750

40 to +125

750

Input leakage current, port 0, EA

0.45V < V

< V

Input leakage current, P1.6/SCL, P1.7/SDA

0V < V

< 6.0V

0V < V

< 6.0V

Power supply current:

See note 1

Active mode @ 16MHz

2, 11

=5.5V

26.5

Active mode @ 24MHz

2, 11

=5.5V

33.8

Idle mode @ 16MHz

3, 11

Idle mode @ 24MHz

3, 11

Power down mode

4, 5

Power down mode

4, 5

40 to +125

100

RST

Internal reset pull-down resistor

150

Pin capacitance

Freq.=1MHz

NOTES ON NEXT PAGE.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 9 through 11 for I

test conditions.

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 5ns;

= V

+ 0.5V; V

= V

0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = V

. See Figure 9.

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 5ns; V

= V

+ 0.5V;

= V

0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

; EA = RST = V

. See Figure 10.

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = V

;

EA = RST = V

. See Figure 11.

5. 2V

max.

6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I

C specification, so an input voltage below 0.3V

will be recognized as a

logic 0 while an input voltage above 0.7V

will be recognized as a logic 1.

7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2V.

8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

9. Under steady state (non-transient) conditions, I

must be externally limited as follows: Maximum I

= 10mA per port pin; Maximum

= 26mA total for Port 0; Maximum I

= 15mA total for Ports 1, 2, and 3; Maximum I

= 71mA total for all output pins. If I

exceeds the

test conditions, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.

10. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0.9V

specification when the

address bits are stabilizing.

11. I

DDMAX

for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. I

DDMAX

is given in mA.

(1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax

fXTAL1 (MHz)

IDD

(mA)

Figure 1. I

vs. Frequency

(2)

(1)

IDD

(mA)

fXTAL1 (MHz)

These values are valid within the specified
frequency range.

(1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax
These values are valid within the specified
frequency range.

(1)

(2)

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

AC ELECTRICAL CHARACTERISTICS

1, 2

(16 MHz type)

16MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

150

CLCL

100

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

143

CLCL

PLIV

PSEN low to valid instruction in

CLCL

105

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

208

CLCL

105

PLAZ

PSEN low to address float

Data Memory

RLRH

3, 4

RD pulse width

275

CLCL

100

WLWH

3, 4

WR pulse width

275

CLCL

100

RLDV

3, 4

RD low to valid data in

148

CLCL

165

RHDX

3, 4

Data hold after RD

RHDZ

3, 4

Data float after RD

CLCL

LLDV

3, 4

ALE low to valid data in

350

CLCL

150

AVDV

3, 4

Address to valid data in

398

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

138

238

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

120

CLCL

130

QVWX

3, 4

Data valid to WR transition

CLCL

3, 4

Data setup time before WR

288

CLCL

150

WHQX

3, 4

Data hold after WR

CLCL

RLAZ

3, 4

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

103

CLCL

+40

Shift Register

XLXL

Serial port clock cycle time

0.75

12t

CLCL

QVXH

Output data setup to clock rising edge

492

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

117

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

492

10t

CLCL

133

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

AC ELECTRICAL CHARACTERISTICS

1, 2

(24 MHz type)

24MHz CLOCK

VARIABLE CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

102

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

128

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

3, 4

RD pulse width

150

CLCL

100

WLWH

3, 4

WR pulse width

150

CLCL

100

RLDV

3, 4

RD low to valid data in

118

CLCL

RHDX

3, 4

Data hold after RD

RHDZ

3, 4

Data float after RD

CLCL

LLDV

3, 4

ALE low to valid data in

180

CLCL

150

AVDV

3, 4

Address to valid data in

210

CLCL

165

LLWL

3, 4

ALE low to RD or WR low

175

CLCL

+50

AVWL

3, 4

Address valid to WR low or RD low

CLCL

QVWX

3, 4

Data valid to WR transition

CLCL

3, 4

Data setup time before WR

162

CLCL

130

WHQX

3, 4

Data hold after WR

CLCL

RLAZ

3, 4

RD low to address float

WHLH

3, 4

RD or WR high to ALE high

CLCL

+25

Shift Register

XLXL

Serial port clock cycle time

0.5

12t

CLCL

QVXH

Output data setup to clock rising edge

283

10t

CLCL

133

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

283

10t

CLCL

133

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

AC ELECTRICAL CHARACTERISTICS I

C INTERFACE

SYMBOL

PARAMETER

INPUT

OUTPUT

SCL TIMING CHARACTERISTICS

HD;STA

START condition hold time

14 t

CLCL

> 4.0

LOW

SCL LOW time

16 t

CLCL

> 4.7

HIGH

SCL HIGH time

14 t

CLCL

> 4.0

SCL rise time

SCL fall time

0.3

< 0.3

SDA TIMING CHARACTERISTICS

SU;DAT1

Data set-up time

250ns

> 20 t

CLCL

SU;DAT2

SDA set-up time (before rep. START cond.)

250ns

> 1

SU;DAT3

SDA set-up time (before STOP cond.)

250ns

> 8 t

CLCL

HD;DAT

Data hold time

0ns

> 8 t

CLCL

SU;STA

Repeated START set-up time

14 t

CLCL

> 4.7

SU;STO

STOP condition set-up time

14 t

CLCL

> 4.0

BUF

Bus free time

14 t

CLCL

> 4.7

SDA rise time

SDA fall time

0.3

< 0.3

NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

CLCL

will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400pF.

4. t

CLCL

= 1/f

OSC

= one oscillator clock period at pin XTAL1. For 63ns (42ns) < t

CLCL

< 285ns (16MHz (24MHz) > f

OSC

> 3.5MHz) the SI01

interface meets the I

C-bus specification for bit-rates up to 100 kbit/s.

TIMING SIO1 (I

C) INTERFACE

tRD

tSU;STA

tBUF

tSU; STO

0.7 VDD

0.3 VDD

0.7 VDD

0.3 VDD

tFD

tRC

tFC

tHIGH

tLOW

tHD;STA

tSU;DAT1

tHD;DAT

tSU;DAT2

tSU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always `t' (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE
P PSEN

Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid

to ALE low.

LLPL

= Time for ALE low

to PSEN low.

PXIZ

Figure 2. External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

PLIV

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

ALE

PSEN

PORT 0

PORT 2

Figure 3. External Data Memory Read Cycle

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPH

A8A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

LLAX

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

Figure 9. I

Test Condition, Active Mode

All other pins are disconnected

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

CLOCK SIGNAL

P1.6

P1.7

P1.6

P1.7

Figure 10. I

Test Condition, Idle Mode

All other pins are disconnected

VDD

RST

XTAL1

XTAL2

VSS

VDD

IDD

(NC)

Figure 11. I

Test Condition, Power Down Mode

All other pins are disconnected. V

= 2V to 5.5V

P1.6

P1.7

NOTE:
*

Ports 1.6 and 1.7 should be connected to V

through resistors of sufficiently high value such that the sink current into these pins does not

exceed the I

OL1

specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Philips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 06-98

Document order number:

9397 750 04047

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

Document Outline

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Document Outline

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