Document Outline

1 FEATURES
2 GENERAL DESCRIPTION
- 2.1 ROMless version: P80CL580
3 APPLICATIONS
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 FUNCTIONAL DIAGRAM
7 PINNING INFORMATION
- 7.1 Pinning
- 7.2 Pin description
8 FUNCTIONAL DESCRIPTION OVERVIEW
- 8.1 General
- 8.2 CPU timing
9 MEMORY ORGANIZATION
- 9.1 Program Memory
- 9.2 Data Memory
- 9.3 Special Function Registers (SFRs)
- 9.4 Addressing
10 I/O FACILITIES
- 10.1 Ports
- 10.2 Port options
- 10.3 Port 0 options
- 10.4 SET/RESET options
11 TIMERS/EVENT COUNTERS
- 11.1 Timer 0 and Timer 1
- 11.2 Timer T2
- 11.3 Timer/Counter 2 Control Register (T2CON)
- 11.4 Watchdog Timer
12 PULSE WIDTH MODULATED OUTPUT
- 12.1 Prescaler Frequency Control Register (PWMP)
- 12.2 Pulse Width Register (PWM0)
13 ANALOG-TO-DIGITAL CONVERTER (ADC)
- 13.1 ADC Control Register (ADCON)
14 REDUCED POWER MODES
- 14.1 Idle mode
- 14.2 Power-down mode
- 14.3 Wake-up from Power-down mode
- 14.4 Status of external pins
- 14.5 Power Control Register (PCON)
15 I2C-BUS SERIAL I/O
- 15.1 Serial Control Register (S1CON)
- 15.2 Serial Status Register (S1STA)
- 15.3 Data Shift Register (S1DAT)
- 15.4 Address Register (S1ADR)
16 STANDARD SERIAL INTERFACE SIO0: UART
- 16.1 Multiprocessor communications
- 16.2 Serial Port Control and Status Register (S0CON)
- 16.3 Baud rates
17 INTERRUPT SYSTEM
- 17.1 External interrupts INT2 to INT8
- 17.2 Interrupt priority
- 17.3 Interrupt registers
18 OSCILLATOR CIRCUITRY
19 RESET
- 19.1 External reset using the RST pin
- 19.2 Power-on-reset
20 SPECIAL FUNCTION REGISTERS OVERVIEW
21 INSTRUCTION SET
22 LIMITING VALUES
23 DC CHARACTERISTICS
24 AC CHARACTERISTICS
25 PACKAGE OUTLINES
- SOT190-1
- SOT319-2
26 SOLDERING
- 26.1 Introduction
- 26.2 Reflow soldering
- 26.3 Wave soldering
- 26.4 Repairing soldered joints
27 DEFINITIONS
28 LIFE SUPPORT APPLICATIONS
29 PURCHASE OF PHILIPS I 2 C COMPONENTS

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

CONTENTS

FEATURES

GENERAL DESCRIPTION

2.1

ROMless version: P80CL580

APPLICATIONS

ORDERING INFORMATION

BLOCK DIAGRAM

FUNCTIONAL DIAGRAM

PINNING INFORMATION

7.1

Pinning

7.2

Pin description

FUNCTIONAL DESCRIPTION OVERVIEW

8.1

General

8.2

CPU timing

MEMORY ORGANIZATION

9.1

Program Memory

9.2

Data Memory

9.3

Special Function Registers (SFRs)

9.4

Addressing

I/O FACILITIES

10.1

Ports

10.2

Port options

10.3

Port 0 options

10.4

SET/RESET options

TIMERS/EVENT COUNTERS

11.1

Timer 0 and Timer 1

11.2

Timer T2

11.3

Timer/Counter 2 Control Register (T2CON)

11.4

Watchdog Timer

PULSE WIDTH MODULATED OUTPUT

12.1

Prescaler Frequency Control Register (PWMP)

12.2

Pulse Width Register (PWM0)

ANALOG-TO-DIGITAL CONVERTER (ADC)

13.1

ADC Control Register (ADCON)

REDUCED POWER MODES

14.1

Idle mode

14.2

Power-down mode

14.3

Wake-up from Power-down mode

14.4

Status of external pins

14.5

Power Control Register (PCON)

C-BUS SERIAL I/O

15.1

Serial Control Register (S1CON)

15.2

Serial Status Register (S1STA)

15.3

Data Shift Register (S1DAT)

15.4

Address Register (S1ADR)

STANDARD SERIAL INTERFACE SIO0: UART

16.1

Multiprocessor communications

16.2

Serial Port Control and Status Register
(S0CON)

16.3

Baud rates

INTERRUPT SYSTEM

17.1

External interrupts INT2 to INT8

17.2

Interrupt priority

17.3

Interrupt registers

OSCILLATOR CIRCUITRY

RESET

19.1

External reset using the RST pin

19.2

Power-on-reset

SPECIAL FUNCTION REGISTERS
OVERVIEW

INSTRUCTION SET

LIMITING VALUES

DC CHARACTERISTICS

AC CHARACTERISTICS

PACKAGE OUTLINES

SOLDERING

26.1

Introduction

26.2

Reflow soldering

26.3

Wave soldering

26.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

FEATURES

�

Full static 80C51 Central Processing Unit

�

8-bit CPU, ROM, RAM, I/O in a 56-lead VSO or 64-lead
QFP package

�

256 bytes on-chip RAM Data Memory

�

6 kbytes on-chip ROM Program Memory for P83CL580

�

External memory expandable up to 128 kbytes: RAM up
to 64 kbytes and ROM up to 64 kbytes

�

Five 8-bit ports; 40 I/O lines

�

Three 16-bit Timers/Event counters

�

On-chip oscillator suitable for RC, LC, quartz crystal or
ceramic resonator

�

Fifteen source, fifteen vector, nested interrupt structure
with two priority levels

�

Full duplex serial port (UART)

�

C-bus interface for serial transfer on two lines

�

Analog-to-digital converter (ADC) with Power-down
mode; 4 input channels and 8-bit ADC

�

Pulse Width Modulated (PWM) output (8-bit resolution)

�

Watchdog Timer

�

Enhanced architecture with:

� non-page oriented instructions

� direct addressing

� four 8-byte RAM register banks

� stack depth limited only by available internal RAM

(maximum 256 bytes)

� multiply, divide, subtract and compare instructions

�

Reduced power consumption through Power-down and
Idle modes

�

Wake-up via external interrupts at Port 1

�

Frequency range: 0 to 12 MHz. For ADC operation
minimum 250 kHz at 2.7 V

�

Supply voltage: 2.5 to 6.0 V

�

Very low current consumption:
typically 4.5 mA at 2.5 V and 8 MHz

�

Operating ambient temperature range:

40 to +85

�

GENERAL DESCRIPTION

The P80CL580; P83CL580 (hereafter generally referred to
as P8xCL580) is manufactured in an advanced CMOS
technology. The P8xCL580 has the same instruction set
as the 80C51, consisting of over 100 instructions:
49 one-byte, 46 two-byte, and 16 three-byte. The device
operates over a wide range of supply voltages and has low
power consumption; there are two software selectable
modes for power reduction: Idle and Power-down.
For emulation purposes, the P85CL580 (piggy-back
version) with 256 bytes of RAM is recommended.

This data sheet details the specific properties of the
P80CL580; P83CL580. For details of the 80C51 core and
the I

C-bus see

"Data Handbook IC20".

2.1

ROMless version: P80CL580

The P80CL580 is the ROMless version of the P83CL580.
The mask options on the P80CL580 are fixed as follows:

�

All ports have option `1S' (standard port, HIGH after
reset), except ports P1.6 and P1.7 which have option
`2S' (open-drain, HIGH after reset)

�

Oscillator option: Oscillator 3

�

Power-on-reset option: off.

APPLICATIONS

The P8xCL580 is an 8-bit general purpose microcontroller
especially suited for cordless telephone and mobile
communication applications. The P8xCL580 also
functions as an arithmetic processor having facilities for
both binary and BCD arithmetic plus bit-handling
capabilities.

ORDERING INFORMATION

Note

1. `x' = 0 or 3. Refer to the Order Entry Form (OEF) for this device for the full type number, including options/program.

TYPE

NUMBER

(1)

PACKAGE

NAME

DESCRIPTION

VERSION

P8xCL580HFT

VSO56 plastic very small outline package; 56 leads

SOT190-1

P8xCL580HFH

QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);

body 14 x 20 x 2.8 mm

SOT319-2

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

7.2

Pin description

Table 1

Pin description for VSO56 (SOT190-1) and QFP64 (SOT319-2)

For more extensive description of the port pins see Chapter 10 "I/O facilities".

SYMBOL

PIN

DESCRIPTION

VSO56

QFP64

ADC3 to ADC0

1 to 4

59 to 62

4 input channels to the ADC.

ref(p)(A)

Positive potential of analog-to-digital conversion reference resistor.

SSA

Analog part ground.

P4.0 to P4.7

7 to 14

1, 2, 4 to 8,

Port 4: 8-bit bidirectional I/O port. (P4.0 to P4.7). Port pins that have
logic 1s written to them are pulled HIGH by internal pull-ups, and in this
state can be used as inputs. As inputs, Port 4 pins that are externally
pulled LOW will source current (I

, see Chapter 23) due to the internal

pull-ups. Port 4 output buffers can sink/source 4 LS TTL loads.

RST

Reset: a HIGH level on this pin for two machine cycles while the
oscillator is running resets the device.

P1.0/INT2/T2

�

Port 1: 8-bit bidirectional I/O port (P1.0 to P1.7). Same characteristics
as Port 4, but note that P1.6 and P1.7 are open-drain only.

�

Alternative functions:

� INT2 to INT8 are external interrupt inputs

� STADC is the external trigger of the analog-to-digital converter

� T2 and T2EX are the Timer/event counter 2 inputs

� SCL and SDA are the I

C-bus clock and data lines.

P1.1/INT3/T2EX

P1.2/INT4/STADC

P1.3/INT5

P1.4/INT6

P1.5/INT7

P1.6/INT8/SCL

P1.7/SDA

PWM0

Pulse Width Modulation output 0.

EWN

Enable Watchdog Timer: enable for Watchdog Timer and enable
Power-down mode.

XTAL2

Crystal oscillator output: output of the inverting amplifier of the
oscillator. Left open when external clock is used.

XTAL1

Crystal oscillator input: input to the inverting amplifier of the oscillator,
also the input for an externally generated clock source.

Ground: circuit ground potential.

P3.0/RXD

�

Port 3: 8-bit bidirectional I/O port (P3.0 to P3.7).
Same characteristics as Port 4

�

Alternative functions:

� RXD is the UART serial data input (asynchronous) or data

input/output (synchronous)

� TXD is the UART serial data output (asynchronous) or clock output

(synchronous)

� INT0 and INT1 are external interrupts 0 and 1

� T0 and T1 are external inputs for timers 0 and 1.

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

P0.0 to P0.7

37 to 44

�

Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written
to them float, and in that state will function as high impedance inputs.

�

Low-order addressing: Port 0 is also the multiplexed low-order
address and data bus during access to external memory. The strong
internal pull-ups are used while emitting logic 1s within the low order
address.

P2.0 to P2.7

55 to 53,

49 to 45

56 to 54,

49 to 45

�

Port 2: 8-bit bidirectional I/O port with internal pull-ups.
Same characteristics as Port 4.

�

High-order addressing: Port 2 emits the high-order address byte
during accesses to external memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the
P2 Special Function Register.

External Access. When EA is held HIGH the CPU executes out of
internal Program Memory (unless the program counter exceeds
17FFH). Holding EA LOW forces the CPU to execute out of external
memory regardless of the value of the Program Counter.

ALE

Address Latch Enable. Output pulse for latching the low byte of the
address during access to external memory. ALE is emitted at a constant
rate of

�

osc

, and may be used for external timing or clocking

purposes (assuming MOVX instructions are not used).

PSEN

Program Store Enable. Output read strobe to external Program
Memory. When executing code out of external Program Memory, PSEN
is activated twice each machine cycle. However, during each access to
external Data Memory two PSEN activations are skipped.

Power supply.

n.c.

3, 9, 17, 18,

35, 36, 50

and 58

Not connected.

SYMBOL

PIN

DESCRIPTION

VSO56

QFP64

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

FUNCTIONAL DESCRIPTION OVERVIEW

This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters:

Chapter 9 "Memory organization"

Chapter 10 "I/O facilities"

Chapter 11 "Timers/event counters"

Chapter 12 "Pulse Width Modulated output"

Chapter 13 "Analog-to-digital converter (ADC)"

Chapter 14 "Reduced power modes"

Chapter 15 "I

C-bus serial I/O"

Chapter 16 "Standard serial interface SIO0: UART"

Chapter 17 "Interrupt system"

Chapter 18 "Oscillator circuitry"

Chapter 19 "Reset".

8.1

General

The P8xCL580 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as cordless telephone and mobile communications,
instrumentation, industrial control, intelligent computer
peripherals and consumer products.

The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.

The P8xCL580 contains a 6 kbytes Program Memory
(ROM; P83CL580); a static 256 bytes Data Memory
(RAM); 40 I/O lines; three 16-bit timer/event counters; a
fifteen-source two priority-level, nested interrupt structure
and on-chip oscillator and timing circuit, 4-channel 8-bit
A/D converter, Watchdog Timer and Pulse Width
Modulation output.

The device has two software-selectable modes of reduced
activity for power reduction:

�

Idle mode; freezes the CPU while allowing the
derivative functions (timers, serial I/O, ADC, PWM) and
interrupt system to continue functioning.

�

Power-down mode; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.

In addition, two serial interfaces are provided on-chip:

�

A standard UART serial interface, and

�

A standard I

C-bus serial interface. The I

C-bus serial

interface has byte-oriented master and slave functions
allowing communication with the whole family of I

C-bus

compatible devices.

8.2

CPU timing

A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1

�

s if the oscillator

frequency (f

osc

) is 12 MHz.

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

MEMORY ORGANIZATION

The P8xCL580 has 6 kbytes of Program Memory (ROM;
P83CL580 only) plus 256 bytes of Data Memory (RAM) on
board.The device has separate address spaces for
Program and Data Memory (see Fig.6). Using Port latches
P0 and P2, the P8xCL580 can address up to 128 kbytes of
external memory. The CPU generates both read (RD) and
write (WR) signals for external Data Memory accesses,
and the read strobe (PSEN) for external Program Memory.

9.1

Program Memory

The P83CL580 contains 6 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 6 kbytes of Program Memory can be
implemented in either on-chip ROM or external Program
Memory.

If the EA pin is tied to V

, then Program Memory fetches

from addresses 0000H to 17FFH are directed to the
internal ROM. Fetches from addresses 1800H to FFFFH
are directed to external ROM. Program Counter values
greater than 17FFH are automatically addressed to
external memory regardless of the state of the EA pin.

9.2

Data Memory

The P8xCL580 contains 256 bytes of internal RAM and
40 Special Function Registers (SFRs). Figure 6 shows the
internal Data Memory space divided into the lower
128 bytes, the upper 128 bytes, and the SFRs space.
Internal RAM locations 0 to 127 are directly and indirectly
addressable. Internal RAM locations 128 to 255 are only
indirectly addressable. The Special Function Register
locations 128 to 255 bytes are only directly addressable.

9.3

Special Function Registers (SFRs)

The upper 128 bytes are the address locations of the
SFRs. Figures 7 and 8 show the Special Function
Registers space. The SFRs include the port latches,
timers, peripheral control, serial I/O registers, etc. These
registers can only be accessed by direct addressing.
There are 128 directly addressable locations in the SFR
address space. Bit addressable SFRs are those that end
in 000B.

9.4

Addressing

The P8xCL580 has five methods for addressing source
operands:

�

Direct

�

Immediate

�

Base-register plus index-register-indirect.

The first three methods can be used for addressing
destination operands. Most instructions have a
`destination/source' field that specifies the data type,
addressing methods and operands involved. For
operations other than MOVs, the destination operand is
also a source operand.

Fig.5 The lower 128 bytes of internal RAM.

halfpage

MLA560 - 1

07H

0FH

08H

17H

10H

1FH

18H

2FH

7FH

20H

30H

bit-addressable space

(bit addresses 0 to 7F)

4 banks of 8 registers

(R0 to R7)

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Access to memory addressing is as follows:

�

Registers in one of the four register banks through
register, direct or register-indirect

�

Lower 128 bytes of internal RAM through direct or
register-indirect; upper 128 bytes of internal RAM
through direct

�

Special Function Registers through direct

�

External Data Memory through register-indirect

�

Program Memory look-up tables through base-register
plus index-register-indirect.

The P8xCL580 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers,
Arithmetic Logic Unit and external data bus are all 8-bits
wide. It performs operations on bit, nibble, byte and
double-byte data types.

Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.

Fig.6 Memory map.

(1) Accessible via indirect addressing only.

(2) Accessible via direct and indirect addressing.

(3) Accessible via direct addressing.

handbook, full pagewidth

MGD676

(1)

(3)

(2)

255

127

EXTERNAL

(EA = 0)

INTERNAL

(EA = 1)

INTERNAL DATA MEMORY

EXTERNAL

DATA MEMORY

PROGRAM MEMORY

EXTERNAL

64 kbytes

6 kbytes

OVERLAPPED SPACE

6 kbytes

SPECIAL

FUNCTION

REGISTERS

INTERNAL

DATA RAM

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

10 I/O FACILITIES

10.1

Ports

The P8xCL580 has 40 I/O lines treated as one 8-bit port
plus 32 individually addressable bits or as five parallel 8-bit
addressable ports.

Port 4 has no alternative functions. To enable a port pin
alternative function for Ports 0, 1, 2 and 3, the port bit
latch in its SFR must contain a logic 1. The alternative
functions are detailed below:

Port 0 Provides the multiplexed low-order address and

data bus for expanding the device with standard
memories and peripherals.

Port 1 Used for a number of special functions:

�

Provides the inputs for the external interrupts:
INT2 to INT8.

�

External activation of Timer 2: T2.

�

External trigger of the ADC: STADC.

�

The I

C-bus interface: SCL and SDA.

Port 2 Provides the high-order address when expanding

the device with external Program or Data Memory.

Port 3 Pins can be configured individually to provide:

�

External interrupt request inputs: INT1 and INT0.

�

Counter input: T1 and T0.

�

Control signals to read and write to external
memories: RD and WR.

�

UART input and output: RXD and TXD.

Each port consists of a latch (SFRs P0 to P4), an output
driver and input buffer. Ports 1, 2, 3 and 4 have internal
pull-ups (except P1.6 and P1.7). Figure 9(a) shows that
the strong transistor `p1' is turned on for only 2 oscillator
periods after a LOW-to-HIGH transition in the port latch.
When on, it turns on `p3' (a weak pull-up) through the
inverter. This inverter and `p3' form a latch which holds the
logic 1. In Port 0 the pull-up `p1' is only on when emitting
logic 1s for external memory access. Writing a logic 1 to a
Port 0 bit latch leaves both output transistors switched off
so that the pin can be used as an high-impedance input.

10.2

Port options

38 of the 40 port pins (excluding P1.6 and P1.7 with option
2S only) may be individually configured with one of the
following options. These options are also shown in Fig.9.

Option 1 Standard Port; quasi-bidirectional I/O with

pull-up. The strong booster pull-up `p1' is turned
on for two oscillator periods after a

LOW-to-HIGH transition in the port latch;
Fig.9(a).

Option 2 Open-drain; quasi-bidirectional I/O with

n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.9(b).

Option 3 Push-pull; output with drive capability in both

polarities. Under this option, pins can only be
used as outputs; see Fig.9(c).

10.3

Port 0 options

The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.

10.3.1

XTERNAL MEMORY ACCESSES

Option 1 True logic 0 and logic 1 are written as address to

the external memory (strong pull-up to be used).

Option 2 An external pull-up resistor is required for

external accesses.

Option 3 Not allowed for external memory accesses as

the port can only be used as output.

10.3.2

I/O A

CCESSES

Option 1 When writing a logic 1 to the port latch, the

strong pull-up `p1' will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.

Option 2 Open-drain; quasi-directional I/O with n-channel

open-drain output. Use as an output requires the
connection of an external pull-up resistor. See
Fig.9(b).

Option 3 Push-Pull; output with drive capability in both

polarities. Under this option pins can only be
used as outputs. See Fig.9(c).

10.4

SET/RESET options

Individual mask selection of the post-reset state is
available with any of the above pins. The selection is made
by appending `S' or `R' to Options 1, 2, or 3 above.

Option R RESET, at reset this pin will be initialized LOW.

Option S SET, at reset this pin will be initialized HIGH.

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

11 TIMERS/EVENT COUNTERS

The P8xCL580 contains three 16-bit timer/event counter
registers; Timer 0, Timer 1 and Timer 2 which can perform
the following functions:

�

Measure time intervals and pulse durations

�

Count events

�

Generate interrupt requests.

In the `Timer' operating mode the register is incremented
every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is

�

osc

In the `Counter' operating mode, the register is
incremented in response to a HIGH-to-LOW transition.
Since it takes 2 machine cycles (24 oscillator periods) to
recognize a HIGH-to-LOW transition, the maximum count
rate is

�

osc

. To ensure a given level is sampled, it

should be held for at least one complete machine cycle.

11.1

Timer 0 and Timer 1

Timer 0 and Timer 1 can be programmed independently to
operate in four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32

prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TH0 as two

separate counters.

11.2

Timer T2

Timer T2 is a 16-bit timer/counter that can operate (like
Timer 0 and 1) either as a timer or as an event counter.
These functions are selected by the state of the C/T2 bit in
the T2CON register; see Tables 2 and 3.

Three operating modes are available Capture, Auto-reload
and Baud Rate Generator, which also are selected via the
T2CON register; see Table 4.

11.2.1

APTURE MODE

Figure 10 shows the Capture mode. Two options in this
mode, may be selected by the EXEN2 bit in T2CON:

�

If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter
which upon overflowing sets the Timer 2 overflow bit
TF2, this may then be used to generate an interrupt.

�

If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX causes the current
value in TL2 and TH2 to be captured into registers
RCAP2L and RCAP2H respectively. In addition, the
transition at T2EX causes the EXF2 bit in T2CON to be
set; this may also be used to generate an interrupt.

11.2.2

UTO

RELOAD MODE

Figure 11 shows the Auto-reload mode. Also two options
in this mode are selected by the EXEN2 bit in T2CON:

�

If EXEN2 = 0, then when Timer 2 rolls over, it sets the
TF2 bit but also causes the Timer 2 registers to be
reloaded with the 16-bit value held in registers RCAP2L
and RCAP2H. The 16-bit value held in these registers is
preset by software.

�

If EXEN2 = 1, Timer 2 operates as described above but
with the additional feature that a HIGH-to-LOW
transition at external input T2EX will also trigger the
16-bit reload and set the EXF2 bit.

11.2.3

AUD

ATE

ENERATOR MODE

The Baud Rate Generator mode is selected when
RTCLK = 1. It will be described in conjunction with the
serial port (UART); see Section 16.3.2.

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Product specification

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UART, I

C-bus and ADC

P80CL580; P83CL580

11.3

Timer/Counter 2 Control Register (T2CON)

Table 2

Timer/Counter 2 Control Register (SFR address C8H)

Table 3

Description of T2CON bits.

Table 4

Timer 2 operating modes; X = don't care.

TF2

EXF2

GF2

RTCLK

EXEN2

TR2

C/T2

CP/RL2

BIT

SYMBOL

DESCRIPTION

TF2

Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when RTCLK = 1.

EXF2

Timer 2 external flag. Set when either a capture or reload is caused by a negative
transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,
EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine. EXF2 must be
cleared by software.

GF2

General purpose flag bit.

RTCLK

Receive/transmit clock flag. When set, causes the UART serial port to use Timer 2
overflow pulses for its receive and transmit clock in Modes 1 and 3. RTCLK = 0 causes
Timer 1 overflows to be used for the receive and transmit clock.

EXEN2

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX, if Timer 2 is not being used to clock the serial port.
EXEN2 = 0, causes Timer 2 to ignore events at T2EX.

TR2

Start/stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

Timer or counter select for Timer 2. C/T2 = 0 selects the internal timer with a clock
frequency of

�

osc

. C/T2 = 1 selects the external event counter; negative edge

triggered.

CP/RL2

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX, if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When RTCLK = 1, this bit is ignored and
the timer is forced to auto-reload on a Timer 2 overflow.

RTCLK

CP/RL2

TR2

MODE

16-bit Auto-reload

16-bit Capture

Baud Rate Generator

Off

1997 Mar 14

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C-bus and ADC

P80CL580; P83CL580

11.4

Watchdog Timer

In addition to Timer T2 and the standard timers, a
Watchdog Timer (consisting of an 11-bit prescaler and an
8-bit timer) is also incorporated.

The Watchdog Timer is controlled by the Watchdog
Enable pin (EWN). When EWN = 0, the timer is enabled
and the Power-down mode is disabled. When EWN = 1,
the timer is disabled and the Power-down mode is
enabled. In the Idle mode the Watchdog Timer and reset
circuitry remain active.

The Watchdog Timer is shown in Fig. 12.

The timer frequency is derived from the oscillator
frequency using the following formula:

timer

osc

2048

�

(

)

---------------------------------

When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin. To
prevent a system reset the timer must be reloaded in time
by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.

The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.

The time interval between the timer reloading and the
occurrence of a reset is dependent upon the reloaded
value. For example, this time period may range from 2 ms
to 500 ms when using an oscillator frequency
f

osc

= 12 MHz.

Fig.12 Functional diagram of the T3 Watchdog Timer.

handbook, full pagewidth

MGD678

INTERNAL BUS

write

PRESCALER

11-BIT

TIMER T3 (8-BIT)

LOAD

CLEAR

overflow

internal

reset

LOADEN

EWN

LOADEN

PCON.4

PCON.1

CLEAR

WLE

RST

VDD

INTERNAL BUS

fosc/12

1997 Mar 14

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UART, I

C-bus and ADC

P80CL580; P83CL580

12 PULSE WIDTH MODULATED OUTPUT

One Pulse Width Modulated output channel (PWM0) is
provided which outputs pulses of programmable length
and interval. The repetition frequency is defined by an 8-bit
prescaler (PWMP) that generates the clock for the
counter. The 8-bit counter counts modulo 255, i.e. from
0 to 254 inclusive. The value held in the 8-bit counter is
compared to the contents of the register PWM0.

Provided the contents of this register are greater than the
counter value, the PWM0 output is set LOW. If the
contents of register PWM0 are equal to, or less than the
counter value, the PWM0 output is set HIGH.
The pulse-width-ratio is therefore defined by the contents
of register PWM0. The pulse-width-ratio will be in the
range 0 to

255

and may be programmed in increments

255

The repetition frequency (f

PWM

) at the PWM0 output is

given by:

For f

osc

= 12 MHz the above formula gives a repetition

frequency range of 92 Hz to 23.5 kHz.

By loading the PWM0 register with either 00H or FFH, the
PWM0 output can be retained at a constant HIGH or LOW
level respectively. When loading FFH into the PWM0
register, the 8-bit counter will never actually reach this
value.

The PWM0 output pin is driven by push-pull drivers and is
not shared with any other function.

PWM

osc

{

(

PWMP

)

255

}

�

----------------------------------------------------------------------------

12.1

Prescaler Frequency Control Register (PWMP)

Table 5

Prescaler Frequency Control Register (address FEH)

Table 6

Description of PWMP bits

12.2

Pulse Width Register (PWM0)

Table 7

Pulse Width Register (address FCH)

Table 8

Description of PWM0 bits

PWMP.7

PWMP.6

PWMP.5

PWMP.4

PWMP.3

PWMP.2

PWMP.1

PWMP.0

BIT

SYMBOL

DESCRIPTION

7 to 1

PWMP.7 to PWMP.0

Prescaler division factor = (PWMP) + 1.

PWM0.7

PWM0.6

PWM0.5

PWM0.4

PWM0.3

PWM0.2

PWM0.1

PWM0.0

BIT

SYMBOL

DESCRIPTION

7 to 1

PWM0.7 to PWM0.0

LOW/HIGH ratio of PWM0 signal

PWM0

(

)

255

PWM0

(

)

�

{

}

--------------------------------------------------

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UART, I

C-bus and ADC

P80CL580; P83CL580

13 ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog input circuitry consists of a 4-bit analog
multiplexer and an ADC with 8-bit resolution. The analog
reference voltage (V

ref(p)(A)

) and analog ground (V

SSA

) are

connected via separate input pins. The conversion is
selectable from 24 machine cycles (24

�

s at

osc

= 12 MHz) to 48 machine cycles. The functional

diagram of the ADC is shown in Fig. 14.

The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer via the ADCON register bits AADR0 and
AADR1. The completion of the 8-bit ADC conversion is
flagged by ADCI in the ADCON register and the result is
stored in the Special Function Register ADCH (address
C5H).

An ADC conversion in progress is unaffected by an
external software ADC start.

The result of a completed conversion remains unaffected
provided ADCI = 1. While ADCS = 1 or ADCI = 1, a new
ADC start will be blocked and consequently lost.

An ADC conversion already in progress is aborted when
the Power-down mode is entered. The result of a
completed conversion (ADCI = 1) remains unaffected
when entering the Idle or Power-down mode.

The analog-to-digital conversion can be started in 3 ways:

�

Start in operating mode, continue in operating mode

�

Start in operating mode, by setting the ADCS bit, then go
to Idle mode

�

Set the ADEX bit, go to the Idle mode and start
conversion externally via the STADC pin.

For the three cases mentioned above the internal flag
ADCI is set upon completion of the conversion.

Fig.14 Functional diagram of analog input.

handbook, full pagewidth

MGC751

ADC0

ANALOG INPUT

MULTIPLEXER

8-BIT ADC

(succesive approximation)

ADCON

START

END

(1)

STADC

ADEX

ref(p)(A)

SSA

ADCH

INTERNAL BUS

ADC1

ADC2

ADC3

(1) For the descriptions of ADCON bits see Table 10.

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C-bus and ADC

P80CL580; P83CL580

13.1

ADC Control Register (ADCON)

Table 9

ADC Control Register (address C4H)

Table 10 Description of ADCON bits

ADPD

ADEX

ADCI

ADCS

CKDIV

AADR1

AADR0

BIT

SYMBOL

DESCRIPTION

Reserved.

ADPD

Power-down. This bit switches off the resistor reference to save power even when the
CPU is operating.

ADEX

Enable external start of conversion. This bit determines whether a conversion can be
started using the external pin STADC. When ADEX = 0, a conversion cannot be started
externally using STADC. When ADEX = 1, a conversion can be started externally using
STADC.

ADCI

ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if this is enabled. This flag must be cleared by software (it cannot
be set by software); see Table 11.

ADCS

ADC start and status flag. When this bit is set an ADC conversion is started. ADCS
may be set by software or by the external signal STADC. The ADC logic ensures that
this signal is HIGH while the ADC is busy. On completion of the conversion ADCS is
reset and after that the interrupt flag ADCI is set. ADCS cannot be reset by software;
see Table 11.

CKDIV

This bit selects the conversion time, in terms of instruction cycles. This allows the CPU
to be run at the maximum frequency (12 MHz) yet keeping the ADC timing at low
frequency. When CKDIV = 0, the conversion time is equivalent to 24 instruction cycles.
When CKDIV = 1, the conversion time is equivalent to 48 instruction cycles.
The conversion time includes a sampling time of 6 cycles.

AADR1

Analog input select. These bits are used to select one of the four analog inputs; see
Table 12. They only can be changed when ADCI and ADCS are both LOW.

AADR0

Table 11 Analog-to-digital operation

ADCI

ADCS

OPERATION

ADC not busy; a conversion can be
started.

ADC busy; start of a new conversion is
blocked.

Conversion completed; start of a new
conversion is blocked.

Intermediate status for a maximum of
one machine cycle before conversion is
completed (ADCI = 1, ADCS = 0).

Table 12 Selection of analog input channel

AADR1 AADR0

SELECTED CHANNEL

AD0

AD1

AD2

AD3

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P80CL580; P83CL580

14 REDUCED POWER MODES

There are two software selectable modes of reduced
activity for further power reduction: Idle and Power-down.

14.1

Idle mode

Idle mode operation permits the interrupt, serial ports,
timer blocks, PWM and ADC to continue to function while
the clock to the CPU is halted.

Idle mode is entered by setting the IDL bit in the Power
Control Register (PCON.0, see Table 14). The instruction
that sets IDL is the last instruction executed in the normal
operating mode before the Idle mode is activated

Once in Idle mode, the CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status
Word and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in Table 13.

The following functions remain active during the Idle
mode:

�

Timer 0, Timer 1, Timer 2 and Timer 3

�

UART, I

C-bus interface

�

External interrupt

�

PWM0 (reset; output = HIGH)

�

ADC.

These functions may generate an interrupt or reset; thus
ending the Idle mode.

There are two ways to terminate the Idle mode:

1. Activation of any enabled interrupt will cause IDL

(PCON.0) to be cleared by hardware thus terminating
the Idle mode. The interrupt is serviced, and following
the RETI instruction, the next instruction to be
executed will be the one following the instruction that
put the device in the Idle mode. The flag bits GF0
(PCON.2) and GF1 (PCON.3) may be used to
determine whether the interrupt was received during
normal execution or during the Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits. When the Idle
mode is terminated by an interrupt, the service routine
can examine the status of the flag bits.

2. The second way of terminating the Idle mode is with an

external hardware reset, or an internal reset caused by
an overflow of Timer T2. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation. Reset redefines all SFRs but does
not affect the on-chip RAM.

14.2

Power-down mode

Operation in Power-down mode freezes the oscillator.
The internal connections which link both Idle and
Power-down signals to the clock generation circuit are
shown in Fig.15.

Power-down mode is entered by setting the PD bit in the
Power Control Register (PCON.1, see Table 14).
The instruction that sets PD is the last executed prior to
going into the Power-down mode.

Once in the Power-down mode, the oscillator is stopped.
The contents of the on-chip RAM and the SFRs are
preserved. The port pins output the value held by their
respective SFRs. ALE and PSEN are held LOW.

In the Power-down mode, V

may be reduced to

minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.

14.3

Wake-up from Power-down mode

When in Power-down mode the controller can be
woken-up with either the external interrupts INT2 to INT8,
or a reset operation. The wake-up operation has two basic
approaches as explained in Section 14.3.1; 14.3.2 and
illustrated in Fig.16.

14.3.1

AKE

UP USING

INT2

INT8

If any of the interrupts INT2 to INT8 are enabled, the
device can be woken-up from the Power-down mode with
the external interrupts. To ensure that the oscillator is
stable before the controller restarts, the internal clock will
remain inactive for 1536 oscillator periods. This is
controlled by an on-chip delay counter.

14.3.2

AKE

UP USING

RST

To wake-up the P8xCL580, the RST pin must be kept
HIGH for a minimum of 24 periods. The on-chip delay
counter is inactive. The user must ensure that the oscillator
is stable before any operation is attempted.

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14.4

Status of external pins

The status of the external pins during Idle and Power-down
mode is shown in Table 13. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.

If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor `p1';
see Fig.9(a).

Table 13 Status of external pins during Idle and Power-down modes

14.5

Power Control Register (PCON)

Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of
PCON is 0XX00000B.

Table 14 Power Control Register (address 87H)

Table 15 Description of PCON bits

MODE

MEMORY

ALE

PSEN

PWM0

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

Idle

internal

active

port data

external

active

floating

port data

address

port data

Power-down

internal

HIGH

port data

external

HIGH

floating

port data

SMOD

WLE

GF1

GF0

IDL

BIT

SYMBOL

DESCRIPTION

SMOD

Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial
port SIO0 is being used in modes 1, 2 or 3.

6 and 5

Reserved.

WLE

Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.

3 and 2

GF1 and GF0 General purpose flag bits.

Power-down bit. Setting this bit activates the Power-down mode. This bit can only be
set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD
takes precedence.

IDL

Idle mode bit. Setting this bit activates the Idle mode.

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15 I

C-BUS SERIAL I/O

The serial port supports the twin line I

C-bus, which

consists of a serial data line (SDA) and a serial clock line
(SCL). These lines also function as the I/O port lines P1.7
and P1.6 respectively.

The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.

The I

C-bus serial I/O has complete autonomy in byte

handling and operates in 4 modes:

�

Master transmitter

�

Master receiver

�

Slave transmitter

�

Slave receiver.

These functions are controlled by the Serial Control
Register S1CON. S1STA is the Status Register whose
contents may also be used as a vector to various service
routines. S1DAT is the Data Shift Register and S1ADR is
the Slave Address Register. Slave address recognition is
performed by on-chip hardware.

Figure 17 is the block diagram of the I

C-bus serial I/O.

Fig.17 Block diagram of I

C-bus serial I/O.

MLB199

SLAVE ADDRESS

S1ADR

SHIFT REGISTER

S1DAT

SDA

ARBITRATION SYNC LOGIC

SCL

BUS CLOCK GENERATOR

S1STA

INTERNAL BUS

S1CON

CONTROL REGISTER

STATUS REGISTER

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Product specification

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UART, I

C-bus and ADC

P80CL580; P83CL580

15.1

Serial Control Register (S1CON)

Table 16 Serial Control Register (SFR address D8H)

Table 17 Description of S1CON bits

CR2

ENS1

STA

STO

CR1

CR0

BIT

SYMBOL

DESCRIPTION

CR2

This bit along with bits CR1 (S1CON.1) and CR0 (S1CON.0) determines the serial clock
frequency when SIO is in the Master mode. See Table 18.

ENS1

ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1.

STA

START flag. When this bit is set in Slave mode, the SIO hardware checks the status of
the I

C-bus and generates a START condition if the bus is free or after the bus becomes

free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition.

STO

STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the I

C-bus, the SIO hardware clears the STO flag.

STO may also be set in Slave mode in order to recover from an error condition. In this
case no STOP condition is transmitted to the I

C-bus. However, the SIO hardware

behaves as if a STOP condition has been received and releases the SDA and SCL.
The SIO then switches to the not addressed slave receiver mode. The STOP flag is
cleared by the hardware.

SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:

�

A start condition is generated in Master mode

�

Own slave address has been received during AA = 1

�

The general call address has been received while GC (S1ADR.0) = 1 and AA = 1

�

A data byte has been received or transmitted in Master mode (even if arbitration is lost)

�

A data byte has been received or transmitted as selected slave

�

A Stop or Start condition is received as selected slave receiver or transmitter.

Assert Acknowledge. When this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:

�

Own slave address is received

�

General call address is received; GC (S1ADR.0) = 1

�

A data byte is received while the device is programmed to be a Master Receiver

�

A data byte is received while the device is a selected Slave Receiver.

When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.

CR1

These two bits along with the CR2 (S1CON.7) bit determine the serial clock frequency
when SIO is in the Master mode. See Table 18.

CR0

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P80CL580; P83CL580

Table 18 Selection of the serial clock frequency SCL in a Master mode of operation

15.2

Serial Status Register (S1STA)

S1STA is a read-only register.The contents of this register may be used as a vector to a service routine. This optimizes
the response time of the software and consequently that of the I

C-bus. The status codes for all possible modes of the

C-bus interface are given in Tables 21 to 25.

Table 19 Serial Status Register (address D9H)

Table 20 Description of S1STA bits

Table 21 MST/TRX mode

CR2

CR1

CR0

osc

DIVISOR

BIT RATE(kHz) AT f

osc

3.58 MHz

6 MHz

12 MHz

256

14.0

23.4

46.9

224

16.0

26.8

53.6

192

18.6

31.3

62.5

160

22.4

37.5

75.0

960

3.73

6.25

12.5

120

29.8

50.0

100.0

59.7

100.0

not allowed

SC4

SC3

SC2

SC1

SC0

BIT

SYMBOL

DESCRIPTION

3 to 7

SC4 to SC0

5-bit status code.

0 to 2

These three bits are always zero.

S1STA VALUE

DESCRIPTION

08H

A START condition has been transmitted.

10H

A repeated START condition has been transmitted.

18H

SLA and W have been transmitted, ACK has been received.

20H

SLA and W have been transmitted, ACK received.

28H

DATA of S1DAT has been transmitted, ACK received.

30H

DATA of S1DAT has been transmitted, ACK received.

38H

Arbitration lost in SLA, R/W or DATA.

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Table 22 MST/REC mode

Table 23 SLV/REC mode

Table 24 SLV/TRX mode

Table 25 Miscellaneous.

S1STA VALUE

DESCRIPTION

08H

A START condition has been transmitted.

10H

A repeated START condition has been transmitted.

38H

Arbitration lost while returning ACK.

40H

SLA and R have been transmitted, ACK received.

48H

SLA and R have been transmitted, ACK received.

50H

DATA has been received, ACK returned.

58H

DATA has been received, ACK returned.

S1STA VALUE

DESCRIPTION

60H

Own SLA and W have been received, ACK returned.

68H

Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned.

70H

General CALL has been received, ACK returned.

78H

Arbitration lost in SLA, R/W as MST. General CALL has been received.

80H

Previously addressed with own SLA. DATA byte received, ACK returned.

88H

Previously addressed with own SLA. DATA byte received, ACK returned.

90H

Previously addressed with general CALL. DATA byte has been received, ACK has been returned.

98H

Previously addressed with general CALL. DATA byte has been received, ACK has been returned.

A0H

A STOP condition or repeated START condition has been received while still addressed as SLV/REC
or SLV/TRX.

S1STA VALUE

DESCRIPTION

A8H

Own SLA and R have been received, ACK returned.

B0H

Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned.

B8H

DATA byte has been transmitted, ACK received.

C0H

DATA byte has been transmitted, ACK received.

C8H

Last DATA byte has been transmitted (AA = 0), ACK received.

S1STA VALUE

DESCRIPTION

00H

Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition.

F8H

No relevant state information available, SI = 0.

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Table 26 Symbols used in Tables 21 to 25

15.3

Data Shift Register (S1DAT)

S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or
received first; i.e. data shifted from right to left.

Table 27 Data Shift Register (SFR address DAH)

15.4

Address Register (S1ADR)

This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.

Table 28 Address Register (SFR address DBH)

Table 29 Description of S1ADR bits

SYMBOL

DESCRIPTION

SLA

7-bit slave address

Read bit

Write bit

ACK

Acknowledgement (acknowledge bit is logic 0)

ACK

No acknowledgement (acknowledge bit is logic 1)

DATA

8-bit data byte to or from I

C-bus

MST

Master

SLV

Slave

TRX

Transmitter

REC

Receiver

S1DAT.7

S1DAT.6

S1DAT.5

S1DAT.4

S1DAT.3

S1DAT.2

S1DAT.1

S1DAT.0

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

BIT

SYMBOL

DESCRIPTION

7 to 1

SLA6 to SLA0 Own slave address.

This bit is used to determine whether the general call address is recognized. When
GC = 0, the general call address is not recognized; when GC = 1, the general call
address is recognized.

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P80CL580; P83CL580

16 STANDARD SERIAL INTERFACE SIO0: UART

This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the register. (However, if the first byte has not
been read by the time the reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed via the
Special Function Register S0BUF. Writing to S0BUF loads
the transmit register and reading S0BUF accesses a
physically separate receive register.

The serial port can operate in 4 modes:

Mode 0 Serial data enters and exits through RXD.

TXD outputs the shift clock. Eight bits are
transmitted/received (LSB first). The baud rate is
fixed at

�

osc

. See Figs 19 and 20.

Mode 1 10 bits are transmitted (through TXD) or received

(through RXD): a start bit (logic 0), 8 data bits
(LSB first), and a stop bit (logic 1). On receive,
the stop bit goes into RB8 in Special Function
Register S0CON. The baud rate is variable.
See Figs 21 and 22.

Mode 2 11 bits are transmitted (through TXD) or received

(through RXD): start bit (logic 0), 8 data bits (LSB
first), a programmable 9

data bit, and a stop bit

(logic 1). On transmit, the 9

data bit (TB8 in

S0CON) can be assigned the value of a logic 0 or
logic 1. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the
9

data bit goes into RB8 in S0CON, while the

stop bit is ignored. The baud rate is
programmable to either

�

osc

See Figs 23 and 24.

Mode 3 11 bits are transmitted (through TXD) or received

(through RXD): a start bit (logic 0), 8 data bits
(LSB first), a programmable 9

data bit and a

stop bit (logic 1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable.
See Figs 25 and 26.

In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.

16.1

Multiprocessor communications

Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9

bit goes into RB8. The following bit is the stop bit.

The port can be programmed such that when the stop bit
is received, the serial port interrupt will be activated, but
only if RB8 = 1. This feature is enabled by setting bit SM2
in S0CON. One use of this feature, in multiprocessor
systems, is as follows.

When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9

bit is HIGH in an

address byte and LOW in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be sent. The slaves that
were not being addressed leave their SM2 bits set and go
on about their business, ignoring the coming data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.

1997 Mar 14

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C-bus and ADC

P80CL580; P83CL580

16.2

Serial Port Control and Status Register (S0CON)

The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the
mode selection bits, but also the 9

data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits

(TI and RI).

Table 30 Serial Port Control Register (address 98H)

Table 31 Description of S0CON bits

Table 32 Selection of the serial port modes

SMO

SM1

SM2

REN

TB8

RB8

BIT

SYMBOL

DESCRIPTION

SM0

These bits are used to select the serial port mode; see Table 32.

SM1

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In these modes,
if SM2 = 1, then RI will not be activated if the received 9

data bit (RB8) is a logic 0.

In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received.
In Mode 0, SM2 should be a logic 0.

REN

Enables serial reception and is set by software to enable reception, and cleared by
software to disable reception.

TB8

Is the 9

data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as

desired.

RB8

In Modes 2 and 3, is the 9

data bit received. In Mode 1, if SM2 = 0 then RB8 is the stop

bit that was received. In Mode 0, RB8 is not used.

The transmit interrupt flag. Set by hardware at the end of the 8

bit time in Mode 0, or

at the beginning of the stop bit time in the other modes, in any serial transmission. Must
be cleared by software.

The receive interrupt flag. Set by hardware at the end of the 8

bit time in Mode 0, or

halfway through the stop bit time in the other modes, in any serial transmission (except
see SM2). Must be cleared by software.

SMO

SM1

MODE

DESCRIPTION

BAUD RATE

Mode 0

Shift register

�

osc

Mode 1

8-bit UART

variable

Mode 2

9-bit UART

�

osc

Mode 3

9-bit UART

variable

1997 Mar 14

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P80CL580; P83CL580

16.3

Baud rates

The baud rate in Mode 0 is fixed and may be calculated as:

The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON and may be
calculated as:

�

If SMOD = 0 (value on reset), the baud rate is

�

osc

�

If SMOD = 1, the baud rate is

�

osc

The baud rates in Modes 1 and 3 are determined by the
Timer 1 or Timer 2 overflow rate.

16.3.1

SING

IMER

TO GENERATE BAUD RATES

When Timer 1 is used as the Baud Rate Generator, the
baud rates in Modes 1 and 3 are determined by the

Baud Rate

osc

--------

Baud Rate

SMOD

-----------------

osc

�

Timer 1 overflow rate and the value of the SMOD bit as
follows:

The Timer 1 interrupt should be disabled in this
application. The Timer itself can be configured for either
`timer' or `counter' operation in any of its 3 running modes.
In most typical applications, it is configured for `timer'
operation, in the Auto-reload mode (high nibble of
TMOD = 0010B). In this case the baud rate is given by the
formula:

By configuring Timer 1 to run as a 16-bit timer (high nibble
of TMOD = 0001B), and using the Timer 1 interrupt to do
a 16-bit software reload, very low baud rates can be
achieved. Table 33 lists commonly used baud rates and
how they can be obtained from Timer 1.

Baud Rate

SMOD

-----------------

Timer 1 Overflow Rate.

�

Baud Rate

SMOD

-----------------

osc

256

TH1

�

(

)

�

{

}

--------------------------------------------------------

�

Table 33 Commonly used baud rates generated by Timer 1

Notes

1. Maximum in Mode 0.

2. X = don't care.

3. Maximum in Mode 2.

4. Maximum in Modes 1 and 3.

BAUD RATE(kb/s)

osc

(MHz)

SMOD

C/T

TIMER 1 MODE

RELOAD VALUE

1000.0

(1)

12.000

(2)

375.0

(3)

12.000

62.5

(4)

12.000

Mode 2

FFH

19.2

11.059

Mode 2

FDH

9.6

11.059

Mode 2

FDH

4.8

11.059

Mode 2

FAH

2.4

11.059

Mode 2

F4H

1.2

11.059

Mode 2

E8H

137.5

11.986

Mode 2

1DH

110.0

6.000

Mode 2

72H

110.0

12.000

Mode 1

FEEBH

1997 Mar 14

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P80CL580; P83CL580

16.3.2

SING

IMER

TO GENERATE BAUD RATES

Timer 2 is selected as a Baud Rate Generator by setting
the RTCLK bit in T2CON. The Baud Rate Generator mode
is similar to the Auto-reload mode, in that a roll-over in TH2
causes Timer 2 registers to be reloaded with the 16-bit
value held in the registers RCAP2H and RCAP2L, which
are preset by software. Baud rates in Modes 1 and 3 are
determined by Timer 2's overflow rate as specified below.

The Timer 2 can be configured for either `timer' or `counter'
operation. In the most typical applications, it is configured
for `timer' operation (C/T2 = 0). `Timer' operation is slightly
different for Timer 2 when it is being used as a Baud Rate
Generator. Normally, as a timer it would increment every

machine cycle at a frequency of

�

osc

. However, as a

Baud Rate Generator it increments every state time at a

frequency of

�

osc

. In this case the baud rate in

Modes 1 and 3 is determined as:

Baud Rate

Timer 2 Overflow Rate

------------------------------------------------------------

Baud Rate

osc

65536

RCAP2H; RCAP2L

(

)

�

{

}

�

------------------------------------------------------------------------------------------------------

Where (RCAP2H; RCAP2L) is the content of registers
RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

The Baud Rate Generator mode for Timer 2 is shown in
Fig.18. This figure is only valid if RTCLK = 1. At roll-over
TH2 does not set the TF2 bit in T2CON and therefore, will
not generate an interrupt. Consequently, the Timer 2
interrupt does not need to be disabled when in the Baud
Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW
transition on T2EX will set the EXF2 bit, also in T2CON,
but will not cause a reload from (RCAP2H; RCAP2L) to
(TH2, TL2). Therefore, in this mode T2EX may be used as
an additional external interrupt.

When Timer 2 is operating as a timer (TR2 = 1), in the
Baud Rate Generator mode, registers TH2 and TL2 should
not be accessed (read or write). Under these conditions
the timer is being incremented every state time and
therefore the results of a read or write may not be
accurate. The registers RCAP2H and RCAP2L however,
may be read but not written to. A write might overlap a
reload and cause write and/or reload errors. If a write
operation is required, Timer 2 or RCAP2H/RCAP2L
should first be turned off by clearing the TR2 bit.

handbook, full pagewidth

MGD622

TL2

(8 BITS)

TR2

control

TH2

(8 BITS)

RCAP2L

RCAP2H

EXF2

EXEN2

control

C/T2 = 0

C/T2 = 1

T2 PIN

OSC

transition

detector

T2EX PIN

TIMER 2 interrupt
(additional external interrupt)

(note: divided by 2

not by 12)

RTCLK

RELOAD

CLK

UART receive/

transmit clock

SMOD

TIMER 1

overflow

Fig.18 Timer 2 in Baud Rate Generator mode.

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Product specification

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UART, I

C-bus and ADC

P80CL580; P83CL580

17 INTERRUPT SYSTEM

External events and the real-time-driven on-chip
peripherals require service by the CPU at unpredictable
times. To tie the asynchronous activities of these functions
to normal program execution a multiple-source,
two-priority-level, nested interrupt system is provided.
The system is shown in Fig.27. The P8xCL580
acknowledges interrupt requests from fifteen sources as
follows:

�

INT0 to INT8

�

Timer 0, Timer 1 and Timer 2

�

C-bus serial I/O

�

UART

�

ADC.

Each interrupt vectors to a separate location in Program
Memory for its service routine. Each source can be
individually enabled or disabled by corresponding bits in
the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. Figure 27 shows the interrupt
system.

17.1

External interrupts INT2 to INT8

Port 1 lines serve an alternative purpose as seven
additional interrupts INT2 to INT8. When enabled, each of
these lines may wake-up the device from the Power-down
mode. Using the Interrupt Polarity Register (IX1), each pin
may be initialized to be either active HIGH or active LOW.
IRQ1 is the Interrupt Request Flag Register. If the interrupt
is enabled, each flag will be set on an interrupt request but
must be cleared by software, i.e. via the interrupt software
or when the interrupt is disabled.

Port 1 interrupts are level sensitive. A Port 1 interrupt will
be recognized when a level (HIGH or LOW depending on
the Interrupt Polarity Register) on P1.n is held active for at
least one machine cycle. The interrupt request is not
serviced until the next machine cycle. Figure 28 shows the
external interrupt system.

17.2

Interrupt priority

Each interrupt source can be set to either a high priority or
to a low priority. If a low priority interrupt is received
simultaneously with a high priority interrupt, the high
priority interrupt will be dealt with first.

If interrupts of the same priority are requested
simultaneously, the processor will branch to the interrupt
polled first, according to the sequence shown in Table 34
and in Fig.27. The `vector address' is the ROM location
where the appropriate interrupt service routine starts.

Table 34 Interrupt vector polling sequence

A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine
cannot be interrupted.

SYMBOL

VECTOR

ADDRESS (HEX)

SOURCE

X0 (first)

0003

External 0

002B

C port

0053

External 5

000B

Timer 0

0033

Timer 2

005B

External 6

0013

External 1

003B

External 2

0063

External 7

001B

Timer 1

0043

External 3

006B

External 8

0023

UART

004B

External 4

ADC (last)

0073

ADC

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P80CL580; P83CL580

17.3.1

NTERRUPT

NABLE

EGISTER

(IEN0)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 36 Interrupt Enable Register (SFR address A8H)

Table 37 Description of IEN0 bits

17.3.2

NTERRUPT

NABLE

EGISTER

(IEN1)

Bit values: 0 = interrupt disabled; 1 = interrupt enabled.

Table 38 Interrupt Enable Register (SFR address E8H)

Table 39 Description of IEN1 bits

ET2

ES1

ES0

ET1

EX1

ET0

EX0

BIT

SYMBOL

DESCRIPTION

General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any
individually enabled interrupt will be accepted.

ET2

enable T2 interrupt

ES1

enable I

C interrupt

ES0

enable UART SIO interrupt

ET1

enable Timer 1 interrupt (T1)

EX1

enable external interrupt 1

ET0

enable Timer 0 interrupt (T0)

EX0

enable external interrupt 0

EAD

EX8

EX7

EX6

EX5

EX4

EX3

EX2

BIT

SYMBOL

DESCRIPTION

EAD

Enable ADC interrupt.

EX8

enable external interrupt 8

EX7

enable external interrupt 7

EX7

enable external interrupt 6

EX5

enable external interrupt 5

EX4

enable external interrupt 4

EX3

enable external interrupt 3

EX2

enable external interrupt 2

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C-bus and ADC

P80CL580; P83CL580

17.3.3

NTERRUPT

RIORITY

EGISTER

(IP0)

Bit values: 0 = low priority; 1 = high priority.

Table 40 Interrupt Priority Register (SFR address B8H)

Table 41 Description of IP0 bits

17.3.4

NTERRUPT

RIORITY

EGISTER

(IP1)

Bit values: 0 = low priority; 1 = high priority.

Table 42 Interrupt Priority Register (SFR address F8H)

Table 43 Description of IP1 bits

PT2

PS1

PS0

PT1

PX1

PT0

PX0

BIT

SYMBOL

DESCRIPTION

reserved

PT2

Timer 2 interrupt priority level

PS1

C interrupt priority level

PS0

UART SIO interrupt priority level

PT1

Timer 1 interrupt priority level

PX1

external interrupt 1 priority level

PT0

Timer 0 interrupt priority level

PX0

external interrupt 0 priority level

PADC

PX8

PX7

PX6

PX5

PX4

PX3

PX2

BIT

SYMBOL

DESCRIPTION

PADC

ADC interrupt priority level

PX8

external interrupt 8 priority level

PX7

external interrupt 7 priority level

PX6

external interrupt 6 priority level

PX5

external interrupt 5 priority level

PX4

external interrupt 4 priority level

PX3

external interrupt 3 priority level

PX2

external interrupt 2 priority level

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17.3.5

NTERRUPT

OLARITY

EGISTER

(IX1)

Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external
interrupt to an active HIGH or active LOW respectively.

Table 44 Interrupt Polarity Register (SFR address E9H)

Table 45 Description of IX1 bits

17.3.6

NTERRUPT

EQUEST

LAG

EGISTER

(IRQ1)

Table 46 Interrupt Request Flag Register (SFR address C0H)

Table 47 Description of IRQ1 bits

IL8

IL7

IL6

IL5

IL4

IL3

IL2

BIT

SYMBOL

DESCRIPTION

reserved

IL8

external interrupt 8 polarity level

IL7

external interrupt 7 polarity level

IL6

external interrupt 6 polarity level

IL5

external interrupt 5 polarity level

IL4

external interrupt 4 polarity level

IL3

external interrupt 3 polarity level

IL2

external interrupt 2 polarity level

IQ8

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

BIT

SYMBOL

DESCRIPTION

reserved

IQ8

external interrupt 8 request flag

IQ7

external interrupt 7 request flag

IQ6

external interrupt 6 request flag

IQ5

external interrupt 5 request flag

IQ4

external interrupt 4 request flag

IQ3

external interrupt 3 request flag

IQ2

external interrupt 2 request flag

1997 Mar 14

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P80CL580; P83CL580

18 OSCILLATOR CIRCUITRY

The on-chip oscillator circuitry of the P8xCL580 is a
single-stage inverting amplifier biased by an internal
feedback resistor. The oscillator circuit is shown in Fig.30.
For operation as a standard quartz oscillator, no external
components are needed, except for the 32 kHz option.
When using external capacitors, ceramic resonators, coils
and RC networks to drive the oscillator, five different
configurations are supported (see Table 48 and Fig.29).

In the Power-down mode the oscillator is stopped and
XTAL1 is pulled HIGH. The oscillator invertor is switched
off to ensure no current will flow regardless of the voltage
at XTAL1, for configurations (a), (b), (c), (d), (e) and (g) of
Fig.29.

To drive the device with an external clock source, apply the
external clock signal to XTAL1, and leave XTAL2 to float,
as shown in Fig.29(f). There are no requirements on the
duty cycle of the external clock, since the input to the
internal clocking circuitry is buffered by a flip-flop.

Various oscillator options are provided for optimum
on-chip oscillator performance; these are specified in
Table 48 and shown in Fig.29. The required option should
be stated when ordering.

Table 48 Oscillator options

OPTION

APPLICATION

Oscillator 1

For 32 kHz clock applications with external trimmer for frequency adjustment. A 4.7 M

bias resistor

is needed for use in parallel with the crystal; see Fig.29(c).

Oscillator 2

Low-power, low-frequency operations using LC components; see Fig.29(e).

Oscillator 3

Medium frequency range applications.

Oscillator 4

High frequency range applications.

RC oscillator

RC oscillator configuration; see Figs 29(g) and 31.

handbook, full pagewidth

MLA577

VDD

XTAL1

XTAL2

(d)

XTAL1

XTAL2

(e)

XTAL1

XTAL2

(f)

XTAL1

XTAL2

(g)

n.c.

XTAL1

XTAL2

(b)

XTAL1

XTAL2

(c)

XTAL1

XTAL2

(a)

STANDARD

QUARTZ

OSCILLATOR

QUARTZ OSCILLATOR

WITH EXTERNAL

CAPACITORS

32 kHz

OSCILLATOR

CERAMIC

RESONATOR

LC - OSCILLATOR

EXTERNAL CLOCK

RC - OSCILLATOR

Fig.29 Oscillator configurations.

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C-bus and ADC

P80CL580; P83CL580

Table 50 Oscillator equivalent circuit parameters

The equivalent circuit data of the internal oscillator compares with that of matched crystals.

SYMBOL

PARAMETER

OPTION

CONDITION

MIN.

TYP.

MAX.

UNIT

transconductance

Oscillator 1; 32 kHz

amb

= +25

�

= 4.5 V

�

Oscillator 2

200

600

1000

�

Oscillator 3

400

1 500

4000

�

Oscillator 4

1000

4000

10000

�

input capacitance

Oscillator 1; 32 kHz

3.0

Oscillator 2

8.0

Oscillator 3

8.0

Oscillator 4

8.0

output capacitance

Oscillator 1; 32 kHz

Oscillator 2

8.0

Oscillator 3

8.0

Oscillator 4

8.0

output resistance

Oscillator 1; 32 kHz

3800

Oscillator 2

Oscillator 3

Oscillator 4

5.0

Fig.32 Oscillator equivalent circuit diagram.

handbook, full pagewidth

MLA578

C1 i

R f

g m

C2 i

R 2

XTAL1

XTAL2

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19 RESET

To initialize the P8xCL580 a reset is performed by either of
three methods:

�

Applying an external signal to the RST pin

�

Via Power-on-reset circuitry

�

Watchdog Timer.

A reset leaves the internal registers as shown in
Chapter 20. The reset state of the port pins is
mask-programmable and can be defined by the user.

19.1

External reset using the RST pin

The reset input for the P8xCL580 is RST. A Schmitt trigger
is used at the input for noise rejection. The output of the
Schmitt trigger is sampled by the reset circuitry every
machine cycle. A reset is accomplished by holding the
RST pin HIGH for at least two machine cycles
(24 oscillator periods) while the oscillator is running.
The CPU responds by executing an internal reset. Port
pins adopt their reset state immediately after the RST goes
HIGH. During reset, ALE and PSEN are held HIGH.

The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW. The reset
circuitry is also affected by the Watchdog timer; see
Section 11.4. The internal RAM is not affected by reset.
When V

is turned on, the RAM contents are

indeterminate.

19.2

Power-on-reset

The device contains on-chip circuitry which switches the
port pins to the customer defined logic level as soon as
V

exceeds 1.3 V; if the mask option `ON' has been

chosen. As soon as the minimum supply voltage is
reached, the oscillator will start up. However, to ensure
that the oscillator is stable before the controller starts, the
clock signals are gated away from the CPU for a further
1536 oscillator periods. During that time the CPU is held in
a reset state. A hysteresis of approximately 50 mV at a
typical power-on switching level of 1.3 V will ensure
correct operation (see Fig.35).

The on-chip Power-on reset circuitry can also be switched
off via the mask option `OFF'. This option reduces the
Power-down current to typically 800 nA and can be
chosen if external reset circuitry is used. For applications
not requiring the internal reset, option `OFF' should be
chosen.

An automatic reset can be obtained by connecting the RST
pin to V

via a 10

�

F capacitor. At power-on, the voltage

on the RST pin is equal to V

minus the capacitor voltage,

and decreases from V

as the capacitor charges through

the internal resistor (R

RST

) to ground. The larger the

capacitor, the more slowly V

RST

decreases. V

RST

must

remain above the lower threshold of the Schmitt trigger
long enough to effect a complete reset. The time required
is the oscillator start-up time, plus 2 machine cycles.
The Power-on-reset circuitry is shown in Fig.34.

Fig.33 Reset configuration.

handbook, halfpage

MGC757

SCHMITT

TRIGGER

RESET

CIRCUITRY

RST

T3 overflow

POR

RST

Fig.34 Recommended Power-on-reset circuitry.

handbook, halfpage

MGC760

P80CL580
P83CL580

�

RST

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P80CL580; P83CL580

20 SPECIAL FUNCTION REGISTERS OVERVIEW

The P8xCL580 has 40 SFRs available to the user.

ADDRESS

(HEX)

NAME

RESET VALUE

(B)

FUNCTION

00000000

Watchdog Timer

PWMP

00000000

Prescaler Frequency Control Register

PWM0

00000000

Pulse Width Register 0

IP1

00000000

Interrupt Priority Register (INT2 to INT8, ADC)

(1)

00000000

B Register

IX1

00000000

Interrupt Polarity Register

IEN1

(1)

00000000

Interrupt Enable Register 1

ACC

(1)

00000000

Accumulator

S1ADR

00000000

C-bus Slave Address Register

S1DAT

00000000

C-bus Data Shift Register

S1STA

11111000

C-bus Serial Status Register

S1CON

(1)

00000000

C-bus Serial Control Register

PSW

(1)

00000000

Program Status Word

TH2

00000000

Timer 2 High byte

TL2

00000000

Timer 2 Low byte

RCAP2H

00000000

Timer 2 Reload/Capture Register High byte

RCAP2L

00000000

Timer 2 Reload/Capture Register Low byte

T2CON

(1)

00000000

Timer/Counter 2 Control Register

ADCH

11111111

ADC Result Register

ADCON

0000000

ADC Control Register

XXXXXXXX

(2)

Digital I/O Port Register 4

IRQ1

(1)

00000000

Interrupt Request Flag Register

1997 Mar 14

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C-bus and ADC

P80CL580; P83CL580

Notes

1. Bit addressable register.

2. Port reset state determined by the customer.

IP0

(1)

0000000

Interrupt Priority Register 0

(1)

XXXXXXXX

(2)

Digital I/O Port Register 3

IEN0

(1)

00000000

Interrupt Enable Register

(1)

XXXXXXXX

(2)

Digital I/O Port Register 2

S0BUF

XXXXXXXX

Serial Data Buffer Register 0

S0CON

(1)

00000000

Serial Port Control Register 0

(1)

XXXXXXXX

(2)

Digital I/O Port Register 1

TH1

00000000

Timer 1 High byte

TH0

00000000

Timer 0 High byte

TL1

00000000

Timer 1 Low byte

TL0

00000000

Timer 0 Low byte

TMOD

00000000

Timer 0 and 1 Mode Control Register

TCON

(1)

00000000

Timer 0 and 1 Control/External Interrupt Control Register

PCON

0XX00000

Power Control Register

DPH

00000000

Data Pointer High byte

DPL

00000000

Data Pointer Low byte

00000111

Stack Pointer

(1)

XXXXXXXX

(2)

Digital I/O Port Register 0

ADDRESS

(HEX)

NAME

RESET VALUE

(B)

FUNCTION

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

21 INSTRUCTION SET

The P8xCL580 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes
byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing
modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1

�

s and 45 instructions execute in 2

�

s. Multiply and divide instructions execute in

�

For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 55.

Table 51 Instruction set description: Arithmetic operations

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Arithmetic operations

ADD

A,Rr

Add register to A

ADD

A,direct

Add direct byte to A

ADD

A,@Ri

Add indirect RAM to A

26, 27

ADD

A,#data

Add immediate data to A

ADDC

A,Rr

Add register to A with carry flag

ADDC

A,direct

Add direct byte to A with carry flag

ADDC

A,@Ri

Add indirect RAM to A with carry flag

36, 37

ADDC

A,#data

Add immediate data to A with carry flag

SUBB

A,Rr

Subtract register from A with borrow

SUBB

A,direct

Subtract direct byte from A with borrow

SUBB

A,@Ri

Subtract indirect RAM from A with borrow

96, 97

SUBB

A,#data

Subtract immediate data from A with borrow

INC

Increment A

INC

Increment register

INC

direct

Increment direct byte

INC

@Ri

Increment indirect RAM

06, 07

DEC

Decrement A

DEC

Decrement register

DEC

direct

Decrement direct byte

DEC

@Ri

Decrement indirect RAM

16, 17

INC

DPTR

Increment data pointer

MUL

Multiply A and B

DIV

Divide A by B

Decimal adjust A

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Table 52 Instruction set description: Logic operations

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Logic operations

ANL

A,Rr

AND register to A

ANL

A,direct

AND direct byte to A

ANL

A,@Ri

AND indirect RAM to A

56, 57

ANL

A,#data

AND immediate data to A

ANL

direct,A

AND A to direct byte

ANL

direct,#data

AND immediate data to direct byte

ORL

A,Rr

OR register to A

ORL

A,direct

OR direct byte to A

ORL

A,@Ri

OR indirect RAM to A

46, 47

ORL

A,#data

OR immediate data to A

ORL

direct,A

OR A to direct byte

ORL

direct,#data

OR immediate data to direct byte

XRL

A,Rr

Exclusive-OR register to A

XRL

A,direct

Exclusive-OR direct byte to A

XRL

A,@Ri

Exclusive-OR indirect RAM to A

66, 67

XRL

A,#data

Exclusive-OR immediate data to A

XRL

direct,A

Exclusive-OR A to direct byte

XRL

direct,#data

Exclusive-OR immediate data to direct byte

CLR

Clear A

CPL

Complement A

Rotate A left

RLC

Rotate A left through the carry flag

Rotate A right

RRC

Rotate A right through the carry flag

SWAP

Swap nibbles within A

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Table 53 Instruction set description: Data transfer

Note

1. MOV A,ACC is not permitted.

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Data transfer

MOV

A,Rr

Move register to A

MOV

A,direct (note 1) Move direct byte to A

MOV

A,@Ri

Move indirect RAM to A

E6, E7

MOV

A,#data

Move immediate data to A

MOV

Rr,A

Move A to register

MOV

Rr,direct

Move direct byte to register

MOV

Rr,#data

Move immediate data to register

MOV

direct,A

Move A to direct byte

MOV

direct,Rr

Move register to direct byte

MOV

direct,direct

Move direct byte to direct

MOV

direct,@Ri

Move indirect RAM to direct byte

86, 87

MOV

direct,#data

Move immediate data to direct byte

MOV

@Ri,A

Move A to indirect RAM

F6, F7

MOV

@Ri,direct

Move direct byte to indirect RAM

A6, A7

MOV

@Ri,#data

Move immediate data to indirect RAM

76, 77

MOV

DPTR,#data 16

Load data pointer with a 16-bit constant

MOVC

A,@A+DPTR

Move code byte relative to DPTR to A

MOVC

A,@A+PC

Move code byte relative to PC to A

MOVX

A,@Ri

Move external RAM (8-bit address) to A

E2, E3

MOVX

A,@DPTR

Move external RAM (16-bit address) to A

MOVX

@Ri,A

Move A to external RAM (8-bit address)

F2, F3

MOVX

@DPTR,A

Move A to external RAM (16-bit address)

PUSH

direct

Push direct byte onto stack

POP

direct

Pop direct byte from stack

XCH

A,Rr

Exchange register with A

XCH

A,direct

Exchange direct byte with A

XCH

A,@Ri

Exchange indirect RAM with A

C6, C7

XCHD

A,@Ri

Exchange LOW-order digit indirect RAM with A

D6, D7

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Table 54 Instruction set description: Boolean variable manipulation, Program and machine control

MNEMONIC

DESCRIPTION

BYTES

CYCLES

OPCODE

(HEX)

Boolean variable manipulation

CLR

Clear carry flag

CLR

bit

Clear direct bit

SETB

Set carry flag

SETB

bit

Set direct bit

CPL

Complement carry flag

CPL

bit

Complement direct bit

ANL

C,bit

AND direct bit to carry flag

ANL

C,/bit

AND complement of direct bit to carry flag

ORL

C,bit

OR direct bit to carry flag

ORL

C,/bit

OR complement of direct bit to carry flag

MOV

C,bit

Move direct bit to carry flag

MOV

bit,C

Move carry flag to direct bit

Program and machine control

ACALL

addr11

Absolute subroutine call

�

LCALL

addr16

Long subroutine call

RET

Return from subroutine

RETI

Return from interrupt

AJMP

addr11

Absolute jump

LJMP

addr16

Long jump

SJMP

rel

Short jump (relative address)

JMP

@A+DPTR

Jump indirect relative to the DPTR

rel

Jump if A is zero

JNZ

rel

Jump if A is not zero

rel

Jump if carry flag is set

JNC

rel

Jump if carry flag is not set

bit,rel

Jump if direct bit is set

JNB

bit,rel

Jump if direct bit is not set

JBC

bit,rel

Jump if direct bit is set and clear bit

CJNE

A,direct,rel

Compare direct to A and jump if not equal

CJNE

A,#data,rel

Compare immediate to A and jump if not equal

CJNE

Rr,#data,rel

Compare immediate to register and jump if not equal

CJNE

@Ri,#data,rel Compare immediate to indirect and jump if not equal

B6, B7

DJNZ

Rr,rel

Decrement register and jump if not zero

DJNZ

direct,rel

Decrement direct and jump if not zero

NOP

No operation

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Table 55 Description of the mnemonics in the Instruction set

MNEMONIC

DESCRIPTION

Data addressing modes

Working register R0-R7.

direct

128 internal RAM locations and any special function register (SFR).

@Ri

Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.

#data

8-bit constant included in instruction.

#data 16

16-bit constant included as bytes 2 and 3 of instruction.

bit

Direct addressed bit in internal RAM or SFR.

addr16

16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.

addr11

111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.

rel

Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is

128 to +127 bytes relative to first byte of the following instruction.

Hexadecimal opcode cross-reference

8, 9, A, B, C, D, E, F.

�

1, 3, 5, 7, 9, B, D, F.

0, 2, 4, 6, 8, A, C, E.

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

able 56

Instruction map

Note

MOV A, ACC is not a valid instruction.

First hexadecimal character of opcode

Second hexadecimal character of opcode

NOP

AJMP

addr1

LJMP

addr16

INC

direct

INC @Ri

INC Rr

01234567

JBC

bit,rel

ACALL

addr1

LCALL

addr16

RRC

DEC

direct

DEC @Ri

DEC Rr

01234567

bit,rel

AJMP

addr1

RET

ADD

A,#data

ADD

A,direct

ADD A,@Ri

ADD A,Rr

01234567

JNB

bit,rel

ACALL

addr1

RETI

RLC

ADDC

A,#data

ADDC

A,direct

ADDC A,@Ri

ADDC A,Rr

01234567

rel

AJMP

addr1

ORL

direct,A

ORL

direct,#data

ORL

A,#data

ORL

A,direct

ORL A,@Ri

ORL A,Rr

01234567

JNC

rel

ACALL

addr1

ANL

direct,A

ANL

direct,#data

ANL

A,#data

ANL

A,direct

ANL A,@Ri

ANL A,Rr

01234567

rel

AJMP

addr1

XRL

direct,A

XRL

direct,#data

XRL

A,#data

XRL

A,direct

XRL A,@Ri

XRL A,Rr

01234567

JNZ

rel

ACALL

addr1

ORL

C,bit

JMP

@A+DPTR

MOV

A,#data

MOV

direct,#data

MOV @Ri,#data

MOV Rr

,#data

01234567

SJMP

rel

AJMP

addr1

ANL

C,bit

MOVC

A,@A+PC

DIV

MOV

direct,direct

MOV direct,@Ri

MOV direct,Rr

01234567

MOV

DTPR,#data16

ACALL

addr1

MOV

bit,C

MOVC

A,@A+DPTR

SUBB

A,#data

SUBB

A,direct

SUBB A,@Ri

SUB A,Rr

01234567

ORL

C,/bit

AJMP

addr1

MOV

bit,C

INC

DPTR

MUL

MOV @Ri,direct

MOV Rr

,direct

01234567

ANL

C,/bit

ACALL

addr1

CPL

bit

CPL

CJNE

A,#data,rel

CJNE

A,direct,rel

CJNE @Ri,#data,rel

CJNE Rr

,#data,rel

01234567

PUSH

direct

AJMP

addr1

CLR

bit

CLR

XCH

A,direct

XCH A,@Ri

XCH A,Rr

01234567

POP

direct

ACALL

addr1

SETB

bit

SETB

DJNZ

direct,rel

XCHD A,@Ri

DJNZ Rr

,rel

01234567

MOVX

A,@DTPR

AJMP

addr1

MOVX A,@Ri

CLR

MOV

A,direct

(1)

MOV A,@Ri

MOV A,Rr

01234567

MOVX

@DTPR,A

ACALL

addr1

MOVX @Ri,A

CPL

MOV

direct,A

MOV @Ri,A

MOV Rr

01234567

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

22 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

23 DC CHARACTERISTICS

= 1.8 to 6 V; V

= 0 V; T

amb

25 to +55

�

C; see notes 1 and 2; all voltages with respect to V

unless specified.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.5

+6.5

input voltage on any pin with respect to ground (V

)

0.5

+ 0.5 V

DC current on any input

5.0

+5.0

DC current on any output

5.0

+5.0

tot

total power dissipation

300

stg

storage temperature

+150

�

amb

operating ambient temperature

+85

�

operating junction temperature

+125

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

operating

2.5

6.0

RAM retention voltage in
Power-down mode

1.0

6.0

supply current operating

= 5 V; f

CLK

= 12 MHz; note 3

27.0

= 3 V; f

CLK

= 3.58 MHz; note 3

5.0

DD(idle)

supply current Idle mode

= 5 V; f

CLK

= 12 MHz; note 4

10.0

= 3 V; f

CLK

= 3.58 MHz; note 4

3.0

DD(pd)

Power-down current

= 1.8 V; T

amb

= 25

�

C; note 5

�

Inputs (note 6)

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input leakage current (Port 0; EA)

�

Outputs

LOW level output current
(except SDA; SCL)

= 5 V; V

= 0.4 V

1.6

= 2.5 V; V

= 0.4 V

0.7

LOW level output current SDA; SCL V

= 5 V; V

= 0.4 V

3.0

LOW level output current PWM0

= 5 V; V

= 0.4 V

3.2

= 2.5 V; V

= 0.4 V

1.6

HIGH level output current PWM0

= 5 V; V

= V

0.4 V

3.2

= 2.5 V; V

= V

0.4 V

1.6

HIGH level output current
(push-pull options only)

= 5 V; V

= V

0.4 V

1.6

= 2.5 V; V

= V

0.4 V

0.7

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Notes to the DC characteristics

1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the LOW level output

voltage of ALE, Port 1 and Port 3 pins when these make a HIGH-to-LOW transition during bus operations. The noise
is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW
transitions during bus operations. In the most adverse conditions (capacitive loading

100 pF), the noise pulse on

the ALE line may exceed 0.8 V. In such events it may be required to qualify ALE with a Schmitt trigger, or use an
address latch with a Schmitt trigger strobe input.

2. Capacitive loading on Ports 0 and 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall

below the 0.9V

specification when the address bits are stabilizing.

3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10 ns;

= V

; V

= V

; XTAL2 not connected; EA = RST = Port 0 = V

4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t

= t

= 10 ns;

= V

; V

= V

; XTAL2 not connected; EA = Port 0 = V

5. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = Port 0 = V

;

RST = V

6. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I

C-bus specification. Therefore, an input voltage

below 0.3V

will be recognized as a logic 0 and an input voltage above 0.7V

will be recognized as a logic 1.

7. V

= 2.7 to 6 V; V

= 0 V; V

SSA

= 0 V; V

ref(p)(A)

= V

; T

amb

40 to +85

�

C, unless otherwise specified.

xtal(min)

= 250 kHz.

8. Absolute error: the maximum difference between actual and ideal code transitions. Absolute error accounts for all

deviations of an actual converter from an ideal converter.

9. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code

transition.

10. Differential non-linearity: the difference between the actual and ideal code widths.

11. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken

from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on
sampling basis.

input current logic 0

= 5 V; V

= 0.4 V

100

�

= 2.5 V; V

= 0.4 V

�

ITL

input current logic 0; HIGH-to-LOW
transition

= 5 V; V

= 0.5V

1.0

= 2.5 V; V

= 0.5V

500

�

RST

RST pull-down resistor

200

Analog inputs (note 7)

IN(A)

analog input voltage

SSA

ref(p)(A)

reference voltage

2.7

ref

resistance between
V

ref(p)(A)

and V

SSA

100

AIN

analog on-chip input capacitance

absolute error (note 8)

�

LSB

zero-offset error (note 9)

�

LSB

differential non-linearity (note 10)

�

LSB

ctc

channel-to-channel matching
(note 11)

�

LSB

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

24 AC CHARACTERISTICS

= 5 V; V

= 0 V; T

amb

40 to +85

�

C; C

= 50 pF for Port 0, ALE and PSEN; C

= 40 pF for all other outputs

unless specified; t

CLK

= 1/ f

CLK

SYMBOL

PARAMETER

osc

= 12 MHz

osc

= VARIABLE

UNIT

MIN.

MAX.

MIN.

MAX.

Program Memory (Fig.41)

LHLL

ALE pulse width

127

CLK

AVLL

address valid to ALE LOW

CLK

LLAX

address hold after ALE LOW

CLK

LLIV

ALE LOW to valid instruction in

233

CLK

100 ns

LLPL

ALE LOW to PSEN LOW

CLK

PLPH

PSEN pulse width

215

CLK

PLIV

PSEN LOW to valid instruction in

125

CLK

125 ns

PXIX

input instruction hold after PSEN

PXIZ

input instruction float after PSEN

CLK

PXAV

PSEN to address valid

CLK

AVIV

address to valid instruction in

302

CLK

115 ns

PLAZ

PSEN LOW to address float

External Data Memory (Figs 42 and 43)

RLRH

RD pulse width

400

CLK

100

WLWH

WR pulse width

400

CLK

100

LLAX

address hold after ALE LOW

CLK

RLDV

RD LOW to valid data in

150

CLK

165 ns

RHDZ

data float after RD

CLK

LLDV

ALE LOW to valid data in

517

CLK

150 ns

AVDV

address to valid data in

585

CLK

165 ns

LLWL

ALE LOW to RD or WR LOW

200

300

CLK

+ 50

AVWL

address valid to RD or WR LOW

203

WHLH

RD or WR HIGH to ALE HIGH

123

CLK

+ 40

QVWX

data valid to WR transition

CLK

QVWH

data valid time WR HIGH

433

CLK

150

WHQX

data hold after WR

CLK

RLAZ

RD LOW to address float

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

Fig.44 Instruction cycle timing.

handbook, full pagewidth

MGD681

P1 P2

one machine cycle

XTAL1
INPUT

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

inst.

address A8 - A15

address

A0 - A7

inst.

address

A0 - A7

inst.

address

A0 - A7

data output or data input

address A8 - A15

address A8 - A15 or Port 2 output

address A8 - A15

old data

new data

sampling time of I/O port pins during input

SERIAL PORT
SHIFT CLOCK
(MODE 0)

PORT 0, 2, 3
INPUT

PORT 0, 2, 3
OUTPUT

PORT 2

BUS
(PORT 0)

read or

write of

external data

memory

PORT 2

BUS
(PORT 0)

external

program

memory

fetch

only active

during a write

to external

data memory

only active

during a read

from external
data memory

PSEN

ALE

dotted lines

are valid when

RD or WR are

active

old data

new data

PORT 1
OUTPUT

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

25 PACKAGE OUTLINES

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

0.3
0.1

3.0
2.8

0.25

0.42
0.30

0.22
0.14

21.65
21.35

11.1
11.0

0.75

15.8
15.2

1.45
1.30

0.90
0.55

7
0

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

1.6
1.4

SOT190-1

92-11-17
96-04-02

detail X

(A )

pin 1 index

0.012
0.004

0.12
0.11

0.017
0.012

0.0087
0.0055

0.85
0.84

0.44
0.43

0.03

2.25

0.089

0.62
0.60

0.057
0.051

0.035
0.022

0.004

0.2

0.008

0.004

0.063
0.055

0.01

10 mm

scale

VSO56: plastic very small outline package; 56 leads

SOT190-1

max.

3.3

0.13

Note

1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

26 SOLDERING

26.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

26.2

Reflow soldering

Reflow soldering techniques are suitable for all QFP and
VSO packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Manual" (order code 9398 510 63011).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

�

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

�

26.3

Wave soldering

26.3.1

QFP

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

�

The footprint must be at an angle of 45

�

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

26.3.2

VSO

Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

�

The longitudinal axis of the package footprint must be
parallel to the solder flow.

�

The package footprint must incorporate solder thieves at
the downstream end.

26.3.3

ETHOD

(QFP

AND

VSO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

26.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

1997 Mar 14

Philips Semiconductors

Product specification

Low voltage 8-bit microcontrollers with
UART, I

C-bus and ADC

P80CL580; P83CL580

27 DEFINITIONS

28 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

29 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1997

SCA53

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Printed in The Netherlands

457047/1200/04/pp80

Date of release: 1997 Mar 14

Document order number:

9397 750 01509

Электронный компонент: P80CL580HF

Document Outline