Document Outline

CONTENTS
1 FEATURES
- 1.1 P80C51 CPU core
- 1.2 P8xCx66 family
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING INFORMATION
- 5.1 Pinning
- 5.2 Pin description
6 MEMORY ORGANIZATION
- 6. Data memory
- 6.2 Special Function Registers
- 6.3 AUX RAM
- 6.4 Addressing
7 I/O FACILITY
- 7.1 I/O ports
- 7.2 Port configurations
8 TIMERS AND EVENT COUNTERS
- 8.1 16-bit timer/counters (T0 and T1)
- 8.2 Watchdog timer (T3)
9 REDUCED POWER MODE
- 9.1 Idle mode
- 9.2 Recover from Idle mode
- 9.3 General purpose flags (GF0 and GF1)
- 9.4 Output in Idle mode
- 9.5 Pending interrupts in Idle mode
- 9.6 Power Control Register (PCON)
10 I 2 C-BUS SERIAL I/O
- 10.1 The I 2 C-bus
- 10.2 Operation modes
- 10.3 Serial Control Register (S1CON)
- 10.4 Status Register (S1STA)
- 10.5 Data Shift Register (S1DAT)
- 10.6 Slave Address Register (S1ADR)
- 10.7 Internal Status Register (S1IST)
- 10.8 I 2 C-bus Control Register (I 2 CCON)
11 INTERRUPT SYSTEM
- 11.1 External interrupts INT2 to INT7 and INT9
- 11.2 Interrupt priority
- 11.3 Related registers
- 11.4 Interrupt Enable Register 0 (IEN0)
- 11.5 Interrupt Enable Register 1 (IEN1)
- 11.6 Interrupt Priority Register 0 (IP0)
- 11.7 Interrupt Priority Register 1 (IP1)
- 11.8 Interrupt Polarity Register (IX1)
- 11.9 Interrupt Request Flag Register (IRQ1)
- 11.10 VSYNC interrupt and level status bit
12 OSCILLATOR CIRCUITRY
- 12.1 RESET CIRCUITRY
- 12.2 Reset operation for the OSD SFRs
- 12.3 Power-on reset
13 RESET CIRCUITRY
- 13.1 Reset operation for the OSD SFRs
- 13.2 Power-on reset
14 PIN FUNCTION SELECTION
- 14.1 Port 1 pin function selection
- 14.2 Port 5 and P3.3 pin function selection
- 14.3 Port 3 pin function selection
15 ANALOG CONTROL
- 15.1 7-bit PWM outputs (PWM0 to PWM7)
- 15.2 14-bit PWM output (TPWM)
16 ANALOG-TO-DIGITAL CONVERTERS (ADC)
- 16.1 ADC Control Register 1 (SAD)
- 16.2 ADC Control Register 2 (SAD2)
17 ON-SCREEN DISPLAY (OSD)
- 17.1 Features
- 17.2 Flexible display format
- 17.3 OSD registers
- 17.4 OSD clock generator
- 17.5 Display RAM organization
- 17.6 Loading character data into display RAM
- 17.7 Writing character data into the display RAM
- 17.8 Character ROM
- 17.9 Character ROM organization
- 17.10 Combination of two or more font cells
- 17.11 More about North-West shadowing and Border shadowing sub-modes
- 17.12 Maximum number of characters per row
- 17.13 Maximum number of rows per frame
- 17.14 OSD vertical debouncing circuit
- 17.15 OSD meshing
- 17.16 FB to RGB delay compensation
18 EPROM PROGRAMMER
- 18.1 Interface to the on-chip EPROMs
- 18.2 EPROM Programming mode
- 18.3 Programming and verification
- 18.4 OSD EPROM bit map and the sequence of programming OSDL and OSDH
- 18.5 Summary of the Programming mode configuration
19 SPECIAL FUNCTION REGISTERS ADDRESS MAP
20 LIMITING VALUES
21 CHARACTERISTICS
- 21.1 DC parameters of EPROM
- 21.2 Programming specification for programmer
- 21.3 AC characteristics of Programming mode
22 PINNING CHARACTERIZATION
- 22.1 Type of packages
23 PACKAGE OUTLINES
- SOT188-2
- SOT270-1
24 SOLDERING
25 DEFINITIONS
26 LIFE SUPPORT APPLICATIONS
27 PURCHASE OF PHILIPS I 2 C COMPONENTS

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

FEATURES

1.1

P80C51 CPU core

80C51 8-bit CPU

64-kbyte Multiple Programming ROM (MTP ROM)

Two 16-bit timer/event counters

Crystal oscillator for system clock (up to 12 MHz)

12 source, 12 vector interrupt structure with two priority
levels

Enhanced architecture with:

Non-page orientated instructions

Direct addressing

Four 8-byte RAM register banks

Stack depth up to 128 bytes

Multiply, divide, subtract and compare instructions.

1.2

P8xCx66 family

ROM/RAM: see Table 1

Pulse Width Modulated (PWM) outputs:

One 14-bit PWM output for Voltage Synthesized

Tuning (VST)

Eight 7-bit PWM outputs for analog controls.

3 Analog-to-Digital (ADC) inputs with 4-bit DAC and
comparator

LED driver port:

All I/O port lines with 10 mA LED drive capability

<1.0 V)

Up to 5 LEDs can be driven at any one time.

Serial I/O:

Multi-master I

C-bus interface

Maximum I

C-bus frequency 400 kHz.

Watchdog timer

Improved EMC measures and slope controlled I/Os

OSD functions:

Programmable VSYNC and HSYNC active levels

Display RAM: 192

12 bits

Display character fonts: 128 (126 customer fonts plus

2 reserved codes)

63 vertical starting positions controlled by software

110 horizontal starting positions controlled by

software

Character size: 4 different character sizes on a

line-by-line basis

Character matrix: 12

18 with no spacing between

characters

Foreground colours: 8 on a character-by-character

basis

Background/shadowing modes: two primary modes -

TV mode and Frame mode on a frame basis. Each
primary mode has four sub-modes on a line basis:
Sub-mode 1: Superimpose (no background)
Sub-mode 2: North-West shadowing
Sub-mode 3: Box background
Sub-mode 4: Border shadowing

Background colours: 8 on a word-by-word basis,

available in all four sub-modes

Display RAM starting address is programmable; fast

switching between banks of display (RAM)
characters is possible through software control

HSYNC driven PLL for OSD clock (4 to 12 MHz)

Character blinking ratio: 1 : 1

Character blinking frequency: programmable using

VSYNC

divisors of 32 and 64, on a character basis

Flexible display format using the Carriage Return

code and the Space codes

Display RAM address post incremented each time

new data is written into RAM

Vertical jitter cancelling circuit to avoid unstable

VSYNC leading edge mismatch with HSYNC signal

OSD meshing.

Power-on reset

Packages: SDIL42 (PLCC68 for piggy-back only)

Operating voltage: 4.5 to 5.5 V

Operating temperature:

20 to +70

System clock frequency: 4 to 12 MHz

OSD clock frequency: 4 to 12 MHz.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

GENERAL DESCRIPTION

The P8xCx66 family consists of the following devices:

P83C266

P83C366

P83C566

P83C766

P87C766.

The P8xCx66 family are 80C51-based microcontrollers
designed for medium-high to high-end TV control
applications. The P8xCx66 devices incorporate many
unique features on-chip, giving them a competitive edge
over similar devices from other manufacturers.

The Philips 80C51 CPU is object code compatible with the
industry standard 80C51. All devices are manufactured in
an advanced CMOS technology.

The P8xCx66 family also function as arithmetic processors
having facilities for both binary and BCD arithmetic plus bit
handling capabilities. The instruction set consists of over
100 instructions: 49 one-byte, 46 two-byte and
16 three-byte. Multiply and divide instructions are
implemented by hardware with a cycle time of 4

CLK

= 12 MHz).

The term P8xCx66 is used throughout this data sheet to
refer to all family members; differences between devices
are highlighted in the text.

Table 1

Memory structure for the different family members

ORDERING INFORMATION

MEMORY

P83C266

P83C366

P83C566

P83C766

P87C766

ROM

24 kbytes

32 kbytes

48 kbytes

64 kbytes

RAM

512 bytes

1 kbyte

2 kbytes

EPROM

64 kbytes

Main memory

256 bytes

Auxiliary RAM

256 bytes

768 bytes

1792 bytes

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

P83C266BDR

SDIP42

plastic shrink dual in-line package; 42 leads (600 mil)

SOT270-1

P83C366BDR

P83C366CBP

P83C566BDR

P83C766BDP

P87C766BDR

P87C766CBP

P83C366BDA

PLCC68

plastic leaded chip carrier; 68 leads

SOT188-2

P83C566BDA

P83C766BDA

P87C766CBA

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

BLOCK DIAGRAM

ok, full pagewidth

MGL302

8-bit internal bus

8-BIT

WATCHDOG

TIMER

(T3)

ROM

32 KBYTES

(1)

EPROM

64 KBYTES

(2)

RAM

512 BYTES

(1)

2 KBYTES

(2)

7-BIT

DACS

4-BIT

ADCS

14-BIT DAC

ON SCREEN DISPLAY

(OSD)

PLL

internal

interrupts

external

interrupts

PWM0 to PWM7

(4)

VPP

RESET

C-BUS

INTERFACE

ADC1

(5)

ADC2

(5)

ADC0

(5)

SDA

(3)

SCL

(3)

TWO 16-BIT

TIMER/

COUNTERS
(T0 AND T1)

(3)

VSSD

VDDD

FUNCTION

COMBINED

PARALLEL
I/O PORTS

PARALLEL

I/O PORT

CPU

80C51 CORE

EXCLUDING

ROM/RAM

XTALIN

XTALOUT

TPWM

(4)

HSYNC

P8xCx66

VSYNC

VDDA

VSSA

Fig.1 P83C366 and P87C766 block diagram.

(1) For the P83C366.

(2) For the P87C766.

(3) Alternative functions of Port 1.

(4) Alternative functions of Port 5, except PWM7 which is an alternative function of Port 3.

(5) Alternative functions of Port 3.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

5.2

Pin description

Table 2

Pin description for SDIP42 and PLCC68 packages

SYMBOL

PIN

I/O

DESCRIPTION

SDIP42

PLCC68

P5.0/TPWM

I/O

Port 5: 8-bit open-drain, bidirectional port.(P5.0 to P5.7) with 8 alternative
functions.
TWPM: 14-bit PWM output.
PWM0 to PWM6: 7-bit PWM outputs.

P5.1/PWM0

P5.2/PWM1

P5.3/PWM2

P5.4/PWM3

P5.5/PWM4

P5.6/PWM5

P5.7/PWM6

P3.0/ADC0

I/O

Port 3: 4-bit open-drain, bidirectional port.(P3.0 to P3.3) with 4 alternative
functions.
ADC0 to ADC2: ADC inputs.
PWM7: 7-bit PWM output.

P3.1/ADC1

P3.2/ADC2

P3.3/PWM7

P0.0 to P0.7

13 to 20

23 to 25,
28 to 32

I/O

Port 0: 8-bit open-drain, bidirectional port (P0.0 to P0.7).

SSD

Ground line for digital circuits.

OSD blue colour output.

OSD green colour output.

OSD red colour output.

OSD fast blanking output.

HSYNC

TV horizontal sync Schmitt trigger input (for OSD synchronization).

VSYNC

TV vertical sync Schmitt trigger input (for OSD synchronization).

DDA

5 V analog power supply.

SSA

Ground line for analog circuits.

+12.75 V programming voltage supply (OTP) for EPROM only. 0 V in
normal application. For the ROM version this pin is not connected.

XTALIN

Crystal input.

XTALOUT

Crystal output.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

RESET

Reset input.

P1.0

I/O

Port 1: 8-bit open-drain, bidirectional port (P1.0 to P1.7) with 6 alternative
functions.
INT1 and INT0: external interrupts 1 and 0.
T1 and T0: 16-bit timer/counter 1 and 0 inputs
SCL: I

C-bus clock line

SDA: I

C-bus data line

P1.1/INT1

P1.2/T0

P1.3/INT0

P1.4/T1

P1.5/SCL

P1.6/SDA

P1.7

DDD

5 V digital power supply.

1, 49, 56

Ground lines.

n.c.

9, 10, 27,

43, 44,

60, 61

not connected

INTD

These 3 signals are used for metalink+ emulation.

PH1SEM

I/O

S1ESEM

I/O

P2.0

I/O

Port 2: 8-bit open-drain, bidirectional port (P2.0 to P2.7).

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

OSD_EPR_
TST

I/O

OSD EPROM test enable.

IDLPDEM

I/O

These 2 signals are used for metalink+ emulation.

EMUPBX

I/O

SSD1

Ground line for digital circuits.

DDD1

5 V digital power supply.

SYMBOL

PIN

I/O

DESCRIPTION

SDIP42

PLCC68

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

MEMORY ORGANIZATION

The P8xCx66 family provides 24, 32, 48 or 64 kbytes of
program memory (ROM/EPROM) plus 512, 1024 or
2048 bytes of data memory (RAM) on-chip (see Table 1).
The device has separate address spaces for program and
data memory (see Fig.4). These devices have no external
memory access capability as the RD (read), WR (write),
EA (External Access), PSEN (read strobe) and ALE
(Address Latch Enable) signals are not bonded out.

6.1

Data memory

The P8xCx66 family contains 512, 1024 or 2048 bytes of
internal RAM and 56 Special Function Registers (SFRs).
Figure 4 shows the internal data memory space divided
into the lower 128, the upper 128, AUX-RAM and the SFR
space. The lower 128 bytes of internal RAM are organized
as shown in Fig.5. The lowest 32 bytes are grouped into
4 banks of 8 registers. Program instructions refer to these
registers as R0 to R7. Two bits in the Program Status
Word (PSW) select which register bank is in use. The next
16 bytes above the register bank form a block of
bit-addressable memory space. The 128 bits in this area
can be directly addressed by the single-bit manipulation
instructions. The remaining registers (30H to 7FH) are
directly and indirectly byte addressable. The registers that
reside at addresses above 7FH and up to FFH can only be
accessed indirectly. These register addresses overlap the
SFR addresses as described in Section 6.2.

6.2

Special Function Registers

The upper 128 bytes are the address locations of the
SFRs when accessed directly. SFRs include the port
latches, timers, 7-bit PWMs, 14-bit VST PWM, ADCs and
OSD control registers. These registers can only be
accessed by direct addressing. There are
128 bit-addressable locations in the SFR address space
(SFRs with addresses divisible by eight). Their addresses
are a multiple of 08H, from 80H to F8H. (i.e., 80H, 88H,
90H, 98H etc.). See Chapter 19 for SFR list.

6.3

AUX RAM

The 1792 byte (P87C766) or 768 byte (P83C766)
AUX RAM, while physically located on-chip, logically
occupies the first 1792/768 bytes of external data memory.
As such, it is indirectly addressed in the same way as
external data memory using MOVX instructions in
combination with any of the registers R0, R1 or DPTR.

6.4

Addressing

The P80C51 CPU has five methods for addressing source
operands

Direct

Immediate

Base-register-plus index-register-indirect.

The first three methods can be used for addressing
destination operands. Most instructions have a
`destination/source' field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.

Access to memory addressing is as follows:

Registers in one of the four register banks through
register direct or indirect

Internal RAM (128 bytes) through direct or
register-indirect

Special Function Registers through direct

External data memory through register-indirect
(for AUX RAM)

Program memory look-up tables through
base-register-plus index-register-indirect.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

I/O FACILITY

7.1

I/O ports

The SDIP42 package has 28 I/O lines treated as
28 individual addressable bits or as 3 parallel 8-bit
addressable ports (Ports 0, 1 and 5) and one 4-bit port
(Port 3).

When these 28 I/O lines are used as input ports, the
corresponding bits in SFRs P0, P1, P3 and P5 should be
set to a logic 1 to facilitate the external input signal.

Ports 1, 3 and 5 also perform the following alternative
functions.

Port 1. Used for a number of special functions:

Provides the external interrupt inputs (INT0 and INT1)

Provides the 16-bit timer/counter inputs (T0 and T1)

Provides the I

C-bus data and clock signals (SDA and

SCL)

P1.0 and P1.7 can be used as external interrupt inputs.

Port 3. Only 4 lines available for alternative functions:

7-bit PWM output (PWM7)

ADC inputs ADC0 to ADC2.

Port 5.

Provides the 14-bit PWM output (TPWM)

7-bit PWMs outputs (PWM0 to PWM6).

To enable the alternative functions of Ports 1, 3 and 5, the
port bit latch of its associated SFR must contain a logic 1.

Each port consists of a latch (SFRs P0, P1, P3 and P5), an
output driver and an input buffer.

7.2

Port configurations

1. Open-drain quasi-bidirectional I/O with n-channel

pull-down (see Fig.6). Use as an output requires the
connection of an external pull-up resistor. Use as an
input requires to write a logic 1 to the port latch before
reading the port line.

2. Push-pull; gives drive capability of the output in both

polarities, see Fig.7.

Fig.6 Open-drain port.

handbook, halfpage

MGK547

from port latch

input data

read port pin

INPUT

BUFFER

I/O pin

Fig.7 Push-pull port.

handbook, halfpage

MGM679

strong pull-up

5 V

from port latch

output pin

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

TIMERS AND EVENT COUNTERS

The P8xCx66 contains two 16-bit timers/counters: Timer 0
and Timer 1 and also an 8-bit Watchdog timer.

8.1

16-bit timer/counters (T0 and T1)

Timer 0 and Timer 1 perform the following functions:

Measure time intervals and pulse durations

Count events

Generate interrupt requests.

Timer 0 and Timer 1 can be independently programmed to
operate in one of four modes.

Mode 0 8-bit timer or counter with divide-by-32 prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TL1 as two

separate counters.

In the `timer' function, the register is incremented every
machine cycle. Since a machine cycle consists of
12 oscillator periods, the count rate is

osc

In the `counter' function, the register is incremented in
response to a HIGH-to-LOW transition. Since it takes
2 machine cycles (24 oscillator periods) to recognize a
HIGH-to-LOW transition, the maximum count rate is

osc

. To ensure that a given level is sampled, it should

be held for at least one complete machine cycle.

8.2

Watchdog timer (T3)

In addition to the standard timers, a Watchdog timer is
implemented on-chip. The Watchdog timer generates a
hardware reset upon overflow. In this way a
microcontroller system can recover from erroneous
processor states caused by electrical noise, RFI or
unexpected ROM code behaviour.

The Watchdog timer consists of an 8-bit timer with an
11-bit prescaler as shown in Fig.8. The prescaler input

frequency is

osc

. The 8-bit timer is incremented every

`t' seconds where `t' is calculated as shown below:

The 8-bit timer is an up-counter so a value 00H gives the
maximum timer interval (510 ms at 12 MHz, 1536 ms at
4 MHz), and a value of FFH gives the minimum timer
interval (2 ms at 12 MHz, 6 ms at 4 MHz). When the 8-bit
timer produces an overflow a short internal reset pulse is
generated which will reset the P8xCx66.

The timer has no disable function. Consequently, all
applications must reload the timer within the previously
loaded timer interval otherwise a reset will occur. The timer
is not stopped in the Idle mode. The interrupt routine for
the Idle mode should also service the Watchdog timer.

The Watchdog timer is controlled by the WLE bit in the
Power Control Register (see Section 9.6). The WLE bit
must be set by the Watchdog timer service routine before
the timer interval can be loaded into T3. A load of T3
automatically clears the WLE bit.

A system reset clears the Watchdog timer and the
prescaler.

8.2.1

ATCHDOG TIMER

EGISTER

(WDT)

Table 3

Watchdog timer Register (SFR address FFH)

T37

T36

T35

T34

T33

T32

T31

T30

2048

osc

--------

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

REDUCED POWER MODE

Only one reduced power mode is implemented; this is the
Idle mode.

During Idle mode all blocks are inactive except Timer 0,
Timer 1, INT0, INT1 and the Watchdog timer. These active
functions may generate an interrupt (if their interrupts are
enabled) and this will cause the device to leave the Idle
mode.

The Idle mode is activated by software using the PCON
register; this register is described in Section 9.6.

9.1

Idle mode

The instruction that sets PCON.0 is the last instruction
executed before entering the Idle mode. Once in the Idle
mode, the internal clock is gated away from the CPU and
from all derivative functions (PWM/TPWM/ADC/I

C-bus),

except Timer 0, Timer 1 and interrupts INT0 and INT1.
The Watchdog timer remains active. The CPU status is
preserved along with the Stack Pointer, Program Counter,
Program Status Word and the Accumulator. The RAM and
all other registers maintain their data during Idle mode and
the port pins retain the logic states held at Idle mode
activation. The OSD clock is gated away from OSD circuit
in Idle mode.

9.2

Recover from Idle mode

There are 3 methods used to terminate the Idle mode.

9.2.1

IA AN

NTERRUPT

Activation of INT0, INT1 or an interrupt from Timer 0 or
Timer 1 will cause PCON to be cleared by hardware thus
terminating the Idle mode. The interrupt is serviced and
following the RETI instruction, the next instruction to be
executed will be the one following the instruction that put
the device in the Idle mode. All the other interrupts are
disabled and will not generate an interrupt to wake-up the
CPU.

9.2.2

ESET

The second method of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for only
two machine cycles to complete the reset operation. Reset
redefines all SFRs, but does not effect the on-chip RAM.

9.2.3

IA A

ATCHDOG TIMER OVERFLOW

If the Watchdog timer is allowed to overflow or an
erroneous processor state causes an overflow, a
hardware reset will be generated, thus terminating the Idle
mode.

9.3

General purpose flags (GF0 and GF1)

Flags GF0 and GF1 may be used to determine whether
the interrupt was received during normal execution or Idle
mode. For example, the instruction that writes to PCON.0
to set the Idle mode can also set or clear one or both flags.
When the Idle mode is terminated by an interrupt, the
service routine can examine the status of the flag bits.

9.4

Output in Idle mode

Ports will keep the value they had before entering the
Idle mode

The PWM0 to PWM7 outputs will be LOW

The TPWM output will be LOW

The I

C-bus output is HIGH

The pins R, G, B and FB will be the `inverse of Bp',
(defined by bit 2 of SFR OSCON).

9.5

Pending interrupts in Idle mode

If pending interrupts (I

C-bus, VSYNC, P1.0 to P1.4 or

P1.7) are present at the moment the CPU is switched to
Idle mode, then these interrupts will wake-up the CPU.
If this is not wanted then before entering the Idle mode all
interrupts must be disabled, except those interrupts
allowed to wake-up the CPU (INT0, INT1, Timer 0 and
Timer1). New interrupts from I

C-bus, VSYNC,

P1.0 to P1.4 or P1.7 are disabled as soon as Idle mode is
entered.

For example if a high priority interrupt is serviced just
before the instruction which sets PCON.0 and a lower
priority interrupt is generated during the interrupt service
routine of the high priority interrupt, then the lower priority
interrupt is pending. After the high priority interrupt is
serviced (last instruction of routine is RETI) the main
program will execute at least one more instruction to
prevent a deadlock of the main program. In this case, it is
the instruction which sets the PCON.0 bit (enter Idle
mode). The pending lower level interrupt will, if enabled,
immediately wake-up the CPU for an interrupt service,
even though this interrupt is not INT0, INT1 or an interrupt
from Timer 1 or Timer 0.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

10 I

C-BUS SERIAL I/O

10.1

The I

C-bus

The serial port supports the two line I

C-bus. The I

C-bus

consists of a serial data line (SDA) and a serial clock line
(SCL). These lines can also function as I/O port lines
P1.6 and P1.5 respectively. To utilize this facility pins
P1.5/SCL and P1.6/SDA must be configured as alternative
functions instead of port lines; see Section 10.8.

The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.

Full details of the I

C-bus are given in the document

"The I

C-bus and how to use it". This document may be

ordered using the code 9398 393 40011.

10.2

Operation modes

The I

C-bus serial I/O has complete autonomy in byte

handling and operates in four modes

Master transmitter

Master receiver

Slave transmitter

Slave receiver.

These functions are controlled by the S1CON register.
S1STA is the status register whose contents may also be
used as a vector to various service routines. S1DAT is the
data shift register and S1ADR the slave address register.
Slave address recognition is performed by hardware.

Fig.9 Block diagram of I

C-bus serial I/O.

handbook, full pagewidth

MBC749 - 1

SLAVE ADDRESS

S1ADR

SHIFT REGISTER

S1DAT

SDA

ARBITRATION LOGIC

SCL

BUS CLOCK GENERATOR

S1STA

INTERNAL BUS

S1CON

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

10.3

Serial Control Register (S1CON)

Table 6

Serial Control Register (SFR address D8H)

Table 7

Description of S1CON bits

CR2

ENS1

STA

STO

CR1

CR0

BIT

SYMBOL

DESCRIPTION

ENSI

Enable Serial I/O. When ENSI = 0, the SIO is disabled and reset. The SDA and SCL
outputs are in a high-impedance state; P1.5 and P1.6 function as open-drain ports.
When ENSI = 1, the SIO is enabled. The P1.5 and P1.6 port latches must be set to
logic 1.

STA

START flag. When the STA bit is set in Slave mode, the SIO hardware checks the
status of the I

C-bus and generates a START condition if the bus is free. If STA is set

while the SIO is in Master mode, SIO transmits a repeated START condition.

STO

STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the
Slave mode, the STO flag may also be set to recover from an error condition. In this
case, no STOP condition is transmitted to the I

C-bus interface. However, the SIO

hardware behaves as if a STOP condition has been received and releases SDA and
SCL. The SIO then switches to the `not addressed' slave receiver mode. The STO flag
is automatically cleared by hardware.

SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of
the following conditions:

A START condition is generated in Master mode

Own slave address received during AA = 1

General call address received while S1ADR.0 = 1 and AA = 1

Data byte received or transmitted in Master mode (even if arbitration is lost)

Data byte received or transmitted as selected slave

STOP or START condition received as selected slave receiver or transmitter.

Assert Acknowledge. When the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line when:

Own slave address is received

General call address is received (S1ADR.0 = 1)

Data byte received while device is programmed as a Master receiver

Data byte received while device is a selected Slave receiver.

With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested
when the `own slave address' or general call address is received.

CR2

Clock Rate selection. These three bits determine the serial clock frequency when SIO
is in a Master mode; see Table 8. The maximum I

C-bus frequency is 400 KHz.

CR1

CR0

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

Table 8

Selection of SCL frequency in Master mode

10.4

Status Register (S1STA)

S1STA is an 8-bit read-only Special Function Register. The contents of S1STA may be used as a vector to a service
routine. This optimizes response time of the software and consequently that of the I

C-bus. The status codes for all

possible modes of the I

C-bus interface are given in Table 12. The abbreviations used in Table 12 are defined in

Table 11.

Table 9

Status Register (SFR address D9H)

Table 10 Description of S1STA bits

Table 11 Abbreviations used in Table 12

CR2

CR1

CR0

osc

DIVISOR

BIT RATE (kHz) at f

osc

= 12 MHz

200

1600

7.5

300

400

240

3200

3.75

160

120

100

SC4

SC3

SC2

SC1

SC0

BIT

SYMBOL

DESCRIPTION

7 to 3

SC4 to SC0

5-bit status code; see Table 12.

2 to 0

These 3 bits are held LOW.

SYMBOL

DESCRIPTION

SLA

7-bit slave address

read bit

write bit

ACK

acknowledgment (Acknowledge bit = 0)

ACK

not acknowledge (Acknowledge bit = 1)

DATA

8-bit byte to or from the I

C-bus

MST

master

SLV

slave

TRX

transmitter

REC

receiver

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

Table 12 Status codes

S1STA VALUE

DESCRIPTION

MST/TRX mode

08H

a START condition has been transmitted

10H

a repeated START condition has been transmitted

18H

SLA and W have been transmitted, ACK received

20H

SLA and W have been transmitted. ACK received

28H

DATA of S1DAT has been transmitted, ACK received

30H

DATA of S1DAT has been transmitted, ACK received

38H

arbitration lost in SLA, R/W or DATA

MST/REC mode

38H

arbitration lost while returning ACK

40H

SLA and R have been transmitted, ACK received

48H

SLA and R have been transmitted, ACK received

50H

DATA has been received, ACK returned

58H

DATA has been received, ACK returned

SLV/REC mode

60H

own SLA and W have been received, ACK returned

68H

arbitration lost in SLA, R/W as MST; own SLA and W have been received, ACK
returned

70H

general CALL has been received, ACK returned

78H

arbitration lost in SLA, R/W as MST; general CALL has been received

80H

previously addressed with own SLA; DATA byte received, ACK returned

88H

previously addressed with own SLA; DATA byte received, ACK returned

90H

previously addressed with general CALL; DATA byte has been received, ACK returned

98H

previously addressed with general CALL; DATA byte has been received, ACK returned

A0H

a STOP condition or repeated START condition has been received while still addressed
as SLV/REC or SLV/TRX

SLV/TRX mode

A8H

own SLA and R have been received. ACK returned

B0H

arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK
returned

B8H

DATA byte has been transmitted, ACK received

C0H

DATA byte has been transmitted, ACK received

C8H

last DATA byte has been transmitted (AA = logic 0) ACK received

Miscellaneous

00H

bus error during MST mode or SLV mode, due to an erroneous START or STOP
condition

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

10.5

Data Shift Register (S1DAT)

S1DAT contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first.

Table 13 Data Shift Register (SFR address DAH)

10.6

Slave Address Register (S1ADR)

This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized.

Table 14 Slave Address Register (SFR address DBH)

Table 15 Description of S1ADR bits

10.7

Internal Status Register (S1IST)

S1IST is an 8-bit read-only Special Function Register and will exist in the design but is not mapped for the user.

Table 16 Internal Status Register (SFR address DCH)

10.8

C-bus Control Register (I

CCON)

Table 17 I

C-bus Control Register (SFR address 86H)

Table 18 Description of I

CCON bits

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

BIT

SYMBOL

DESCRIPTION

7 to 1

SLA6 to
SLA0

Own slave address.

When GC = 0, the general CALL address is not recognized. When GC = 1, the general
CALL address is recognized.

MST

TRX

ARL

SEL

AD0

SHRA

BIT

SYMBOL

DESCRIPTION

7 to 3

These 5 bits are not used.

C-bus enable. This bit selects the functions of pins 39 and 40 for the SDIP42 package

(or pins 64 and 65 for the PLCC68 package). When I

CE = 1, the alternative functions

SCL and SDA are selected. When I

CE = 0, these pins act as port lines P1.5 and P1.6.

1 to 0

These bits are not used.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11 INTERRUPT SYSTEM

External events and the real-time driven on-chip
peripherals require service by the CPU asynchronous to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The P8xCx66
acknowledges interrupt requests from twelve sources as
shown in Table 20.

Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by using corresponding
bits in the Interrupt Enable Registers (IEN0 and IEN1).
The priority level is selected via the Interrupt Priority
Registers (IP0 and IP1). All enabled sources can be
globally disabled or enabled. The minimum width of the
external interrupt signal is

6 XTAL clocks. The maximum

width of the interrupt signal is the total length of all
instructions in the interrupt service routine until the clear
instruction of the IRQ bit. The external interrupts are INT0,
INT1, P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7.

11.1

External interrupts INT2 to INT7 and INT9

Port 1 lines also serve as additional interrupts
INT2 to INT7 (P1.0, P1.1, P1.2, P1.3, P1.4 and P1.7).
INT7 is used by the derivative functional blocks as follows:

X7 VSYNC interrupt 0063H

Using the IX1 register, each pin may be initialized to be
either active HIGH or active LOW except INT7 which is
fixed active HIGH because this interrupt is from another
derivative function. IRQ1 is the Interrupt Request Flag

Register. Each flag will be set on interrupt request but it
must be cleared by software, i.e. via the interrupt software.

11.2

Interrupt priority

Each interrupt source can be set to either high or low
priority. If both priorities are requested simultaneously, the
controller will branch to the high priority vector.

A low priority interrupt can only be interrupted by a high
priority interrupt. A high priority interrupt routine cannot be
interrupted

11.3

Related registers

The following registers are used in conjunction with the
interrupt system.

Table 19 Interrupt registers

REGISTER

ADDRESS

Interrupt Polarity Register (IX1)

E9H

Interrupt Request Flag Register (IRQ1)

C0H

Interrupt Enable Register 0 (IEN0)

A8H

Interrupt Enable Register 1 (IEN1);
interrupts INT2 to INT9

E8H

Interrupt Priority Register 0 (IP0)

B8H

Interrupt Priority Register 1 (IP1);
interrupts INT2 to INT9

F8H

Table 20 Interrupt request (priority within level)

INTERRUPT MNEMONIC

SOURCE

VECTOR ADDRESS

PX0 (highest)

external interrupt 0 (INT0)

0003H

C-bus

002BH

Timer 0 overflow

000BH

PX2

P1.0 port line

0033H

PX6

P1.4 port line

005BH

PX1

external interrupt 1 (INT1)

0013H

PX3

P1.1 port line

003BH

PX7

VSYNC interrupt

0063H

Timer 1 overflow

001BH

PX4

P1.2 port line

0043H

PX5

P1.3 port line

004BH

PX9 (lowest)

P1.7 port line

0073H

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11.4

Interrupt Enable Register 0 (IEN0)

Table 21 Interrupt Enable Register (SFR address A8H)

Table 22 Description of IEN0 bits

A logic 0 disables the interrupt; a logic 1 enables the interrupt.

11.5

Interrupt Enable Register 1 (IEN1)

Table 23 Interrupt Enable Register (SFR address E8H)

Table 24 Description of IEN1 bits

Where EXx = 0, interrupt disabled. EXx = 1, interrupt enabled

ES1

ET1

EX1

ET0

EX0

BIT

SYMBOL

DESCRIPTION

General enable/disable control. When EA = 0, no interrupt is enabled. When EA = 1,
any individually enabled interrupt will be accepted.

not used

ES1

enable I

C-bus SIO interrupt

not used

ET1

enable Timer 1 interrupt

EX1

enable external interrupt 1

ET0

enable Timer 0 interrupt

EX0

enable external interrupt 0

EX9

EX7

EX6

EX5

EX4

EX3

EX2

BIT

SYMBOL

DESCRIPTION

EX9

enable external interrupt 9 (P1.7 port line)

not used

EX7

enable external interrupt 7 (VSYNC interrupt)

EX6

enable external interrupt 6 (P1.4 port line)

EX5

enable external interrupt 5 (P1.3 port line)

EX4

enable external interrupt 4 (P1.2 port line)

EX3

enable external interrupt 3 (P1.1 port line)

EX2

enable external interrupt 2 (P1.0 port line)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11.6

Interrupt Priority Register 0 (IP0)

Table 25 Interrupt Priority Register 0 (SFR address B8H)

Table 26 Description of IP0 bits

A logic 0 selects low priority; a logic 1 selects high priority.

11.7

Interrupt Priority Register 1 (IP1)

Table 27 Interrupt Priority Register 1 (SFR address F8H)

Table 28 Description of IP1 bits

Where PXx = 0 selects low priority; PXx = 1 selects high priority.

PS1

PT1

PX1

PT0

PX0

BIT

SYMBOL

DESCRIPTION

These 2 bits are not used.

PS1

C-bus SIO interrupt priority level

This bit is not used.

PT1

Timer 1 interrupt priority level

PX1

external interrupt 1 priority level

PT0

Timer 0 interrupt priority level

PX0

external interrupt 0 priority level

PX9

PX7

PX6

PX5

PX4

PX3

PX2

BIT

SYMBOL

DESCRIPTION

PX9

enable external interrupt 9 priority level (P1.7 port line)

not used

PX7

enable external interrupt 7 priority level (VSYNC interrupt)

PX6

enable external interrupt 6 priority level (P1.4 port line)

PX5

enable external interrupt 5 priority level (P1.3 port line)

PX4

enable external interrupt 4 priority level (P1.2 port line)

PX3

enable external interrupt 3 priority level (P1.1 port line)

PX2

enable external interrupt 2 priority level (P1.0 port line)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11.8

Interrupt Polarity Register (IX1)

Writing a logic 1 to bits IL9, IL6, IL5, IL4, IL3 and IL2 will set the polarity level of the corresponding external interrupt to
be active HIGH. Writing a logic 0 to these bits will set the corresponding external interrupt to be active LOW.

External interrupts INT1 and INT0 however can be programmed to be edge sensitive. Writing a logic 1 to bits IL8 and IL7
will activate the external interrupts INT1 and INT0 on a rising edge (LOW-to-HIGH). Writing a logic 0 to bits IL8 and IL7
will activate the external interrupts INT1 and INT0 on a falling edge (HIGH-to-LOW). This feature is useful for pulse width
measurement; see Section 11.8.1.

Table 29 Interrupt Polarity Register (SFR address E9H)

Table 30 Description of IX1 bits

11.8.1

ULSE WIDTH MEASUREMENT EXAMPLE

To determine the LOW time of a signal on the external interrupt pin INT0 the following sequence should be followed.

1. External interrupt 0 must be programmed to edge sensitivity (SFR TCON, address 88H).

2. IL7 must be programmed as shown in Fig.12.

3. The value held in Timer 0 or Timer 1 represents the pulse width of the signal on the INT0 pin.

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

BIT

SYMBOL

DESCRIPTION

IL9

external interrupt 9 polarity level (P1.7 port line)

IL8

external interrupt 1 polarity level (INT1) polarity level

IL7

external interrupt 0 polarity level (INT0) polarity level

IL6

external interrupt 6 polarity level (P1.4 port line)

IL5

external interrupt 5 polarity level (P1.3 port line)

IL4

external interrupt 4 polarity level (P1.2 port line)

IL3

external interrupt 3 polarity level (P1.1 port line)

IL2

external interrupt 2 polarity level (P1.0 port line)

Fig.12 Pulse width measurement timing diagram.

handbook, full pagewidth

INT0

IL7

INT0(CPU)

Start interrupt service
routine to start counting
system clock periods
with Timer 0 or Timer 1

Start interrupt service
routine to stop counting
of Timer 0 or Timer 1

MGL295

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11.9

Interrupt Request Flag Register (IRQ1)

Bits IQ9 and IQ6 to IQ2 will be set to a logic 1, if one of the two conditions specified below is met:

If its associated port line is programmed to generate an interrupt when HIGH (selected using the Interrupt Polarity
Register) and the state of that port line is HIGH

If its associated port line is programmed to generate an interrupt when LOW (selected using the Interrupt Polarity
Register) and the state of that port line is LOW.

IQ7 is set to a logic 1, if the interrupt condition is met within the corresponding derivative function. Therefore, all IRQ1 bits
serve not only as pending interrupt request bits but also as interrupt status bits. This means that even if the external
interrupts are disabled (using the Interrupt Enable Register 1) the IRQ1 bits can still be set to a logic 1 if the interrupt
condition is met within the corresponding derivative function. For example, if the interrupt condition within VSYNC is met
then:

If IEN0.7 = X, IEN1.5 = 0 then IRQ1.5 = 1, no pending interrupt to CPU

If IEN0.7 = 0, IEN1.5 = 1 then IRQ1.5 = 1, interrupt to CPU is pending

If IEN0.7 = 1, IEN1.5 = 1 then IRQ1.5 = 1, interrupt will be serviced when either:

The CPU finishes current instruction, if not in the interrupt service routine

The current interrupt service routine is interrupted if the VSYNC has a higher interrupt priority

This VSYNC interrupt becomes pending, waiting until the current higher priority level interrupt is serviced.

Bits IQ9 and IQ7 to IQ2 can be reset by software.

Table 31 Interrupt Request Flag Register (SFR address C0H)

Table 32 Description of IRQ1 bits

IQ9

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

BIT

SYMBOL

DESCRIPTION

IQ9

external interrupt 9 request flag (P1.7 port line)

reserved

IQ7

external interrupt 7 request flag (VSYNC interrupt)

IQ6

external interrupt 6 request flag (P1.4 port line)

IQ5

external interrupt 5 request flag (P1.3 port line)

IQ4

external interrupt 4 request flag (P1.2 port line)

IQ3

external interrupt 3 request flag (P1.1 port line)

IQ2

external interrupt 2 request flag (P1.0 port line)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

11.10 VSYNC interrupt and level status bit

The SFR VINT is read-only. Figure 13 shows the timing diagram of VSYNC interrupt.

Table 33 VSYNC Interrupt Register (SFR address C9H)

Table 34 Description of VINT bits

11.10.1 E

XTERNAL INTERRUPT REQUEST

(IQ7)

A rising or falling edge (see Fig.13) of the active VSYNC signal generates a pending interrupt to the CPU and drives IQ7
HIGH (IQ7 resides in the SFR IRQ1). In the service routine, this bit should be cleared before return to main routine.
As long as this bit is HIGH a pending interrupt is always there. Each time VSYNC is activated by a rising or falling edge,
IQ7 is set HIGH. If the interrupt is not serviced before the next leading VSYNC edge, then IQ7 is written HIGH again and
no error of overrun is indicated.

VLVL

BIT

SYMBOL

DESCRIPTION

7 to 1

These 7 bits are not used.

VLVL

VSYNC input pin level. The state of this bit indicates the level of the VSYNC input. As
the input polarity of VSYNC is programmable two situations may be defined.

If VSYNC is programmed active HIGH then:

VLVL = 0, means VSYNC is at a LOW level, i.e. raster scan period

VLVL = 1, means VSYNC is at HIGH level, i.e.vertical fly-back period.

If VSYNC is programmed to active LOW then:

VLVL = 0, means VSYNC is at LOW level, i.e. vertical fly-back period

VLVL = 1, means VSYNC is at HIGH level, i.e. raster scan period

Fig.13 Timing diagram of VSYNC interrupt.

handbook, full pagewidth

VSYNC

VSYNC active LOW (Vp = 0)

VSYNC active HIGH (Vp = 1)

MGL286

The falling edge of VSYNC generates interrupt

The rising edge of VSYNC generates an interrupt

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

13 RESET CIRCUITRY

To initialize the P8xCx66 a reset is performed by one of
3 methods:

Via the RESET pin

Via a Power-on reset

Via the Watchdog timer.

A reset leaves the internal registers as shown in Table 35.

The reset input of the P8xCx66 is the RESET pin. A
Schmitt trigger input qualifies the input for noise rejection.
The output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle. A reset is accomplished by
holding the RESET pin HIGH for at least two machine
cycles (24 oscillator periods), while the oscillator is
running. The CPU responds by generating an internal
reset. Port pins adopt their reset state immediately after
RESET goes HIGH.

The external reset is asynchronous to the internal clock.
The RESET pin is sampled during state 5, phase 2 of
every machine cycle. After a HIGH is detected at the
RESET pin, an internal reset is repeated until RESET goes
LOW.

The internal RAM is not affected by reset. When V

switched on the RAM contents are indeterminate.

13.1

Reset operation for the OSD SFRs

There are 12 OSD Special Function Registers: OSAT,
OSDT, OSAD, OSCON, OSCON2, OSORGV, OSORGH,
OSDDEF, OSSTART, HDEL, OSFBD and OSPLL.

The OSD SFRs are only updated when VSYNC and
HSYNC are present. If these signals are not present during
a reset operation then the OSD SFRs will retain their
values held after a Power-on reset.

In existing television systems HSYNC and VSYNC are
often generated by a dedicated IC, consequently during
start-up these signals may not be present. In this situation,
it is mandatory to initialize all the OSD registers before
entering the application.

13.2

Power-on reset

The P8xCx66 contains on-chip circuitry which switches the
port to the customer defined logic level as soon as V

exceeds 3.9 V. As soon as the minimum supply voltage is
reached, the oscillator will start-up. However, to ensure
that the oscillator is stable before the controller starts, the
reset is extended internally for 2048 oscillator periods.
A hysteresis of approximately 500 mV at a typical
power-on switching level of 3.9 V will ensure correct
operation.

An automatic reset can be obtained at power-on by
connecting the RESET pin to V

via a 10

F capacitor.

At power-on, the voltage on the RESET pin is equal to V

minus the capacitor voltage, and decreases from V

the capacitor discharges through the internal resistor
R

RESET

to ground. The larger the capacitor, the more

slowly V

RESET

decreases. V

RESET

must remain above the

lower threshold of the Schmitt trigger input long enough to
effect a complete reset. The time required is
2048 oscillator cycles plus 2 machine cycles.

Fig.16 Reset configuration at RESET pin.

handbook, halfpage

MGL293

SCHMITT

TRIGGER

RESET

CIRCUITRY

RESET

Fig.17 Recommended Power-on reset circuity.

handbook, halfpage

MGL291

P8xCx66

RESET

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

Table 35 State of internal registers after a reset

REGISTER

ADDRESS

CONTENTS

(1)

ACC

E0H

0000 0000

F0H

0000 0000

DPL

82H

0000 0000

DPH

83H

0000 0000

IEN0

A8H

0000 0000

IEN1

E8H

0000 0000

IP0

B8H

00 0000

IP1

F8H

0000 0000

IX1

E9H

0000 0000

IRQ1

C0H

0000 0000

PSW

D0H

0000 0000

PCON

87H

XXX

0 0000

80H

1111 1111

90H

1111 1111

A0H

1111 1111

B0H

XXXX

1111

98H

1111 1111

OSDDEF

9CH

001

0010

S1ADR

DBH

0000 0000

S1CON

D8H

000 0000

S1DAT

DAH

0000 0000

S1STA

D9H

1111 1000

81H

0000 0111

TCON

88H

0000 0000

TH0

8CH

0000 0000

TH1

8DH

0000 0000

TL0

8AH

0000 0000

TL1

8BH

0000 0000

TMOD

89H

0000 0000

Note

1. Where X = undefined state.

CCON

86H

XXXX X

OSAT

99H

XXX

1 1111

OSDT

9AH

1111 1111

OSAD

9BH

0000 0000

OSCON

C1H

0001 1100

OSORGV

C2H

11 1111

OSORGH

C3H

111 1111

OSPLL

C4H

0000 0000

OSSTART

C5H

0000 0000

HDEL

C6H

XXXX

0000

OSFBD

C7H

XXXX

0000

SAD

C8H

0000 0000

S1IST

DCH

0000 0000

VINT

C9H

XXXX XXXX

SAD2

CAH

XXXX X

000

OSCON2

CFH

XXX

0 0010

TDACL

D2H

0000 0000

TDACH

D3H

0X00 0000

PWM0

E4H

0000 0000

PWM1

E5H

0000 0000

PWM2

E6H

0000 0000

PWM3

E7H

0000 0000

PWM4

ECH

0000 0000

PWM5

EDH

0000 0000

PWM6

EEH

0000 0000

PWM7

EFH

0000 0000

WDT

FFH

0000 0000

REGISTER

ADDRESS

CONTENTS

(1)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

14 PIN FUNCTION SELECTION

Ports 1, 3 and 5 are dual purpose ports and can be
configured as general I/O port lines or selected as
alternative functions. Selection of the pin function as an
alternative function is achieved by setting the associated
port latch bit to a logic 1 and then enabling the alternative
function using its associated SFR.

14.1

Port 1 pin function selection

Port 1 is an 8-bit port which can be configured as eight
bidirectional port lines (P1.0 to P1.7) or as two external
interrupts (INT0 and INT1), two timer/counter inputs
(T0 and T1) and the I

C-bus lines (SDA and SCL).

P1.0 and P1.7 have no alternative functions.

To configure these pins as alternative functions the
corresponding bit in the Port 1 Latch (P1) should be
programmed to a logic 1. The I

C-bus lines are enabled by

setting the I

CE bit in the I

C-bus Port Control Register,

see Section 10.8. The remaining alternative functions are
enabled using the associated SFR.

To use Port 1 pins as general I/O lines the alternative
functions must be disabled.

14.2

Port 5 and P3.3 pin function selection

Port 5 pins can be selected as eight bidirectional port lines
(P5.0 to P5.7) or as seven 7-bit PWM outputs
(PWM0 to PWM6) and one 14-bit PWM output (TPWM).

Each 7-bit PWM output can be selected by setting the
PWMnE bit in its associated PWMn register, to a logic 1
(see Section 15.1). When the PWMnE bit is a logic 0 the
port line function is selected. The 14-bit PWM output
(TPWM) is selected by setting the TPWME bit in SFR
TDACH to a logic 1 (see Section 15.2).

P3.3 can also be selected as a bidirectional port line (P3.3)
or as a 7-bit PWM output (PWM7). The 7-bit PWM output
is enabled by setting the PWME7 bit in SFR PWM7 to a
logic 1 (see Section 15.1).

14.3

Port 3 pin function selection

Port 3 is a 4-bit port which can be configured as four
bidirectional port lines (P3.0 to P3.3) or as 3 ADC inputs
(ADC0 to ADC2) and one 7-bit PWM output (PWM7).
The selection of the PWM7 output is discussed in
Section 14.2.

To select the alternative function of these port lines the
corresponding bit in the Port 3 Latch (P3) should be
programmed to a logic 1. The ADC inputs are then
enabled using the SFR SAD2 as described in
Section 14.3.1.

To use Port 3 pins as general I/O lines the alternative
functions must be disabled.

14.3.1

ADC C

ONTROL

EGISTER

2 (SAD2)

Table 36 ADC Control Register 2 (SFR address CAH)

Table 37 Description of SAD2 bits

ADCE2

ADCE1

ADCE0

BIT

SYMBOL

DESCRIPTION

7 to 3

These 5 bits are not used.

ADCE2

ADC2 input select. If ADC2 = 1, the ADC2 input is selected. If ADC2 = 0, the
open-drain bidirectional port line P3.2 is selected.

ADCE1

ADC1 input select. If ADC1 = 1, the ADC1 input is selected. If ADC2 = 0, the
open-drain bidirectional port line P3.1 is selected.

ADCE0

ADC0 input select. If ADC0 = 1, the ADC0 input is selected. If ADC0 = 0, the
open-drain bidirectional port line P3.0 is selected.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

15 ANALOG CONTROL

The P8xCx66 has nine Pulse Width Modulated (PWM)
outputs for analog control purposes e.g., volume, balance,
brightness, voltage synthesized tuning etc. Each PWM
output generates a pulse pattern with a programmable
duty cycle.

The nine PWM outputs are specified below:

8 PWM outputs with 7-bit resolution (PWM0 to PWM7)

1 PWM output with 14-bit resolution (TPWM).

The 7-bit PWM outputs are described in Section 15.1 and
the 14-bit PWM output is described in Section 15.2.

15.1

7-bit PWM outputs (PWM0 to PWM7)

The block diagram of a typical 7-bit PWM circuit is shown
in Fig.19.

PWM outputs PWM0 to PWM7 share the same pins as
general I/O port lines P5.1 to P5.7 and P3.3 respectively.
Selection of the pin function as either a PWM output or
general I/O port line is achieved by setting the PWMnE bit
in the associated PWM register (where n = 0 to 7).
The PWM registers are shown in Table 38.

The clock frequency of each PWM circuit is

osc

and

therefore the repetition frequency of each 7-bit PWM
output is

512

osc

The polarity of each PWM output is fixed active HIGH.
The HIGH period of each PWM output is dependent upon
the contents of the PWM data latch and may be calculated
as shown below:

where (PWMn) is the decimal value held in the PWMn data
latch

The PWM output analog value is determined by the ratio
of the HIGH period and the repetition period. A DC voltage
proportional to the PWM control setting is obtained by
means of an external integration network (low-pass filter)
connected to the PWM output pin.

The rising edge of each of the 8 PWM outputs is separated
by one

osc

cycle, this is shown in Fig.21. PWM1 will

always start at `2', and PWM5 will start at `6' independent
of other PWMs value.

Figure 20 shows active HIGH PWM output patterns.

HIGH

PWMn

(

)

osc

----------------------------------

Table 38 7-bit PWM data registers

REGISTER

ADDRESS

PWM0

E4H

PWM0E

data6

data5

data4

data3

data2

data1

data0

PWM1

E5H

PWM1E

data6

data5

data4

data3

data2

data1

data0

PWM2

E6H

PWM2E

data6

data5

data4

data3

data2

data1

data0

PWM3

E7H

PWM3E

data6

data5

data4

data3

data2

data1

data0

PWM4

ECH

PWM4E

data6

data5

data4

data3

data2

data1

data0

PWM5

EDH

PWM5E

data6

data5

data4

data3

data2

data1

data0

PWM6

EEH

PWM6E

data6

data5

data4

data3

data2

data1

data0

PWM7

EFH

PWM7E

data6

data5

data4

data3

data2

data1

data0

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

15.2

14-bit PWM output (TPWM)

The on-chip 14-bit DAC has one output with a resolution of
16384 levels for Voltage Synthesized Tuning (VST).
The output is active HIGH, the HIGH period being
determined by the values stored in the SFRs TDACH and
TDACL. The 14-bit DAC output is connected to the TPWM
pin.

TPWM shares the same pin as port line P5.0. Selection of
the pin function as either a PWM output or as a port line is
achieved using the TPWME bit in SFR TDACH, see
Section 15.2.5.

The block diagram for the 14-bit PWM circuit is shown in
Fig.22 and consists of:

Two 7-bit SFRs: TDACH and TDACL

One 14-bit register TDACREG

One coarse control block for the generation of the
coarse adjustment pulse

One fine control block for the generation of the fine
adjustment pulses

One 14-bit counter running at f

TDAC

One mixer block that combines the coarse adjustment
pulse and fine tuning pulses; the resultant pulse pattern
is fed to the TPWM output.

Data is loaded into the 14-bit data latch (TDACREG) from
the two 7-bit data latches (TDACL and TDACH) at the
beginning of the first T

sub

period, after TDACH has been

written to. To ensure that correct data is loaded into
TDACREG, the data held in TDACL must be valid before
the write operation to TDACH is started. In other words,
TDACL must be written first before TDACH can be written
to. Examples of valid and invalid loading sequences are
shown in Fig.23.

Once TDACREG has been loaded it takes one T

sub

period

to generate the appropriate pulse patterns. To ensure
correct operation of the DAC, two T

sub

periods should be

allowed before any further changes to the data latches are
made.

The upper seven bits of TDACREG, identified as VSTH,
are used for coarse adjustment and the lower seven bits,
identified as VSTL, are used for fine adjustment.
The outputs OUT1 and OUT2 of the coarse and fine pulse
controllers are `ORed' in the mixer to give the TPWM
output.

The 14-bit counter is continuously running and is clocked
by f

TDAC

which is

osc

Figure 24 shows the output of the coarse pulse controller
when VSTH = 001 1101; Fig.25 shows the output of the
fine pulse controller when VSTL = 1111010, and Fig.26
shows a typical TPWM output after the `OR' operation has
been carried out by the mixer.

15.2.1

EPETITION TIME OF

OUT1

AND

OUT2:

The repetition period of OUT1 (T

sub

) may be calculated as

shown in Equation (1).

(1)

Where

The repetition period of OUT2 (T

std

) may be calculated as

shown in Equation (2).

(2)

15.2.2

OARSE ADJUSTMENT

An active HIGH pulse is generated in every subperiod
(except the first one); the pulse duration being determined
by the contents of VSTH. The coarse pulses are generated
at the OUT1 output. The coarse pulse output is LOW at the
start of each subperiod and will remain LOW until the time

has elapsed. The output will then go

HIGH and remain HIGH until the start of the next
subperiod. The coarse pulse duration is

The trailing edge of each coarse pulse coincides with the
end of each T

sub

period. If VSTH = 0000000, then the

coarse output is LOW for the complete period. If the
contents of VSTH = 1111111, then the coarse output is
LOW for the first t

period but will go HIGH for the

remaining 127

periods of Tsub.

15.2.3

INE ADJUSTMENT

Fine adjustment is achieved by generating an additional
pulse in specific subperiods. These additional pulses
appear at the OUT2 output. The pulse is added at the start
of the selected subperiod and has a pulse width of t

The value held in VSTL determines the subperiod in which
an additional pulse is generated and also determines the
number of additional pulses that will be added during one
T

std

period. Table 39 shows the relationship between the

value held in VSTL, the subperiod during which an
additional pulse OUT2 is generated and the total number
of additional OUT2 pulses generated.

sub

128

TDAC

--------------

128

TDAC

--------------

std

128

TDAC

---------------

128

16384

128

VSTH

(

)

[

]

VSTH

(

)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

For example, if the contents of VSTL = 000 0000, no
additional pulses are generated; if the contents of
VSTL = 111 1111, the number of additional pulses that are
generated is 127. Therefore, up to 127 additional pulses
can be added during a T

std

period. Additional pulses must

be distributed equally in one T

std

period (pulse distribution

procedure).

Figure 25 shows some examples of OUT2.

15.2.4

TPWM

OUTPUT

If the contents of VSTH = 001 1101, and the contents of
VSTL = 000 0010, then the TPWM output is as shown in
Fig.26. The additional OUT2 pulses are generated in
subperiods 32 and 96.

Two extreme cases are worthy of further analysis:

VSTH = 000 0000, and VSTL = 000 0000. No coarse
pulses will be generated and OUT1 is LOW for the whole
T

std

period. No fine pulses will be generated and

consequently TPWM is LOW for the whole T

std

period.

VSTH = 111 1111 and VSTL = 111 1111. This value of
VSTH results in OUT1 being LOW for the first t

period

but will go HIGH for the remaining 127

periods in the

sub

cycle. This value of VSTL will generate

127 additional fine pulses (in every T

sub

cycle except in

sub0

). These additional fine pulses fill the gaps in the

OUT1 output (except in T

sub0

). Consequently, the

TPWM output will be LOW for the first t

period (T

sub0

)

but will be HIGH for the remainder of the T

std

period.

Table 39 Additional pulse distribution

VSTL

CONTENTS

ADDITIONAL PULSE GENERATED

IN SUBPERIOD T

subn

BINARY POSITION

TOTAL NUMBER OF

ADDITIONAL OUT2 PULSES

000 0000

000 0001

100 0000

000 0010

32, 96

010 0000

000 0011

32, 64, 96

100 0000
010 0000

000 0100

16, 48, 80, 112

001 0000

000 0101

16, 48, 64, 80, 112

100 0000
001 0000

000 1000

8, 24, 40, 56, 72, 88, 104, 120

000 1000

001 0000

4, 12, 20, 28, 36, 44, 52, 60, ...116,
124

000 0100

010 0000

2, 6, 10, 14, 18, 22, 26, 30, ...122, 126

000 0010

100 0000

1, 3, 5, 7, 9, 11, 13, 15, ...125, 127

000 0001

111 1110

1, 2, 3, 4, ...62, 63, 65, 66, ...125, 126,
127

010 0000
001 0000
000 1000
000 0100
000 0010
000 0001

126

111 1111

1, 2, 3, 4, 5, 6, 7, ...125, 126, 127

100 0000
010 0000
001 0000
000 1000
000 0100
000 0010
000 0001

127

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

16 ANALOG-TO-DIGITAL CONVERTERS (ADC)

The 3 channel ADC consists of a 4-bit Digital-to-Analog
Converter (DAC), a comparator, an analog channel
selector and control circuitry. The block diagram of the
ADC circuit is shown in Fig.27.

One of these channels can be used to measure the level
of the Automatic Frequency Control signal. This is
achieved by comparing the ADC signal with the output of
a 4 bit DAC using the comparator (accuracy

LSB).

The ADC inputs ADC0, ADC1 and ADC2 share the same
pins as general I/O port lines P3.0, P3.1 and P3.2,
respectively. Selection of the pin function as either an ADC
input or a general I/O port line is achieved using bits
ADCE0, ADCE1 and ADCE2 in SFR SAD2 (see
Section 16.2).

The conversion time of the ADC is equal to 8 machine
cycles (8

s at 12 MHz). Some NOP instructions should be

added in between the instruction which changes the
reference voltage or the channel selection and the
instruction which reads the VHI register bit. The ST bit
must be set to a logic 1 at the same time as the reference
voltage or channel selection change, otherwise the VHI
state of the previous comparison will be read out.
The recommended procedure is as follows:

1. Write SFR SAD (X, CH<1:0>, ST = 1, SAD<3:0>)

2. Wait 8 machine cycles (for example 8 NOPs)

3. Read SFR SAD for VHI value.

ST is reset by hardware when it is set to a logic 1 by a
written instruction. When ST is read, the value is always a
logic 0.

Fig.27 ADC block diagram.

handbook, full pagewidth

4-BIT DAC

COMPARATOR

SAD3

SAD2

SAD1

SAD0

ADCE1

ADCE0

ADCE2

CH1

CH0

MGL397

ADC enable selection (SFR address: CAH)

AFC value selection (SFR address: C8H)

ENABLE

SELECTOR

ADC

CHANNEL

SELECTOR

P3.2/ADC2

P3.1/ADC1

P3.0/ADC0

Vref

DERIVATIVE PORT

SELECTOR

EN1

EN0

VHI

(SFR address: C8H)

internal bus

Channel selection

EN2

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

16.1

ADC Control Register 1 (SAD)

Table 44 ADC Control Register 1 (SFR address C8H)

Table 45 Description of SAD bits

Table 46 ADC input channel selection

16.2

ADC Control Register 2 (SAD2)

Table 47 ADC Control Register 2 (SFR address CAH)

Table 48 Description of SAD2 bits

VHI

CH1

CH0

SAD3

SAD2

SAD1

SAD0

BIT

SYMBOL

DESCRIPTION

VHI

Compare result. If VHI = 0, then the ADC input voltage is lower than the reference
voltage. If VHI = 1, then the ADC input voltage is higher than the reference voltage.

CH1

ADC input channel selection. These 2 bits select the ADC channel, see Table 46.

CH0

Start voltage comparison. If ST = 0, voltage comparison is disabled. If ST = 1, a
voltage comparison is started.

SAD3

Reference voltage level selection. These 4 bits are used to select the analog output
voltage (V

ref

) of the 4-bit DAC. V

ref

is calculated as shown below.

SAD2

SAD1

SAD0

CH1

CH0

CHANNEL SELECTED

Reserved.

Input channel ADC0 selected.

Input channel ADC1 selected.

Input channel ADC2 selected.

ADCE2

ADCE1

ADCE0

BIT

SYMBOL

DESCRIPTION

7 to 3

These 5 bits are not used.

ADCE2

ADC2 input select. If ADC2 = 1, then pin 11 is selected as the ADC2 input. If
ADC2 = 0, then pin 11 is selected as the open-drain bidirectional port line P3.2.

ADCE1

ADC1 input select. If ADC1 = 1, then pin 10 is selected as the ADC1 input. If
ADC2 = 0, then pin 10 is selected as the open-drain bidirectional port line P3.1.

ADCE0

ADC0 input select. If ADC0 = 1, then pin 9 is selected as the ADC0 input. If ADC0 = 0,
then pin 9 is selected as the open-drain bidirectional port line P3.0.

ref

----------

SAD value

(

)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17 ON-SCREEN DISPLAY (OSD)

17.1

Features

Programmable active level polarity of VSYNC, HSYNC
and digital RGB with polarity selection

Display RAM: 192

12 bits

Display character fonts: 128 (126 customer fonts plus
2 reserved codes)

One programmable vertical starting position counter
giving 63 different vertical starting positions

One programmable horizontal starting position counter
giving 110 different horizontal starting positions

Character size: 4 character sizes on a line-by-line basis

Character matrix: 12

18 with no spacing between

characters

Foreground colours: 8 on a character-by-character
basis

Background/shadowing modes: Two primary modes:
TV mode and Frame mode on a frame basis. Each
primary mode has four sub-modes on a character row
basis:

Sub-mode 1: Superimpose (no background)

Sub-mode 2: North-West shadowing

Sub-mode 3: Box background

Sub-mode 4: Border shadowing.

Background colours: 8 on a word-by-word basis.
Available when background is either in North-West
shadowing, Box background, Border shadowing and
Frame shadowing sub-modes.

Display RAM starting address is programmable. Fast
switching between banks of display characters is
possible through software control.

HSYNC driven PLL (frequency determined by SFR
OSPLL)

Character blinking ratio: 1 : 1

Character blinking frequency: programmable using
f

VSYNC

divisors of 32 and 64, on a character basis

Display format: Flexible display format by using CR
(carriage return) and SP1, SP2 (space) and split space
code

Display RAM address post increment each time new
data is written

Vertical jitter cancelling circuit to avoid unstable VSYNC
leading edge mismatch with HSYNC signal

OSD clock operating frequency: 4 to 12 MHz

Meshing function.

17.2

Flexible display format

Figures 28 and 29 show typical examples of on-screen
displays generated by the P8xCx66.

There are 128 different fonts available two of which, the
Carriage Return (CR) code and the Space (SP) code, are
reserved for special functions. The CR code performs the
same function as the return key on a conventional
keyboard, the display will start on the next line. The SP
code enables the background colour of the space itself
and that of the following characters to be changed.

There are 192 display RAM locations (00H to BFH) and
these are considered as a linear addressed RAM. The first
character fetched is from the display RAM address pointed
to by the contents of the Special Function Register
OSSTART (see Section 17.3.5).

The OSD starting position is programmable, this is
described in detail in Section 17.2.1.

Two other registers are used to program the OSD:
OSCON and OSCON2. These registers are described in
Sections 17.3.2 and 17.3.6.

17.2.1

OSD

STARTING POSITION

The horizontal and vertical starting position of the display
is controlled by two counters: SFRs OSORGH and
OSORGV.

OSORGH controls the horizontal starting position. This
counter is incremented every OSD clock cycle after the
falling edge of HSYNCP (after the polarity selection).
HSYNCP is always active HIGH. OSORGH is described in
Section 17.3.4.

OSORGV controls the vertical starting position. This
counter is incremented every HSYNC cycle and is reset by
the VSYNC signal. OSORGV is described in
Section 17.3.3.

The OSD starting position reference points are shown in
Fig.32.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.3

OSD registers

17.3.1

OSD D

EFAULT

EGISTER

(OSDDEF)

This register is used to set the default values for background colour, character size and sub-mode after each VSYNC
pulse. After a system reset OSDDEF holds 22H. These values can be changed by writing new data to OSDDEF or by
starting the screen with a space code (SP1 or SP2) and a CR code.

Table 49 OSD Default Register (SFR address 9CH)

Table 50 Description of OSDEF bits

Table 51 Default sub-mode selection

The default value of OSDDEF gives the following initial settings:

Character size = 1 horizontal line/1 DOSC (Fig.31)

Background colour = blue (R = G = 0, B = 1)

Sub-mode = Box background mode.

BIT

SYMBOL

DESCRIPTION

Default background colour. These 3 bits select the default background colour.

This bit is reserved for future use (intensity output).

Default character size. If SV = 0, then the vertical dot size is equal to one horizontal
line. If SV = 1, then the vertical dot size is equal to two horizontal lines.

Default horizontal dot size. If SH = 0, then the horizontal dot size is equal to one OSD
clock. If SH = 1, then the horizontal dot size is equal to two OSD clocks.

Default sub-mode selection. These 2 bits select the default sub-mode; see Table 51.

SUB-MODE

Superimpose mode selected.

North-West shadowing mode selected.

Box background mode selected.

Border shadowing mode selected.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.3.2

OSD C

ONTROL

EGISTER

1 (OSCON)

Table 52 OSD Control Register 1 (SFR address C1H)

Table 53 Description of OSCON bits

Split

Mesh

Mode

OSDE

BIT

SYMBOL

DESCRIPTION

Split

Split space control. If Split = 0, then split space is disabled. If Spilt = 1, then split
space is enabled on frame-by-frame basis. Split space only effects Space 1 (SP1)
because Space 2 (SP2) is displayed transparent.

Mesh

OSD meshing mode. If Mesh = 0, then the OSD meshing mode is disabled.
If Mesh = 1, the OSD meshing mode is enabled.

Mode

Background mode selection. If Mode = 0, then TV mode is selected (FB only active
when there are characters displayed). If Mode = 1, then Frame mode is selected (FB is
active in every single active scan line; FB is inactive during horizontal and vertical
retrace period).

HSYNC active polarity selection. If Hp = 0, then HSYNC is an active LOW input.
If Hp = 1, then HSYNC is an active HIGH input. See Fig.30.

VSYNC active polarity selection. If Vp = 0, then VSYNC is an active LOW input.
If Vp = 1, then VSYNC is an active HIGH input. See Fig.30.

Active R, G, B and FB output polarity selection. If Bp = 0, then these signals are all
active LOW. If Bp = 1, then these signals are all active HIGH. See Fig.31.

Character blinking frequency control. If BF = 0, the blinking frequency is

VSYNC

. If

BF = 1, the blinking frequency is

VSYNC

. The duty cycle of the blinking frequency is

fixed at 1 : 1.

OSDE

OSD circuit general enable/disable. If OSDE = 0, the OSD is disabled and the R, G, B
and FB signals stay in the inactive status (inverse of the Bp bit in SFR OSCON). If
OSDE = 1, the OSD is enabled.

Fig.30 HSYNC and VSYNC active level selection.

handbook, full pagewidth

MGL284

character display interval

fly-back period

HSYNC/VSYNC pin
Hp/Vp = 1 (active HIGH)

HSYNC/VSYNC pin
Hp/Vp = 0 (active LOW)

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.3.4

OSD H

ORIZONTAL

TART

EGISTER

(OSORGH)

Table 56 OSD Horizontal Start Register (SFR address C3H)

Table 57 Description of OSORGH bits

HP6

HP5

HP4

HP3

HP2

HP1

HP0

BIT

SYMBOL

DESCRIPTION

This bit is not used.

HP6

Horizontal starting position selection. These 7 bits select the horizontal starting
position of the OSD. 1 from 110 starting positions may be selected.The reference point
of the horizontal starting position is the leading edge of HSYNC. The horizontal starting
position (HP) is calculated as follows:

Where (HP6

HP0) is the decimal value of the contents of OSORGH and

(HP6

HP0)

12H.

Note that the period of the horizontal starting position plus characters display cannot be
more than one HSYNC period (for example 64

s).

HP5

HP4

HP3

HP2

HP1

HP0

HP6

HP0

(

)

OSD clock

Fig.32 OSD starting position reference points.

handbook, full pagewidth

MGL285

VPx

HPx

Personal preferrance
Sound
Picture
Tuning

Leading edge of HSYNCP is the reference point of HPx
Leading edge of VSYNCP is the reference point of VPx

HSYNCP

VSYNCP

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.3.5

OSD S

TART

EGISTER

(OSSTART)

Table 58 OSD Start Register (SFR address C5H)

Table 59 Description of OSSTART bits

17.3.6

OSD C

ONTROL

EGISTER

2 (OSCON2)

Table 60 OS Control Register 2 (SFR address CFH)

Table 61 Description of OSCON2 bits

START7

START6

START5

START4

START3

START2

START1

START0

BIT

SYMBOL

DESCRIPTION

START7

RAM start address. These 7 bits specify the display RAM address from which the first
character will be fetched. The display RAM address is from 0 to 191 decimal, or
00 to BF hexadecimal.

START6

START5

START4

START3

START2

START1

START0

TCEN

BIT

SYMBOL

DESCRIPTION

These 3 bits are reserved.

TCEN

Test Code Enable. When TCEN = 1, the content of the space from character ROM is
displayed. This is valid for Space 1 and Space 2. The default value of TCEN is a logic 0.
This feature is for testing purposes only.

Background colour selection. These 3 bits select the background colour of the
TV screen in the Frame mode. The default background colour is blue.

This bit is reserved.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.4

OSD clock generator

The clock generator comprises Phase-Locked-Loop circuitry. The frequency of the OSD clock is programmable and is
determined by the decimal value of the contents of the 8-bit OSPLL register. OSD clock frequencies within the range
4 to 12 MHz can be selected in increments of 31.25 kHz. The OSD frequency (f

OSD

) is calculated as shown below:

Where f

HSYNCP

is the horizontal sync frequency after the polarity selection circuit.

17.4.1

OSD PLL R

EGISTER

(OSPLL)

The reset value of OSPLL is 00H.

Table 62 OSD PLL Register (SFR address C4H)

Table 63 Description of OSPLL bits

Table 64 Selection of OSD clock frequency

PLL7

PLL6

PLL5

PLL4

PLL3

PLL2

PLL1

PLL0

BIT

SYMBOL

DESCRIPTION

7 to 0

PLL7 to PLL0 These 8 bits are used to select the OSD clock frequency. Examples of OSD clock

selection are shown in Table 64.

OSPLL VALUE

OSD FREQUENCY (MHz)

00H

4.00

3FH

6.00

7FH

8.00

BFH

10.00

FFH

12.00

OSD

HSYNCP

129

OSPLL value

(

)

Fig.33 OSD PLL.

handbook, halfpage

MGM681

OSPLL

(C4H)

DIVIDER

SYSCLK

fOSD

HSYNC

PLL

HSYNCP

LOAD_SFR

RESET

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.5

Display RAM organization

The display character RAM is organized as 192

12 bits.

The general format of each RAM location is as follows.
Bits <11-5> hold character data: 1 out of 128 different
character fonts may be specified (126 customized fonts
plus 2 reserved codes). Bits <4-0> hold attribute data of
the character font, for example, colour, character size etc.

17.5.1

ISPLAY

RAM

FORMATS

There are four different formats to be considered:

1. Customer character code.

2. Carriage Return code

3. Space code 1 and Space code 2.

These formats are shown in Tables 70 to 72.

17.5.1.1

Customer character code

If bits <11-5> are in the range 00H to 7CH then this is a
customized character code.

Bits <4-2> select the character colour, a choice of
8 colours are available.

Bit <0> determines whether the character blinks or not.
The actual blinking frequency is determined by the BF bit
in SFR OSCON.

17.5.1.2

Carriage Return code

If bits <11-5> hold 7EH then this is the Carriage Return
code. A transparent pattern will be displayed on the
screen, the current display row will be terminated and the
character stored in the display RAM next to this code will
be displayed at the beginning of the next row.

Bits <4-3> select the size of the characters to be displayed
in the next row. The character size is independently
controlled in both the vertical and the horizontal direction.
Bit <4> controls the vertical size as shown in Table 65 and
bit <3> controls the horizontal size as shown in Table 66.
Figure 34 shows the four different character sizes
available.

Bits <2-1> select the display sub-mode of the next row.
Four sub-modes can be selected (see Table 67) in either
the Frame mode or the TV mode. Therefore a total of
8 different modes are available, these are illustrated in
Figs 35 and 36.

Bit <0> is the end of display control bit and stops the
display function before the last display RAM address
(191 decimal). By combining the `end of display' feature
with the start RAM address (controlled by SFR OSSTART)
the display RAM can be configured into several banks for
fast display data switching. The states of the end of display
control bit are defined in Table 68.

Table 65 Selection of vertical size

Table 66 Selection of horizontal size

Table 67 Selection of sub-modes

Table 68 End of display control

BIT 4

VERTICAL SIZE

One vertical dot is equal to one horizontal
scan-line width.

One vertical dot is equal to two horizontal
scan-line widths.

BIT 3

HORIZONTAL SIZE

One horizontal dot is equal to one OSD clock
width.

One horizontal dot is equal to two OSD clock
widths.

BIT 2

BIT 1

SUB-MODE

Superimpose

North-West shadowing

Box shadowing

Border shadowing

BIT 0

OPERATION

Continue to display in next row.

Stop the display and wait for the next display
field. As soon as the horizontal and vertical
starting position has been reached, continue
to display.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.5.1.3

Space code 1 and Space code 2

If bits <11-5> hold 7FH, then this is a space code. One of
two space codes can be selected: Space code 1 and
Space code 2.

Space code 2 always displays a transparent pattern, equal
to one character width, on the screen regardless of which
primary mode and sub-mode is selected. Space code 1
only differs from Space code 2 when in the Box shadowing
sub-mode. In this mode SP1 displays a 12

18 dot matrix

pattern filled with the background colour whilst SP2
displays a transparent pattern. See Figs 37 and 38.

Selection of a specific space code is determined by the
state of bit 0 as detailed in Table 69.

Table 69 Selection of Space code

Bits <4-1> determine the background colour of the
characters that follow the space code dependent upon the
sub-mode selected, see Figs 35 and 36.

BIT 0

SPACE CODE

Space code 1 is selected.

Space code 2 is selected.

In North-West shadowing sub-mode the background
colour is the colour of the bit pattern shadow

In Box shadowing sub-mode the background colour is
the colour within the character 12

18 dot matrix where

no foreground character bits are present

In the Superimpose sub-mode there is no background
colour

In the Border shadowing sub-mode the background
colour is the colour of the border bit pattern.

17.5.1.4

Summary of CR, SP1 and SP2 functions

Carriage Return code:

Ends the current display row and uses the character

in the display RAM next to this CR code as the first
character of next display row

Selects the character size of next display row

Selects the character sub-mode of next display row

Indicates the end of display for present screen.

Space code 1 and Space code 2:

Inserts transparent pattern in a row of characters

Selects the background colour of the characters

following this space code.

Table 70 Format of Character font code

Table 71 Format of Carriage Return code

Table 72 Format of Space code

Character Font code (00H to 7CH)

Foreground colour

Blink

Carriage Return code (7EH)

Character size

Mode

End

Space code 1 and Space code 2 (7FH)

Background colour

SP1
SP2

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.6

Loading character data into display RAM

Three registers are used to address and load data into the
display RAM: OSAD, OSDT and OSAT. These registers
are described in Sections 17.6.1 to 17.6.3.

17.6.1

OSD A

DDRESS

EGISTER

(OSAD)

This register holds the address of the location in display
RAM, into which character data is to be written.

Table 73 OSD Address Register (address 9BH)

17.6.2

OSD D

ATA

EGISTER

(OSDT)

This register holds the character font data that will be
loaded into bits <11-5> of the location in RAM addressed
by the contents of OSAD.

Table 74 OSD Data Register (address 9AH)

17.6.3

OSD A

TTRIBUTE

EGISTER

(OSAT)

This register is loaded with character attribute data.
The data will be loaded into bits <4-0> of the location in
RAM addressed by the contents of OSAD. The actual
attribute is dependent upon whether the Character Font
Code, Carriage Return Code, Space Code 1 or Space
Code 2 has been selected.; this is explained in
Section 17.5.1. Bits 7 to 5 are not used and are reserved.

Table 75 OSD Attribute Register (address 99H)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

17.7

Writing character data into the display RAM

The procedure for writing character data into the display
RAM is as follows:

1. Initialize the starting address of the display RAM by

writing data into OSAD.

2. Write the character attributes to OSAT. If the attributes

of a series of displayed characters are the same, the
contents of this register need not be changed; only
OSDT need be updated.

3. Write the character font code to be displayed to OSDT.

When the write to OSDT operation is finished an
automatic transfer occurs that loads the data stored in
OSAT and OSDT into the display RAM location
addressed by OSAD. The address held in OSAD is
then incremented by `1'.

4. Post increment operation is executed in OSAD

(OSAD

OSAD + 1) making it point to the next RAM

location. On overflow OSAD is cleared. Figure 39
shows the post-increment operation.

Fig.39 OSAD post-increment operation.

handbook, halfpage

MGL282

189

190

191

OSAD

numbers are in decimal

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.8

Character ROM

128 character fonts may be stored in ROM: 126 customer
selected character fonts plus two reserved codes (the
Carriage Return code and the Space code).

Each character font is stored in a 12

19 dot matrix in

character ROM. However, only elements in rows 1 to 18
can be selected as visible dots on the TV screen. Row 0 is
used only in the North-West shadowing sub-mode and the
Border shadowing sub-mode when two character cells are
to be combined in a vertical direction to formulate a new
pattern. If combination of character fonts is not required
then row 0 should be filled with zeros. An example of a bit
pattern stored in ROM is shown in Fig.40.

A software package that helps the customer design the
character fonts on the screen and that also generates the
bit pattern HEX files automatically, is available on request,
from local Philips sales organisations. The package is run
under the MS-DOS environment for IBM compatible PCs.

17.9

Character ROM organization

ROM is divided into two parts: OSDL and OSDH.
The address of OSDL is from 0000H to 0FFFH and the
address of OSDH is from 1000H to 1FFFH.

The organisation of the bit patterns stored in ROM and the
file format to submit to Philips for customized character
sets is shown in Fig.40. Regarding Fig.40 the following
points should be noted.

1. Each character is structured using 38 bytes.

2. Row 0 of each font is reserved for vertical combination

of two fonts. In vertical mergence row 0 holds the
same code as row 18 of the previous font.

3. Binary 1 denotes visual dots.

4. ROM data files are in Intel HEX format on a byte basis.

Each byte is structured high nibble followed by low
nibble.

5. The unused bytes in ROM must be filled with FFH.

17.10 Combination of two or more font cells

Two (or more) character font cells may be combined in a
vertical or horizontal direction to create a new higher
resolution pattern.

The combination of two cells in a horizontal direction is
straight forward and presents no problems to the user.
All 4 background/shadowing sub-modes can be used.

However, the combination of two character font cells in a
vertical direction is more difficult and care must be taken
otherwise the new pattern may be created with gaps in its
shadowing.

Row 0 in the character ROM is for use in the North-West
shadowing and Border shadowing sub-modes. If either
of these sub-modes is selected when combining two
character cells in a vertical direction then row 0 must
contain the bit pattern of row 18 of the font above it
otherwise a broken dot in the shadow may occur.

17.11 More about North-West shadowing and Border

shadowing sub-modes

Some special care must be taken when designing the
character bit pattern if the character is intended to be used
in the North-West shadowing or Border shadowing
sub-mode.

North-West shadowing and Border shadowing
sub-modes are limited in the 18 display scan lines box
only in the vertical direction if the character in the next
row is not in North-West shadowing sub-mode
(otherwise as described in Section 17.10) if the shadow
of the last foreground bit pattern line is intended to be
seen as well. To get correct shadowing following the
character font then in:

North-West shadowing: row 18 must be blank

Border shadowing: row 1 and 18 must be blank.

North-West shadowing and Border shadowing
sub-modes are not limited to the 12 horizontal OSD
dots. Shadows of the previous font cell may cross over
the 12 dot boundary and appear in the next font cell.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

Fig.40 Character bit pattern stored in on-chip ROM.

MGL312

k, full pagewidth

0
1
2
3
4
5
6
7
8
9

12
13
14
15
16
17

2
3
2
2
3
2
2
3
0
0
5
5
0
0
0

2
F
2
2
F
2
2
F
0
0
5
5
0
0
5

0
0

0
3
2

0
F
2

0
0
F
1
1
3
2
6

0 3 0

F 2
F 3
F 2
F 2
F 3
F 2
F 2
F 3
F 0
F 0
F 5
F 5
F 0
F 0
F 0

F 0
F 3
F 2

F 0

10 0020 00
10 0030 00
10 0040 00
..................
10 0FE0 00
10 0FF0 00
10 1000 00
10 1010 00
10 1020 00
10 1030 00
10 1040 00
.................
10 1FE0 00
10 1FF0 00

Intel Hex
Format

Byte#

10 0000 00
10 0010 00

OSDL

FF
FF
F0
F0

OSDH

FF
FF

00
0C

FF
FF
F3
F0

FF
FF

FC
58

FF
FF
F2
F0

FF
FF

20
30

....
FF
FF
F2

....
FF
FF

....

---

FF
FF
F3

....
FF
FF

....
FF
FF
F2

....
FF
FF

....
FF
FF
F2

....
FF
FF

20
Data for font 2 OSDL

Data for font 3 OSDL

....
FF
FF
F3

....
FF
FF

....
FF
FF
F2

....
FF
FF

....
FF
FF
F2

....
FF
FF

Data for font 4

....
FF
FF
F3

....
FF
FF

FF
FF
F0

FF
FF

FF
FF
F0

FF
FF

FF
FF
F5

FF
FF

FF
FF
F5

FF
FF

FF
FF
F0

FF
FF

11 10 9 8 7 6 5 4 3 2 1 0

EPROM

OSDH

ROM

2 0

F C

2 0
2 0

F C

2 0
2 0

F F

0 1
0 1
5 3
5 2
0 6

0 C

5 8

0 0

F C

2 0

3 0

EPROM

OSDL

Row

Column

MSB

LSB

---

Data for font 2 OSDH

---

Data for font 3 OSDH

Data for font 4

---

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.12 Maximum number of characters per row

The number of characters per row is a function of the OSD
clock frequency and the TV standard used.

The active video signal period of a horizontal line is
53.5

s. However, in order to reduce jittering at the screen

edge, overscan is normally applied by the TV
manufacturer and this reduces the visible video signal
period to 48.15

The examples given below show how the number of
characters per row and the character width may be
obtained for the NTSC 525LPF/60 Hz TV standard using
different OSD clock frequencies.

17.12.1 NTSC 525LPF/60 Hz; f

OSD

= 6 MH

As f

OSD

= 6 MHz; T

OSD

= 0.1666

The number of visible dots on one horizontal line is 290
(48.15

s/0.1666

Each character is composed of a 12 x 18 dot matrix;
therefore the maximum number of characters on one
line is 24 (290/12)

If a 19 inch TV screen is used, the width of a horizontal
line is approximately 370 mm and this gives a character
width of 15.4 mm (370/24).

17.12.2 NTSC 525LPF/60 H

; f

OSD

= 10 MH

As f

OSD

= 10 MHz; T

OSD

= 0.1

The number of visible dots on one horizontal line is 481
(48.15

s/0.1

Each character is composed of a 12 x 18 dot matrix;
therefore the maximum number of characters on one
line is 40

If a 19 inch TV screen is used, the width of a horizontal
line is approximately 370 mm and this gives a character
width of 9.25 mm.

17.13 Maximum number of rows per frame

The number of rows per frame is a function of the number
of active lines per display field and the number of vertical
dots in the character matrix (which is 18). The number of
rows per frame (N) is calculated as shown below.

The two examples shown below illustrate how the
maximum number of rows per frame is obtained for
different TV scanning standards.

17.13.1 NTSC 525LPF/60 H

The number of active lines per field for this standard is
between 241.5 and 249 H. If the value of 241 is used then
the maximum number of rows per frame is 13.

17.13.2 PAL 625LPF/50 H

The number of active lines per field for this standard is 280.
Therefore, the maximum number of rows per frame is 15.

number of active lines per field

---------------------------------------------------------------------------------

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.14 OSD vertical debouncing circuit

The HSYNC and VSYNC signals entering the OSD circuit are usually extracted from the horizontal and vertical deflection
units of a television set. The shaping and timing of these signals is therefore related to several external conditions that
all have certain tolerances. The trigger levels of the input circuitry also influence the internal timing of HSYNC and
VSYNC. In the odd field the leading edge of both signals is very close, so jitter on one or both of them may result in
occasionally miscounting the number of lines in a field causing a displayed character to bounce up and down on a line.
To avoid this situation the HSYNC signal is delayed by a number of dot clocks. Because the relationship between HSYNC
and VSYNC is not fully known there are 16 user selectable delays available. The period of the horizontal starting position
plus the HDEL delay cannot exceed the HSYNC period.

17.14.1 H

ORIZONTAL

ELAY

EGISTER

(HDEL)

Table 76 Horizontal Delay Register (SFR address C6H)

Table 77 Description of HDEL bits

Table 78 Selection of HSYNC delay

HDEL3

HDEL2

HDEL1

HDEL0

BIT

SYMBOL

DESCRIPTION

7 to 4

These 4 bits are reserved.

HDEL3

HSYNC delay. The state of these 4 bits determines the delay time applied to the
HSYNC signal, see Table 78.

HDEL2

HDEL1

HDEL0

HDEL3

HDEL2

HDEL1

HDEL0

NO. OF DOT

CLOCKS

DELAY TIME AT

5 MHz (

DELAY TIME AT

10 MHz (

6.4

3.2

12.8

6.4

19.2

9.6

128

25.6

12.8

160

192

38.4

19.2

224

44.8

22.4

256

51.2

25.6

288

57.6

28.8

320

352

70.4

35.2

384

76.8

38.4

416

83.2

41.6

448

89.6

44.8

480

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.15 OSD meshing

Meshing results is a contrast reduction of a selected video
area. This reduced contrast enhances the reliability of the
OSD character displayed in that area without the loss of
the video information in that area in case of a normal solid
background. This feature is implemented by replacing the
normal character solid background by a checker-board
pattern background and inverts this pattern every new
frame. The checker-board pattern itself is generated by
switching FB on and off with a pixel frequency in the first
frame and off and on in the next frame only for those OSD
characters that have background switched on.

The OSD character itself or its contrast is not affected by
the meshing feature

The meshing function is frame based

Normal background is replaced by an alternating
meshing pattern

For meshing the meshing bit and the background mode
must be set

Meshing can only be activated in TV mode, e.g mode bit
(bit 5 in SFR OSCON) must be a logic 0.

Fig.43 TV/video signal superimposed with checker-board pattern.

handbook, full pagewidth

MGM684

TAXI

OSD background colour

checker-board pattern

TV/Video colour

Fig.44 Complete meshing feature.

handbook, full pagewidth

MGM685

TAXI

VOLUME

OLUME

IIII

OSD character

(not affected by the checker-board pattern

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

17.16 FB to RGB delay compensation

The P8xCx66 is connected to an analog video mixer. In the past analog mixers had different delays between FB and
RGB. To compensate for these differences, FB to RGB delay compensation is implemented on-chip. The delay time is
selected using the OSFBD register.

The delay compensation can be done with a resolution of

OSC

. The OSC clock runs at 4 times the OSD clock

frequency for OSD frequencies from 4 up to 6.75 MHz, and at 2 times the OSD clock frequency from OSD frequencies
from 6.75 MHz up to 12 MHz. At 4 MHz the delay unit is 33 ns, at 6.5 MHz the delay unit is 19 ns, at 8 MHz the delay
unit is 33 ns, at 10 MHz the delay unit is 25 ns and at 12 MHz the delay unit is 21 ns.

17.16.1 OSD FB D

ELAY

EGISTER

(OSFBD)

Table 79 OSD FB Delay Register (SFR address C7H)

Table 80 Description of OSFBD bits

Table 81 Selection of FB to RGB delay

FBD3

FBD2

FBD1

FBD0

BIT

SYMBOL

DESCRIPTION

7 to 5

These 3 bits are not used.

This bit must be set to a logic 0. If set to a logic 1, the character font will come from
internal logic instead of character ROM.

3 to 0

FBD3 to FB

FB to RGB delay select. These 4 bits select the delay unit multiple that will determine
the delay time between FB and RGB; see Table 81.

FBD3

FBD2

FBD1

FBD0

DECIMAL

VALUE

FB to RGB DELAY

Delay RGB with 7 units in relation to FB.

Delay RGB with 6 units in relation to FB.

Delay RGB with 5 units in relation to FB.

Delay RGB with 4 units in relation to FB.

Delay RGB with 3 units in relation to FB.

Delay RGB with 2 units in relation to FB.

Delay RGB with 1 units in relation to FB.

Delay RGB with 0 unit in relation to FB.

Delay FB with 0 unit in relation to RGB.

Delay FB with 1 unit in relation to RGB.

Delay FB with 2 units in relation to RGB.

Delay FB with 3 units in relation to RGB.

Delay FB with 4 units in relation to RGB.

Delay FB with 5 units in relation to RGB.

Delay FB with 6 units in relation to RGB.

Delay FB with 7 units in relation to RGB.

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

18 EPROM PROGRAMMER

18.1

Interface to the on-chip EPROMs

The P87C766 contains two EPROMs: the program
EPROM and the OSD EPROM. The EPROM memory map
is shown in Fig.46.

The 64K

8-bit program EPROM is subdivided into four

EPROM modules: Modules 1 to 4, each of 16 kbytes.

The 8K

8-bit OSD EPROM is subdivided into two

modules: OSDL and OSDH, each of 4 kbytes. The OSDL
module provides the 8 LSBs of the 12-bit character word
and the OSDH module provides the 4 MSBs of the 12-bit
character word. The 4 MSBs of OSDH are not used and
should be programmed to logic 1s.

To ensure greater reliability and to reduce power
consumption, all unused EPROM cells should be
programmed to logic 1s.

To program the EPROM modules, several functions of the
EPROMs must be mapped to the pins of the package.

The program EPROM uses 16 address lines: A0 to A15

A0 to A13 are used for the EPROM address

A14 and A15 are used to select one of the 4 program

EPROM modules; see Table 82.

The OSD EPROM uses 13 address lines A0 to A12

A0 to A11 are used for the EPROM address

A12 is used to select one of the 2 OSD EPROM

modules; see Table 83.

Data I/O: D0 to D7 are used for all EPROM modules

Write Enable (WE): active LOW programming pulse

Output Enable (OE): active LOW data output enable,
when in EPROM verify mode, OE must be LOW

Programming voltage: the programming and verification
voltage (V

) is typically 12.75 V; when programming

and verify operations have been completed V

should

be reduced to 0 V.

All other signals to be connected to the EPROM module in
the programming/verification mode are generated
internally. Table 84 gives an overview of the functions
mapped to the pins.

Programming and verification waveform characteristics
are specified in Chapter 21.

Table 82 Selection of Program EPROM modules

Table 83 Selection of OSD EPROM modules

A15

A14

PROGRAM EPROM MODULE

Module 1

Module 2

Module 3

Module 4

A12

OSD EPROM MODULE

OSDL module

OSDH module

Table 84 Truth table for EPROM modules

OPERATION MODE

I/O

ADDRESS LINES

Programming Program EPROM

12.75

data in

A0 to A15

Verification Program EPROM

12.75

data out

A0 to A15

Programming OSD EPROM

12.75

data in

A0 to A12

Verification OSD EPROM

12.75

data out

A0 to A12

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

18.2

EPROM Programming mode

In the EPROM programming mode the selected EPROM is
under the direct control of the external pins. For entering
the programming mode the RESET pin serves as the data
input and the XTALIN pin serves as the clock input. There
is no need to synchronise the addresses, data, read and
write signals with the CPU.

To enter the programming mode, the microcontroller must
first be reset in accordance to the normal reset procedure
to avoid the Idle mode. The programming code is then
shifted in serially via the RESET pin and stored in a
register. After decoding, the required control signals are
generated.

18.2.1

ERIAL PROGRAMMING CODES

Once the device has been reset the programming code
can be shifted in via the RESET pin. The 10-bit
programming code is shown in Fig.45 and defined in
Table 85.

Table 85 Programming code format

BIT

FUNCTION

9 to 6

Stop bits. These are the last 4 bits to be
shifted in and always take the value `0101',
indicating the end of the test mode code.

5 to 1

Mode bits. These 5 bits follow the start bit
and select the test mode; see Table 86.

Start bit. This is the first bit to be shifted in
and is always a logic 0, indicating that the
following 5 bits are test mode code.

Fig.45 Serial programming code.

handbook, halfpage

MGM683

bit 0

X X X X X

0 1 0

bit 9

Stop bits

Mode bits

Start bit

Table 86 Test mode selection.

18.2.2

NTERING THE

ROGRAMMING MODE

The procedure for entering the Programming mode is
detailed below and illustrated in Fig.47

1. The normal reset should be active for at least

24 XTALIN clocks:

a) The first 10 XTALIN clocks cancel any special

modes

b) The 24 XTALIN clocks (2 machine cycles) ensure

that the CPU core is reset.

2. Shift in the programming code via the RESET pin

3. Wait at least 2 XTALIN clocks until the control signals

are ready, then the EPROM address, data and control
signals can be applied. The RESET pin should be
released within 10 XTALIN clocks to prevent the circuit
escaping from EPROM programming mode.

18.2.3

EAVING THE

ROGRAMMING MODE

The device will exit the Programming mode when the
RESET pin is driven HIGH for at least 10 XTALIN clock
cycles.

18.3

Programming and verification

It is not recommended to carry out programming/verify
operations on a byte basis. It is far better to program all
program EPROM (or OSD EPROM) and then verify the
contents.

18.4

OSD EPROM bit map and the sequence of
programming OSDL and OSDH

Each character bit pattern is stored in the on-chip
ROM/EPROM. The character displayed on the screen is in
a 12

18 dot matrix format, however it is stored in the

on-chip character ROM in a 12

19 format. For the OSD

EPROM character the dot matrix is 16

19, but only

19 is used, therefore the high nibble of OSDH must

be filled with FH.

MODE BITS

TEST MODE

Program EPROM

OSD EPROM

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

19 SPECIAL FUNCTION REGISTERS ADDRESS MAP

The SFRs are presented in ascending address order in Table 89 to aid designer/programmers quick reference.

Table 89 SFRs address map

ADDRESS

NAME

80H

(1)

P0 latch

P07

P06

P05

P04

P03

P02

P01

P00

81H

(1)

Stack Pointer (SP)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

82H

(1)

Data Pointer Low (DPL)

DPL7

DPL6

DPL5

DPL4

DPL3

DPL2

DPL1

DPL0

83H

(1)

Data Pointer High (DPH)

DPH7

DPH6

DPH5

DPH4

DPH3

DPH2

DPH1

DPH0

86H

C-bus Port Control Register (I

CCON)

87H

(1)

Power Control Register (PCON)

WLE

GF1

GF0

IDL

88H

(1)

Timer/Counter Control Register (TCON)

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

89H

(1)

Timer/Counter Mode Control Register (TMOD)

Gate

C/T

Gate

C/T

8AH

(1)

Timer 0 Low byte (TL0)

TL07

TL06

TL05

TL04

TL03

TL02

TL01

TL00

8BH

(1)

Timer 1 Low byte (TL1)

TL17

TL16

TL15

TL14

TL13

TL12

TL11

TL10

8CH

(1)

Timer 0 High byte (TH0)

TH07

TH06

TH05

TH04

TH03

TH02

TH01

TH00

8DH

(1)

Timer 1 High byte (TH1)

TH17

TH16

TH15

TH14

TH13

TH12

TH11

TH10

90H

(1)

P1 latch

P17

P16

P15

P14

P13

P12

P11

P10

98H

P5 latch

P57

P56

P55

P54

P53

P52

P51

P50

99H

OSD Attribute Register (OSAT)

9AH

OSD Character Data Register (OSDT)

9BH

OSD Address Register (OSAD)

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

9CH

OSD Default Register (OSDDEF)

A0H

(1)

P2 latch

P27

P26

P25

P24

P23

P22

P21

P20

A8H

(1)

Interrupt Enable Register 0 (IEN0)

ES1

ET1

EX1

ET0

EX0

B0H

(1)

P3 latch

P33

P32

P31

P30

B8H

(1)

Interrupt Priority Register 0 (IP0)

PS1

PT1

PX1

PT0

PX0

C0H

Interrupt Request Register 1 (IRQ1)

IQ9

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

C1H

OSD Control Register 1 (OSCON)

Split

Mesh

Mode

OSDE

C2H

OSD Vertical Start Register (OSORGV)

VP5

VP4

VP3

VP2

VP1

VP0

C3H

OSD Horizontal Start Register (OSORGH)

HP6

HP5

HP4

HP3

HP2

HP1

HP0

C4H

OSD PLL Register (OSPLL)

PLL7

PLL6

PLL5

PLL4

PLL3

PLL2

PLL1

PLL0

C5H

OSD Start Register (OSSTART)

START7 START6 START5 START4 START3 START2 START1 START0

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Notes

1. Standard 80C51 register.

2. Read only register.

C6H

Horizontal Delay Register (HDEL)

HDEL3

HDEL2

HDEL1

HDEL0

C7H

OSD FB Delay Register (OSFBD)

FBD3

FBD2

FBD1

FBD0

C8H

ADC Control Register (SAD)

#VHI

CH1

CH0

SAD3

SAD2

SAD1

SAD0

C9H

(1)

VSYNC Interrupt Register (VINT)

VLVL

CAH

ADC Control Register 2 (SAD2)

ADCE2

ADCE1

ADCE0

CFH

OSD Control Register 2 (OSCON2)

D0H

(1)

Program Status Word (PSW)

#CY

#AC

#F0

RS1

RS0

#OV

D2H

TDACL

TD7

TD6

TD5

TD4

TD3

TD2

TD1

TD0

D3H

TDACH

TPWME

TD13

TD12

TD11

TD10

TD9

TD8

D8H

Serial Control Register (S1CON)

CR2

ENS1

STA

STO

CR1

CR0

D9H

(2)

Status Register (S1STA)

SC4

SC3

SC2

SC1

SC0

DAH

Data Shift Register (S1DAT)

DBH

Slave Address Register (S1ADR)

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

DCH

(2)

Internal Status Register (S1IST)

MST4

ARL

SEL

AD0

SHRA

E0H

(1)

Accumulator (ACC)

ACC7

ACC6

ACC5

ACC4

ACC3

ACC2

ACC1

ACC0

E4H

PWM0 (7-bit PWM)

PWM0E data6

data5

data4

data3

data2

data1

data0

E5H

PWM1 (7-bit PWM)

PWM1E data6

data5

data4

data3

data2

data1

data0

E6H

PWM2 (7-bit PWM)

PWM2E data6

data5

data4

data3

data2

data1

data0

E7H

PWM3 (7-bit PWM)

PWM3E data6

data5

data4

data3

data2

data1

data0

E8H

(1)

Interrupt Enable Register 1 (IEN1)

EX9

EX7

EX6

EX5

EX4

EX3

EX2

E9H

(1)

Interrupt Polarity Register (IX1)

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

ECH

PWM4 (7-bit PWM)

PWM4E data6

data5

data4

data3

data2

data1

data0

EDH

PWM5 (7-bit PWM)

PWM5E data6

data5

data4

data3

data2

data1

data0

EEH

PWM6 (7-bit PWM)

PWM6E data6

data5

data4

data3

data2

data1

data0

EFH

PWM7 (7-bit PWM)

PWM7E data6

data5

data4

data3

data2

data1

data0

F0H

(1)

B Register (B)

F8H

Interrupt Priority Register 1 (IP1)

PX9

PX7

PX6

PX5

PX4

PX3

PX2

FFH

Watchdog timer Register (WDT)

T37

T36

T35

T34

T33

T32

T31

T30

ADDRESS

NAME

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

20 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134)

21 CHARACTERISTICS

= 4.5 to 5.5 V; V

= 0 V; T

amb

20 to 70

C; all voltages with respect to V

unless otherwise specified.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

DDX

any supply voltage

4.5

5.5

input voltage (all inputs)

0.5

+ 0.5 V

tot

total power dissipation

170

stg

storage temperature

+125

amb

operating ambient temperature

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD

digital supply voltage

4.5

5.0

5.5

DDA

analog supply voltage

4.5

5.0

5.5

DDD

digital supply current

CLK

= 12 MHz

DDA

analog supply current

CLK

= 12 MHz

5.0

programming voltage

12.5

12.75

programming current

CMOS inputs

LOW-level input voltage

0.3V

HIGH-level input voltage

0.7V

input leakage current

+10

CMOS inputs (Schmitt trigger)

LOW-level input voltage

0.2V

HIGH-level input voltage

0.8V

TTL inputs

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

TTL inputs (Schmitt trigger)

LOW-level input voltage

0.6

HIGH-level input voltage

2.4

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

21.1

DC parameters of EPROM

21.2

Programming specification for programmer

Analog inputs: ADC0 to ADC2

input voltage

Push-pull outputs: R, G, B and FB

LOW-level output current

1.6

HIGH-level output current

1.6

Open-drain outputs

t(L-H)

transition time LOW to HIGH determined by external RC

network

100

t(H-L)

transition time HIGH to LOW load independent slope

control for a capacitance
load up to 50 pF

100

O(sink)

output sink current logic 0

OL =

0.4

1.6

OL =

1.0

System clock

CLK

system clock frequency

MHz

OSD clock

OSD

OSD clock frequency

MHz

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

oper

operating temperature (programming/verification)

programming current

10.0

programming voltage

12.50

12.75

13.0

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

oper

operating temperature (programming/verification)

supply voltage (reading)

4.5

5.0

5.5

DDP

supply voltage (programming)

5.0

DDP

supply voltage (verify)

5.8

W(P)

programming pulse width per time

100

110

Nprog

number of pulses for programming

acc(byte)

accumulated programming time per byte

450

500

550

programming voltage

12.50

12.75

13.00

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

book, full pagewidth

MGM676

tOZ

High Z

tACC(OE)

VDDP

(power supply)

D0 to D7

A0 to Axx

address

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tW(P)

th(WE)

th(A)

tsu(A)

th(D)

tsu(D)

tsu(PV)

tsu(OE)

tW(OE)

VPP

(program voltage)

data out

VIH

VIL

address valid

programming

verify

data invalid

data out

Fig.48 Programming waveforms.

and V

are CMOS levels and are typically 5 V and 0 V respectively.

When OE is HIGH, P0.0 to P0.7 are used as inputs, when OE is LOW, P0.0 to P0.7 are used as outputs.

During programming the power supply must remain at 5 V. During verification the power supply must remain at 5.8 V.

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

22 PINNING CHARACTERIZATION

This chapter describes every pin used in both the SDIP42 and PLCC68 packages.

22.1

Type of packages

SDIP42: for P8XCX66

PLCC68: for Metalink+ applications

Table 91 Explanation of symbols/terms used in Table 92

Table 92 Pin characteristics

SYMBOL/TERM

MEANING

STr

Schmitt trigger

Rpu

pull-up resistor

Rpd

pull-down resistor

high-impedance

original state

the outputs keep the state they had before entering the Idle mode

PIN

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42 PLCC68

INTD

CMOS + Rpu

(1)

P5.0

I/O

CMOS

open-drain

Yes

original state

(2)

TPWM

push-pull

LOW

P5.1

I/O

CMOS

open-drain

Yes

original state

(2)

PWM0

open-drain

Yes

LOW

P5.2

I/O

CMOS

open-drain

Yes

original state

(2)

PWM1

open-drain

Yes

LOW

P5.3

I/O

CMOS

open-drain

Yes

original state

(2)

PWM2

open-drain

Yes

LOW

P5.4

I/O

CMOS

open-drain

Yes

original state

(2)

PWM3

open-drain

Yes

LOW

P5.5

I/O

CMOS

open-drain

Yes

original state

(2)

PWM4

open-drain

Yes

LOW

n.c.

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

n.c.

P5.6

I/O

CMOS

open-drain

Yes

original state

(2)

PWM5

open-drain

Yes

LOW

P5.7

I/O

CMOS

open-drain

Yes

original state

(2)

PWM6

open-drain

Yes

LOW

P3.0

I/O

CMOS + Rpu

(3)

open-drain

Yes

original state

(2)

ADC0

analog

PH1SEM

open-drain, 2 mA

note 4

S1ESEM

open-drain, 2 mA

note 4

P3.1

I/O

CMOS + Rpu

(3)

open-drain

Yes

original state

(2)

ADC1

analog

P2.0

I/O

CMOS

open-drain + Rpu

(5)

Yes

P3.2

I/O

CMOS + Rpu

(3)

open-drain

Yes

original state

(2)

ADC2

analog

P2.1

I/O

CMOS

open-drain + Rpu

(5)

Yes

P3.3

I/O

CMOS

open-drain

Yes

original state

(2)

PWM7

open-drain

Yes

LOW

P2.2

I/O

CMOS

open-drain + Rpu

(5)

Yes

P2.3

I/O

CMOS

open-drain + Rpu

(5)

Yes

P0.0

I/O

CMOS

open-drain

Yes

original state

(2)

P0.1

I/O

CMOS

open-drain

Yes

original state

(2)

P0.2

I/O

CMOS

open-drain

Yes

original state

(2)

OSD_EPR_TST

n.c.

P0.3

I/O

CMOS

open-drain

Yes

original state

(2)

P0.4

I/O

CMOS

open-drain

Yes

original state

(2)

P0.5

I/O

CMOS

open-drain

Yes

original state

(2)

P0.6

I/O

CMOS

open-drain

Yes

original state

(2)

P0.7

I/O

CMOS

open-drain

Yes

original state

(2)

DDD

SSD

PIN

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42 PLCC68

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

P2.4

I/O

CMOS

open-drain + Rpu

(5)

Yes

P2.5

I/O

CMOS

open-drain + Rpu

(5)

Yes

push-pull, 1.6 mA

note 6

LOW

(7)

SW con

push-pull, 1.6 mA

note 6

LOW

(7)

SW con

push-pull, 1.6 mA

note 6

LOW

(7)

SW con

push-pull, 1.6 mA

note 6

LOW

(7)

SW con

HSYNC

TTL STr

SW con

VSYNC

TTL STr

SW con

n.c.

DDA

P2.6

I/O

CMOS

open-drain + Rpu

(5)

Yes

12.75 V

XTALIN

CPU XTAL

XTALOUT

CPU XTAL

P2.7

I/O

CMOS

open-drain + Rpu

(5)

Yes

IDLPDEM

push-pull, 2 mA

note 4

RESET

CMOS
STr + Rpd

(8)

EMUPBX

push-pull, 2 mA

note 4

note 9

P1.0

I/O

TTL STr

open-drain + Rpu

(5)

Yes

original state

(2)

notes 9 and 10

P1.1

I/O

TTL STr

open-drain

Yes

original state

(2)

INT1

TTL STr

P1.2

I/O

TTL STr

open-drain

Yes

original state

(2)

TTL STr

n.c.

PIN

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42 PLCC68

1999

Mar

Philips Semiconductors

Product specification

Microcontrollers for P

AL/SECAM TV

with OSD and VST

P8xCx66 family

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Notes

1. A pull-up resistor must be present to prevent a floating input during normal/alternative mode when no external signal is applied to the pad.

Pull-up = present internally.

2. All ports are in input mode after reset; that means the value at the pin is determined by the external circuitry: pull-up registers Rext (and/or external

applied input).

3. A pull-up resistor must be present to prevent floating (digital) inputs if the pad is used for the analog inputs ADCO, ADCI and ADC2. This pull-up is

also present if these pins are used as port function. Pull-up is internally.

4. These pins are standard I/O cells SPF20PGD (2 mA PP slew-rate controlled).

5. A pull-up resistor must be present to prevent a floating input during nominal/alternative mode when no external signal is applied to the pad.

Pull-up = present internally.

6. Inverse of the Bp bit (located in OSCON).

7. After reset the Bp bit (located in OSCON) = 1, therefore output becomes LOW.

8. Its pull-down resistor is present internally (see Section 13.2).

9. For the SDIP42 package, pin P1.0 can be exchanged for a V

or V

, pin P1.7 for a V

10. For the PLCC68 package, pin P1.0 can be exchanged for a V

line.

11. Output is HIGH via external resistor.

n.c.

P1.3

I/O

TTL STr

open-drain

Yes

original state

(2)

INT0

TTL STr

P1.4

I/O

TTL STr

open-drain

Yes

original state

(2)

TTL STr

P1.5

I/O

TTL STr

open-drain

Yes

original state

(2)

SCL

I/O

TTL STr

open-drain

Yes

HIGH

(11)

P1.6

I/O

TTL STr

open-drain

Yes

original state

(2)

SDA

I/O

TTL STr

open-drain

Yes

HIGH

(11)

P1.7

I/O

TTL STr

open-drain + Rpu

(5)

Yes

original state

(2)

note 9

PIN

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42 PLCC68

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

23 PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

SOT188-2

detail X

(A )

Z D

Z E

pin 1 index

112E10

MO-047AC

10 mm

scale

92-11-17
95-03-11

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT

min.

max.

max. max.

(1)

4.57
4.19

0.51

3.30

0.53
0.33

0.021
0.013

1.27

0.51

2.16

0.18

0.10

0.18

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

(1)

24.33
24.13

25.27
25.02

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.020

0.13

0.25

0.01

0.05

0.020

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.958
0.950

24.33
24.13

0.958
0.950

0.995
0.985

25.27
25.02

0.995
0.985

23.62
22.61

0.930
0.890

23.62
22.61

0.930
0.890

0.085

0.032
0.026

0.048
0.042

inches

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

24 SOLDERING

24.1

Introduction

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.

24.2

Through-hole mount packages

24.2.1

OLDERING BY DIPPING OR BY SOLDER WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

24.2.2

ANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

24.3

Surface mount packages

24.3.1

EFLOW SOLDERING

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

24.3.2

AVE SOLDERING

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

24.3.3

ANUAL SOLDERING

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

24.4

Suitability of IC packages for wave, reflow and dipping soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

MOUNTING

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

DIPPING

Through-hole mount DBS, DIP, HDIP, SDIP, SIL

suitable

(2)

suitable

Surface mount

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS

not suitable

(3)

suitable

PLCC

(4)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(4)(5)

suitable

SSOP, TSSOP, VSO

not recommended

(6)

suitable

1999 Mar 10

Philips Semiconductors

Product specification

Microcontrollers for PAL/SECAM TV
with OSD and VST

P8xCx66 family

25 DEFINITIONS

26 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

27 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA62

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 489 4339/4239, Fax. +30 1 481 4240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Printed in The Netherlands

275002/750/01/pp92

Date of release: 1999 Mar 10

Document order number:

9397 750 03304

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P87C766BDR/C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P87C766BDR/C