Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

DESCRIPTION

The 89C51RB2/RC2/RD2 device contains a non-volatile
16kB/32kB/64kB Flash program memory that is both parallel
programmable and serial In-System and In-Application
Programmable. In-System Programming (ISP) allows the user to
download new code while the microcontroller sits in the application.
In-Application Programming (IAP) means that the microcontroller
fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link.
A default serial loader (boot loader) program in ROM allows serial
In-System programming of the Flash memory via the UART without
the need for a loader in the Flash code. For In-Application
Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.

This device executes one machine cycle in 6 clock cycles, hence
providing twice the speed of a conventional 80C51. An OTP
configuration bit lets the user select conventional 12 clock timing
if desired.

This device is a Single-Chip 8-Bit Microcontroller manufactured in
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The instruction set is 100% compatible with
the 80C51 instruction set.

The device also has four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt structure,
an enhanced UART and on-chip oscillator and timing circuits.

The added features of the P89C51RB2/RC2/RD2 makes it a
powerful microcontroller for applications that require pulse width
modulation, high-speed I/O and up/down counting capabilities such
as motor control.

FEATURES

80C51 Central Processing Unit

On-chip Flash Program Memory with In-System Programming
(ISP) and In-Application Programming (IAP) capability

Boot ROM contains low level Flash programming routines for
downloading via the UART

Can be programmed by the end-user application (IAP)

6 clocks per machine cycle operation (standard)

12 clocks per machine cycle operation (optional)

Speed up to 20 MHz with 6 clock cycles per machine cycle
(40 MHz equivalent performance); up to 33 MHz with 12 clocks
per machine cycle

Fully static operation

RAM expandable externally to 64 kB

4 level priority interrupt

8 interrupt sources

Four 8-bit I/O ports

Full-duplex enhanced UART

Framing error detection

Automatic address recognition

Power control modes

Clock can be stopped and resumed

Idle mode

Power down mode

Programmable clock out

Second DPTR register

Asynchronous port reset

Low EMI (inhibit ALE)

Programmable Counter Array (PCA)

PWM

Capture/compare

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

ORDERING INFORMATION

PHILIPS

(EXCEPT NORTH

AMERICA)

PHILIPS

NORTH

MEMORY

TEMPERATURE

VOLTAGE

FREQUENCY (MHz)

AMERICA)

PART ORDER

NUMBER

PART MARKING

AMERICA

PART ORDER

NUMBER

FLASH

RAM

RANGE (

AND PACKAGE

VOLTAGE

RANGE

6 CLOCK

MODE

12 CLOCK

MODE

DWG #

P89C51RB2HBP

P89C51RB2BP

16 kB

512 B

0 to +70, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RB2HFP

P89C51RB2FP

16 kB

512 B

40 to +85, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RB2HBA

P89C51RB2BA

16 kB

512 B

0 to +70, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RB2HFA

P89C51RB2FA

16 kB

512 B

40 to +85, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RB2HBB

P89C51RB2BB

16 kB

512 B

0 to +70, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

P89C51RB2HFB

P89C51RB2FB

16 kB

512 B

40 to +85, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

P89C51RC2HBP

P89C51RC2BP

32 kB

512 B

0 to +70, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RC2HFP

P89C51RC2FP

32 kB

512 B

40 to +85, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RC2HBA

P89C51RC2BA

32 kB

512 B

0 to +70, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RC2HFA

P89C51RC2FA

32 kB

512 B

40 to +85, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RC2HBB

P89C51RC2BB

32 kB

512 B

0 to +70, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

P89C51RC2HFB

P89C51RC2FB

32 kB

512 B

40 to +85, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

P89C51RD2HBP

P89C51RD2BP

64 kB

1 kB

0 to +70, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RD2HFP

P89C51RD2FP

64 kB

1 kB

40 to +85, PDIP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT129-1

P89C51RD2HBA

P89C51RD2BA

64 kB

1 kB

0 to +70, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RD2HFA

P89C51RD2FA

64 kB

1 kB

40 to +85, PLCC

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

P89C51RD2HBB

P89C51RD2BB

64 kB

1 kB

0 to +70, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

P89C51RD2HFB

P89C51RD2FB

64 kB

1 kB

40 to +85, PQFP

4.55.5 V

0 to 20 MHz

0 to 33 MHz

SOT307-2

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

LOGIC SYMBOL

POR

ADDRESS AND

DATA BUS

ADDRESS BUS

T2EX

RxD

TxD

INT0

INT1

T0
T1

SECONDAR

FUNCTIONS

RST

EA/V

PSEN

ALE/PROG

XTAL1

XTAL2

SU01302

PINNING

Plastic Dual In-Line Package

T2/P1.0

T2EX/P1.1

ECI/P1.2

CEX0/P1.3

CEX1/P1.4

CEX2/P1.5

CEX3/P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

CEX4/P1.7

WR/P3.6

RD/P3.7

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

DUAL

IN-LINE

PACKAGE

SU00021

Plastic Leaded Chip Carrier

LCC

Pin

Function

NIC*

P1.0/T2

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

Pin

Function

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

Pin

Function

P2.7/A15

PSEN

ALE/PROG

NIC*

EA/V

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SU00023

* NO INTERNAL CONNECTION

Plastic Quad Flat Pack

PQFP

Pin

Function

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

Pin

Function

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

NIC*

EA/V

P0.7/AD7

Pin

Function

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

NIC*

P1.0/T2

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

SU00024

* NO INTERNAL CONNECTION

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

PIN DESCRIPTIONS

MNEMONIC

PIN NUMBER

TYPE

NAME AND FUNCTION

MNEMONIC

PDIP

PLCC

PQFP

TYPE

NAME AND FUNCTION

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.

P0.00.7

3932

4336

3730

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program

and data memory. In this application, it uses strong internal pull-ups when emitting 1s.

P1.0P1.7

4044,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins
except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them
are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1
pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I

Alternate functions for 89C51RB2/RC2/RD2 Port 1 include:

I/O

T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable
Clock-Out)

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

ECI (P1.2): External Clock Input to the PCA

I/O

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

I/O

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

I/O

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

I/O

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

I/O

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P2.0P2.7

2128

2431

1825

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I

). Port 2

emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri),
port 2 emits the contents of the P2 special function register.

P3.0P3.7

1017

11,

1319

5, 713

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: I

). Port 3 also serves

the special features of the 89C51RB2/RC2/RD2, as listed below:

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V

permits a power-on reset

using only an external capacitor to V

ALE

Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted twice
every machine cycle, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory. ALE can be
disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a
MOVX instruction.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

MNEMONIC

NAME AND FUNCTION

TYPE

PIN NUMBER

MNEMONIC

NAME AND FUNCTION

TYPE

PQFP

PLCC

PDIP

PSEN

Program Store Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations. If EA is held high, the device executes from internal program memory.
The value on the EA pin is latched when RST is released and any subsequent
changes have no effect. This pin also receives the programming supply voltage
(V

) during Flash programming.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:
To avoid "latch-up" effect at power-on, the voltage on any pin (other than V

) must not be higher than V

+ 0.5 V or less than V

0.5 V.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Table 1.

Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

MSB

LSB

RESET
VALUE

ACC*

Accumulator

E0H

00H

AUXR#

Auxiliary

8EH

EXTRAM

xxxxxx10B

AUXR1#

Auxiliary 1

A2H

ENBOOT

GF2

DPS

xxxxxxx0B

B register

F0H

00H

CCAP0H#

Module 0 Capture High

FAH

xxxxxxxxB

CCAP1H#

Module 1 Capture High

FBH

xxxxxxxxB

CCAP2H#

Module 2 Capture High

FCH

xxxxxxxxB

CCAP3H#

Module 3 Capture High

FDH

xxxxxxxxB

CCAP4H#

Module 4 Capture High

FEH

xxxxxxxxB

CCAP0L#

Module 0 Capture Low

EAH

xxxxxxxxB

CCAP1L#

Module 1 Capture Low

EBH

xxxxxxxxB

CCAP2L#

Module 2 Capture Low

ECH

xxxxxxxxB

CCAP3L#

Module 3 Capture Low

EDH

xxxxxxxxB

CCAP4L#

Module 4 Capture Low

EEH

xxxxxxxxB

CCAPM0#

Module 0 Mode

DAH

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

CCAPM1#

Module 1 Mode

DBH

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

CCAPM2#

Module 2 Mode

DCH

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

CCAPM3#

Module 3 Mode

DDH

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

CCAPM4#

Module 4 Mode

DEH

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

CCON*#

PCA Counter Control

D8H

CCF4

CCF3

CCF2

CCF1

CCF0

00x00000B

CH#

PCA Counter High

F9H

00H

CL#

PCA Counter Low

E9H

00H

CMOD#

PCA Counter Mode

D9H

CIDL

WDTE

CPS1

CPS0

ECF

00xxx000B

DPTR:

Data Pointer (2 bytes)

DPH

Data Pointer High

83H

00H

DPL

Data Pointer Low

82H

00H

IE*

Interrupt Enable 0

A8H

ET2

ET1

EX1

ET0

EX0

00H

IP*

Interrupt Priority

B8H

PPC

PT2

PT1

PX1

PT0

PX0

x0000000B

IPH#

Interrupt Priority High

B7H

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

x0000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*

Port 1

90H

CEX4

CEX3

CEX2

CEX1

CEX0

ECI

T2EX

FFH

P2*

Port 2

A0H

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

FFH

P3*

Port 3

B0H

INT1

INT0

TxD

RxD

FFH

PCON#

Power Control

87H

SMOD1

SMOD0

GF1

GF0

IDL

00xxx000B

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

1. Reset value depends on reset source.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Table 1.

Special Function Registers (Continued)

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

MSB

LSB

RESET
VALUE

PSW*

Program Status Word

D0H

RS1

RS0

00000000B

RCAP2H

Timer 2 Capture High

CBH

00H

RCAP2L

Timer 2 Capture Low

CAH

00H

SADDR#

Slave Address

A9H

00H

SADEN#

Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

SCON*

Serial Control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00H

Stack Pointer

81H

07H

TCON*

Timer Control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

T2CON*

Timer 2 Control

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

00H

T2MOD#

Timer 2 Mode Control

C9H

T2OE

DCEN

xxxxxx00B

TH0

Timer High 0

8CH

00H

TH1

Timer High 1

8DH

00H

TH2#

Timer High 2

CDH

00H

TL0

Timer Low 0

8AH

00H

TL1

Timer Low 1

8BH

00H

TL2#

Timer Low 2

CCH

00H

TMOD

Timer Mode

89H

GATE

C/T

GATE

C/T

00H

WDTRST

Watchdog Timer Reset

A6H

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.

To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. Minimum and maximum
high and low times specified in the data sheet must be observed.

This device is configured at the factory to operate using 6 clock
periods per machine cycle, referred to in this datasheet as "6 clock
mode". (This yields performance equivalent to twice that of standard
80C51 family devices). It may be optionally configured on
commercially-available EPROM programming equipment to operate
at 12 clocks per machine cycle, referred to in this datasheet as
"12 clock mode". Once 12 clock mode has been configured, it
cannot be changed back to 6 clock mode.

RESET

A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator
periods in 12 clock mode), while the oscillator is running. To ensure a
good power-on reset, the RST pin must be high long enough to allow
the oscillator time to start up (normally a few milliseconds) plus two
machine cycles. At power-on, the voltage on V

and RST must

come up at the same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a voltage
above V

IH1

(min.) is applied to RESET.

The value on the EA pin is latched when RST is deasserted and has
no further effect.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

LOW POWER MODES
Stop Clock Mode

The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.

Idle Mode

In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return V

the minimum specified operating voltages before the Power Down
Mode is terminated.

Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.

To properly terminate Power Down, the reset or external interrupt
should not be executed before V

is restored to its normal

operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).

With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.

POWER OFF FLAG

The Power Off Flag (POF) is set by on-chip circuitry when the V

level on the 89C51RB2/RC2/RD2 rises from 0 to 5 V. The POF bit
can be set or cleared by software allowing a user to determine if the
reset is the result of a power-on or a warm start after powerdown.
The V

level must remain above 3 V for the POF to remain

unaffected by the V

level.

Design Consideration

When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.

ONCE

Mode

The ONCE ("On-Circuit Emulation") Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.

Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:

1. to input the external clock for Timer/Counter 2, or

2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at

a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode).

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:

Oscillator Frequency

(65536

RCAP2H, RCAP2L)

n =

2 in 6 clock mode
4 in 12 clock mode

Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.

Table 2.

External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.

Capture Mode

In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/6 pulses
(osc/12 in 12 clock mode).).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter [C/T2* in T2CON]) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down

Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.

Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.

If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.

In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16-bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows.
This EXF2 bit can be used as a 17th bit of resolution if needed. The
EXF2 flag does not generate an interrupt in this mode of operation.

(MSB)

(LSB)

Symbol

Position

Name and Significance

TF2

T2CON.7

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.

EXF2

T2CON.6

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).

RCLK

T2CON.5

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK

T2CON.4

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2

T2CON.3

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.

TR2

T2CON.2

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

T2CON.1

Timer or counter select. (Timer 2)

0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 in 12 clock mode)
1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

SU01251

Figure 1. Timer/Counter 2 (T2CON) Control Register

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Table 3.

Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

TR2

MODE

16-bit Auto-reload

16-bit Capture

Baud rate generator

(off)

OSC

C/T2 = 0

C/T2 = 1

TR2

Control

TL2

(8-bits)

TH2

(8-bits)

TF2

RCAP2L

RCAP2H

EXEN2

Control

EXF2

Timer 2

Interrupt

T2EX Pin

Transition

Detector

T2 Pin

Capture

SU01252

* n = 6 in 6 clock mode, or 12 in 12 clock mode.

Figure 2. Timer 2 in Capture Mode

Not Bit Addressable

Symbol

Function

Not implemented, reserved for future use.*

T2OE

Timer 2 Output Enable bit.

DCEN

Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

T2OE

DCEN

SU00729

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.

Bit

T2MOD

Address = 0C9H

Reset Value = XXXX XX00B

Figure 3. Timer 2 Mode (T2MOD) Control Register

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

OSC

C/T2 = 0

C/T2 = 1

TR2

Control

TL2

(8-bits)

TH2

(8-bits)

RCAP2L

RCAP2H

EXEN2

Control

EXF2

Timer 2

Interrupt

T2EX Pin

Transition

Detector

T2 Pin

Reload

"0"

"1"

RX Clock

TX Clock

"0"

"1"

"0"

"1"

Timer 1

Overflow

Note availability of additional external interrupt.

SMOD

RCLK

TCLK

SU01213

Figure 6. Timer 2 in Baud Rate Generator Mode

Table 4.

Timer 2 Generated Commonly Used
Baud Rates

Baud Rate

Timer 2

12 clock

mode

6 clock

mode

Osc Freq

RCAP2H

RCAP2L

375 k

750 k

12 MHz

9.6 k

19.2 k

12 MHz

2.8 k

5.6 k

12 MHz

2.4 k

4.8 k

12 MHz

1.2 k

2.4 k

12 MHz

300

600

12 MHz

110

220

12 MHz

300

600

6 MHz

110

220

6 MHz

Baud Rate Generator Mode

Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates one generated by
Timer 1, the other by Timer 2.

Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode,in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value
in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2's
overflow rate given below:

Modes 1 and 3 Baud Rates

Timer 2 Overflow Rate

The timer can be configured for either "timer" or "counter" operation.
In many applications, it is configured for "timer" operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.

Usually, as a timer it would increment every machine cycle (i.e.,

the oscillator frequency in 6 clock mode,

the oscillator

frequency in 12 clock mode). As a baud rate generator, it increments
at the oscillator frequency in 6 clock mode (

OSC

in 12 clock mode).

Thus the baud rate formula is as follows:

Oscillator Frequency

[ n *

[65536

(RCAP2H, RCAP2L)]]

Modes 1 and 3 Baud Rates =

* n =

16 in 6 clock mode
32 in 12 clock mode

Where:

(RCAP2H, RCAP2L)= The content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

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1999 Sep 23

When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.

Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.

Summary of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:

Baud Rate

Timer 2 Overflow Rate

If Timer 2 is being clocked internally, the baud rate is:

Baud Rate

OSC

[ n *

[65536

(RCAP2H, RCAP2L)]]

* n =

16 in 6 clock mode
32 in 12 clock mode

Where f

OSC

= Oscillator Frequency

To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:

RCAP2H, RCAP2L

65536

OSC

n *

Baud Rate

Timer/Counter 2 Set-up

Except for the baud rate generator mode, the values given for T2CON
do not include the setting of the TR2 bit. Therefore, bit TR2 must be
set, separately, to turn the timer on. see Table 5 for set-up of Timer 2
as a timer. Also see Table 6 for set-up of Timer 2 as a counter.

Table 5.

Timer 2 as a Timer

T2CON

MODE

INTERNAL CONTROL

(Note 1)

EXTERNAL CONTROL

(Note 2)

16-bit Auto-Reload

00H

08H

16-bit Capture

01H

09H

Baud rate generator receive and transmit same baud rate

34H

36H

Receive only

24H

26H

Transmit only

14H

16H

Table 6.

Timer 2 as a Counter

TMOD

MODE

INTERNAL CONTROL

(Note 1)

EXTERNAL CONTROL

(Note 2)

16-bit

02H

0AH

Auto-Reload

03H

0BH

NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

generator mode.

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Preliminary specification

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89C51RD2

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16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Enhanced UART

The UART operates in all of the usual modes that are described in
the first section of

Data Handbook IC20, 80C51-Based 8-Bit

Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.

When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.

Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the "Given"
address or the "Broadcast" address. The 9-bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave's address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are "don't care". The SADEN
mask can be logically ANDed with the SADDR to create the "Given"
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:

Slave 0

SADDR

1100 0000

SADEN

1111 1101

Given

1100 00X0

Slave 1

SADDR

1100 0000

SADEN

1111 1110

Given

1100 000X

In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.

In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:

Slave 0

SADDR

1100 0000

SADEN

1111 1001

Given

1100 0XX0

Slave 1

SADDR

1110 0000

SADEN

1111 1010

Given

1110 0X0X

Slave 2

SADDR

1110 0000

SADEN

1111 1100

Given

1110 00XX

In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don't-cares. In most cases, interpreting the don't-cares as ones,
the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all "don't cares" as well as a Broadcast address of all "don't
cares". This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

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1999 Sep 23

SCON Address = 98H

Reset Value = 0000 0000B

SM0/FE

SM1

SM2

REN

TB8

RB8

Bit Addressable

(SMOD0 = 0/1)*

Symbol

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

SM1

Serial Port Mode Bit 1
SM0

SM1

Mode

Description

Baud Rate**

shift register

OSC

/6 (6 clock mode) or f

OSC

/12 (12 clock mode)

8-bit UART

variable

9-bit UART

OSC

/32 or f

OSC

/16 (6 clock mode) or

OSC

/64 or f

OSC

/32 (12 clock mode)

9-bit UART

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

RB8

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:
*SMOD0 is located at PCON6.
**f

OSC

= oscillator frequency

SU01255

Bit:

Figure 7. SCON: Serial Port Control Register

Philips Semiconductors

Preliminary specification

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89C51RD2

80C51 8-bit Flash microcontroller family

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1999 Sep 23

Interrupt Priority Structure

The 89C51RB2/RC2/RD2 has an 8 source four-level interrupt
structure (see Table 7).

There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.

The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1

Level 2

Level 3 (highest priority)

The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

IE0

N (L)

Y (T)

03H

TP0

0BH

IE1

N (L)

Y (T)

13H

TF1

1BH

PCA

CF, CCFn

n = 04

33H

RI, TI

23H

TF2, EXF2

2BH

NOTES:
1. L = Level activated
2. T = Transition activated

EX0

IE (0A8H)

Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.

BIT

SYMBOL

FUNCTION

IE.7

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.

IE.6

PCA interrupt enable bit

IE.5

ET2

Timer 2 interrupt enable bit.

IE.4

Serial Port interrupt enable bit.

IE.3

ET1

Timer 1 interrupt enable bit.

IE.2

EX1

External interrupt 1 enable bit.

IE.1

ET0

Timer 0 interrupt enable bit.

IE.0

EX0

External interrupt 0 enable bit.

SU01290

ET0

EX1

ET1

ET2

Figure 10. IE Registers

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89C51RD2

80C51 8-bit Flash microcontroller family

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1999 Sep 23

PX0

IP (0B8H)

Priority Bit = 1 assigns high priority
Priority Bit = 0 assigns low priority

BIT

SYMBOL

FUNCTION

IP.7

IP.6

PPC

PCA interrupt priority bit

IP.5

PT2

Timer 2 interrupt priority bit.

IP.4

Serial Port interrupt priority bit.

IP.3

PT1

Timer 1 interrupt priority bit.

IP.2

PX1

External interrupt 1 priority bit.

IP.1

PT0

Timer 0 interrupt priority bit.

IP.0

PX0

External interrupt 0 priority bit.

SU01291

PT0

PX1

PT1

PT2

PPC

Figure 11. IP Registers

PX0H

IPH (B7H)

Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority

BIT

SYMBOL

FUNCTION

IPH.7

IPH.6

PPCH

PCA interrupt priority bit

IPH.5

PT2H

Timer 2 interrupt priority bit high.

IPH.4

PSH

Serial Port interrupt priority bit high.

IPH.3

PT1H

Timer 1 interrupt priority bit high.

IPH.2

PX1H

External interrupt 1 priority bit high.

IPH.1

PT0H

Timer 0 interrupt priority bit high.

IPH.0

PX0H

External interrupt 0 priority bit high.

SU01292

PT0H

PX1H

PT1H

PSH

PT2H

PPCH

Figure 12. IPH Registers

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.

Reduced EMI Mode

AUXR (8EH)

EXTRAM

AUXR.1

EXTRAM

AUXR.0

Turns off ALE output.

Dual DPTR

The dual DPTR structure (see Figure 13) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.

New Register Name: AUXR1#

SFR Address: A2H

Reset Value: xxxxxxx0B

AUXR1 (A2H)

ENBOOT

GF2

DPS

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg

DPS

DPTR0

DPTR1

The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.

The GF2 bit is a general purpose user-defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to

be quickly toggled simply by executing an INC AUXR1 instruction
without affecting the GF2 bit.

The ENBOOT bit determines whether the BOOTROM is enabled
or disabled. This bit will automatically be set if the status byte is
non zero during reset or PSEN is pulled low, ALE floats high, and
EA > V

on the falling edge of reset. Otherwise, this bit will be

cleared during reset.

DPS

DPTR1

DPTR0

DPH

(83H)

DPL

(82H)

EXTERNAL

DATA

MEMORY

SU00745A

BIT0

AUXR1

Figure 13.

DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:

INC DPTR

Increments the data pointer by 1

MOV DPTR, #data16

Loads the DPTR with a 16-bit constant

MOV A, @ A+DPTR

Move code byte relative to DPTR to ACC

MOVX A, @ DPTR

Move external RAM (16-bit address) to
ACC

MOVX @ DPTR , A

Move ACC to external RAM (16-bit
address)

JMP @ A + DPTR

Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See

Application Note AN458 for more details.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Programmable Counter Array (PCA)

The Programmable Counter Array available on the
89C51RB2/RC2/RD2 is a special 16-bit Timer that has five 16-bit
capture/compare modules associated with it. Each of the modules
can be programmed to operate in one of four modes: rising and/or
falling edge capture, software timer, high-speed output, or pulse
width modulator. Each module has a pin associated with it in port 1.
Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc.
The basic PCA configuration is shown in Figure 14.

The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/6 the oscillator frequency, 1/2 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 17):

CPS1 CPS0 PCA Timer Count Source

1/6 oscillator frequency (6 clock mode);
1/12 oscillator frequency (12 clock mode)

1/2 oscillator frequency (6 clock mode);
1/4 oscillator frequency (12 clock mode)

Timer 0 overflow

External Input at ECI pin

In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 15.

The watchdog timer function is implemented in module 4 (see
Figure 24).

The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 18).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when

the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 16.

Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 19). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module's capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module's capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the positive
edge. If both bits are set both edges will be enabled and a capture will
occur for either transition. The last bit in the register ECOM
(CCAPMn.6) when set enables the comparator function. Figure 20
shows the CCAPMn settings for the various PCA functions.

There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.

MODULE FUNCTIONS:

16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)

MODULE 0

MODULE 1

MODULE 2

MODULE 3

MODULE 4

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

16 BITS

PCA TIMER/COUNTER

TIME BASE FOR PCA MODULES

16 BITS

SU00032

Figure 14. Programmable Counter Array (PCA)

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

CMOD Address = C1H

Reset Value = 00XX X000B

CIDL

WDTE

CPS1

CPS0

ECF

Bit:

Symbol

Function

CIDL

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.

WDTE

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.

Not implemented, reserved for future use.*

CPS1

PCA Count Pulse Select bit 1.

CPS0

PCA Count Pulse Select bit 0.
CPS1

CPS0

Selected PCA Input**

Internal clock, f

OSC

/6 in 6 clock mode (f

OSC

/12 in 12 clock mode)

Internal clock, f

OSC

/2 in 6 clock mode (f

OSC

/4 in 12 clock mode)

Timer 0 overflow

External clock at ECI/P1.2 pin

(max. rate = f

OSC

/4 in 6 clock mode, f

OCS

/8 in 12 clock mode)

ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.

NOTE:
*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

** f

OSC

= oscillator frequency

SU01257

Figure 17. CMOD: PCA Counter Mode Register

CCON Address = 0C0H

Reset Value = 00X0 0000B

CCF4

CCF3

CCF2

CCF1

CCF0

Bit Addressable

Bit:

Symbol

Function

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.

Not implemented, reserved for future use*.

CCF4

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

CCF3

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

CCF2

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

CCF1

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

CCF0

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

NOTE:
*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01099

Figure 18. CCON: PCA Counter Control Register

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

CCAPMn Address

CCAPM0

0C2H

CCAPM1

0C3H

CCAPM2

0C4H

CCAPM3

0C5H

CCAPM4

0C6H

Reset Value = X000 0000B

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Not Bit Addressable

Bit:

Symbol

Function

Not implemented, reserved for future use*.

ECOMn

Enable Comparator. ECOMn = 1 enables the comparator function.

CAPPn

Capture Positive, CAPPn = 1 enables positive edge capture.

CAPNn

Capture Negative, CAPNn = 1 enables negative edge capture.

MATn

Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit
in CCON to be set, flagging an interrupt.

TOGn

Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn
pin to toggle.

PWMn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.

ECCFn

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01100

Figure 19. CCAPMn: PCA Modules Compare/Capture Registers

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

MODULE FUNCTION

No operation

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative trigger on CEXn

16-bit capture by a transition on CEXn

16-bit Software Timer

16-bit High Speed Output

8-bit PWM

Watchdog Timer

Figure 20. PCA Module Modes (CCAPMn Register)

PCA Capture Mode
To use one of the PCA modules in the capture mode either one or
both of the CCAPM bits CAPN and CAPP for that module must be
set. The external CEX input for the module (on port 1) is sampled for
a transition. When a valid transition occurs the PCA hardware loads
the value of the PCA counter registers (CH and CL) into the
module's capture registers (CCAPnL and CCAPnH). If the CCFn bit
for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated. Refer to Figure 21.

16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the modules CCAPMn register. The PCA
timer will be compared to the module's capture registers and when a
match occurs an interrupt will occur if the CCFn (CCON SFR) and
the ECCFn (CCAPMn SFR) bits for the module are both set (see
Figure 22).

High Speed Output Mode
In this mode the CEX output (on port 1) associated with the PCA
module will toggle each time a match occurs between the PCA

counter and the module's capture registers. To activate this mode
the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must
be set (see Figure 23).

Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 24
shows the PWM function. The frequency of the output depends on
the source for the PCA timer. All of the modules will have the same
frequency of output because they all share the PCA timer. The duty
cycle of each module is independently variable using the module's
capture register CCAPLn. When the value of the PCA CL SFR is
less than the value in the module's CCAPLn SFR the output will be
low, when it is equal to or greater than the output will be high. When
CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. the allows updating the PWM without glitches. The PWM
and ECOM bits in the module's CCAPMn register must be set to
enable the PWM mode.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

CCAPM4
(C6H)

CCAP4H

CCAP4L

RESET

PCA TIMER/COUNTER

16BIT COMPARATOR

MATCH

ENABLE

WRITE TO
CCAP4L

RESET

WRITE TO
CCAP4H

CMOD
(C1H)

CIDL

WDTE

CPS1

CPS0

ECF

SU01105

MODULE 4

Figure 25. PCA Watchdog Timer m(Module 4 only)

PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the
reliability of the system without increasing chip count. Watchdog
timers are useful for systems that are susceptible to noise, power
glitches, or electrostatic discharge. Module 4 is the only PCA module
that can be programmed as a watchdog. However, this module can
still be used for other modes if the watchdog is not needed.

Figure 25 shows a diagram of how the watchdog works. The user
pre-loads a 16-bit value in the compare registers. Just like the other
compare modes, this 16-bit value is compared to the PCA timer
value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:
1. periodically change the compare value so it will never match the

PCA timer,

2. periodically change the PCA timer value so it will never match

the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it.

The first two options are more reliable because the watchdog
timer is never disabled as in option #3. If the program counter ever
goes astray, a match will eventually occur and cause an internal
reset. The second option is also not recommended if other PCA
modules are being used. Remember, the PCA timer is the time
base for all modules; changing the time base for other modules
would not be a good idea. Thus, in most applications the first
solution is the best option.

Figure 26 shows the code for initializing the watchdog timer.
Module 4 can be configured in either compare mode, and the WDTE
bit in CMOD must also be set. The user's software then must
periodically change (CCAP4H,CCAP4L) to keep a match from
occurring with the PCA timer (CH,CL). This code is given in the
WATCHDOG routine in Figure 26.

This routine should not be part of an interrupt service routine,
because if the program counter goes astray and gets stuck in an
infinite loop, interrupts will still be serviced and the watchdog will
keep getting reset. Thus, the purpose of the watchdog would be
defeated. Instead, call this subroutine from the main program within
2

count of the PCA timer.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Expanded Data RAM Addressing

The 89C51RB2/RC2/RD2 has internal data memory that is mapped
into four separate segments: the lower 128 bytes of RAM, upper 128
bytes of RAM, 128 bytes Special Function Register (SFR), and
256 bytes expanded RAM (ERAM) (768 bytes for the RD2).

The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

4. The 256/768-bytes expanded RAM (ERAM, 00H 1FFH/2FFH)

are indirectly accessed by move external instruction, MOVX, and
with the EXTRAM bit cleared, see Figure 27.

The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.

When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:

MOV 0A0H,#data

accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.

For example:

MOV @R0,#data

where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).

The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 7936-bytes of external
data memory.

With EXTRAM = 0, the ERAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external
addressing. For example, with EXTRAM = 0,

MOVX @R0,#data

where R0 contains 0A0H, access the ERAM at address 0A0H rather
than external memory. An access to external data memory locations
higher than the ERAM will be performed with the MOVX DPTR
instructions in the same way as in the standard 80C51, so with P0
and P2 as data/address bus, and P3.6 and P3.7 as write and read
timing signals. Refer to Figure 28.

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.

AUXR

Reset Value = xxxx xx00B

EXTRAM

Not Bit Addressable

Bit:

Symbol

Function

Disable/Enable ALE

Operating Mode

ALE is emitted at a constant rate of

the oscillator frequency (6 clock mode;

OSC

in 12 clock mode).

ALE is active only during a MOVX or MOVC instruction.

EXTRAM

Internal/External RAM access using MOVX @Ri/@DPTR

EXTRAM

Operating Mode

Internal ERAM access using MOVX @Ri/@DPTR

External data memory access.

Not implemented, reserved for future use*.

SU01258

Address = 8EH

Figure 27. AUXR: Auxiliary Register

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

ERAM

256 or 768 BYTES

UPPER

128 BYTES

INTERNAL RAM

LOWER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION
REGISTER

100

EXTERNAL

DATA

MEMORY

FFFF

0000

SU01293

Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0

HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 89C51RB2/RC2/RD2)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit
counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in
sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and
there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an
output reset HIGH pulse at the RST-pin (see the note below).

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to
service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this
will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset
the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only
register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin (see note
below). The RESET pulse duration is 98

OSC

(6 clock mode; 196 in 12 clock mode), where T

OSC

= 1/f

OSC

. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER

RATING

UNIT

Operating temperature under bias

0 to +70 or 40 to +85

Storage temperature range

65 to +150

Voltage on EA/V

pin to V

0 to +13.0

Voltage on any other pin to V

0.5 to +6.5

Maximum I

per I/O pin

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise noted.

4. Programming is guaranteed from 0

C to T

max

for all devices.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

DC ELECTRICAL CHARACTERISTICS

amb

= 0

C to +70

C or 40

C to +85

C; 5 V

10%; V

= 0 V

SYMBOL

PARAMETER

TEST

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Input low voltage

4.5 V < V

< 5.5 V

0.5

0.2V

0.1

Input high voltage (ports 0, 1, 2, 3, EA)

0.2V

+0.9

+0.5

IH1

Input high voltage, XTAL1, RST

0.7V

+0.5

Output low voltage, ports 1, 2, 3

= 4.5 V

= 1.6 mA

0.4

OL1

Output low voltage, port 0, ALE, PSEN

7, 8

= 4.5 V

= 3.2 mA

0.4

Output high voltage, ports 1, 2, 3

= 4.5 V

= 30

0.7

OH1

Output high voltage (port 0 in external bus mode),
ALE

, PSEN

= 4.5 V

= 3.2 mA

0.7

Logical 0 input current, ports 1, 2, 3

= 0.4 V

Logical 1-to-0 transition current, ports 1, 2, 3

= 2.0 V

See Note 4

650

Input leakage current, port 0

0.45 < V

< V

0.3

Power supply current (see Figure 36):

See Note 5

Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see

42 f

diti

)

amb

= 0

C to 70

< 1

Figure 42 for conditions)

amb

= 40

C to +85

RST

Internal reset pull-down resistor

225

Pin capacitance

(except EA)

NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

s of ALE and ports 1 and 3. The noise is due

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these conditions provided that no

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the V

0.7 specification when the

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V

is approximately 2 V.

5. See Figures 39 through 42 for I

test conditions and Figure 36 for I

vs Freq.

Active mode:

CC(MAX)

= (1.8

FREQ. + 20)mA for all devices, in 6 clock mode; (0.9

FREQ. + 20)mA in 12 clock mode.

Idle mode:

CC(MAX)

= (0.7

FREQ. +1.0)mA in 6 clock mode; (0.35

FREQ. +1.0)mA in 12 clock mode.

6. This value applies to T

amb

= 0

C to +70

7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

15 mA (*NOTE: This is 85

C specification.)

Maximum I

per 8-bit port:

26 mA

Maximum total I

for all outputs:

71 mA

If I

exceeds the test condition, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

test conditions.

9. ALE is tested to V

OH1

, except when ALE is off then V

is the voltage specification.

10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF

(except EA is 25 pF).

11. Programming is guaranteed from 0

C to T

max

for all devices.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5 V

10%, V

= 0V

1, 2, 3

VARIABLE CLOCK

20 MHz CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

0.5t

CLCL

LLAX

Address hold after ALE low

0.5t

CLCL

LLIV

ALE low to valid instruction in

CLCL

LLPL

ALE low to PSEN low

0.5t

CLCL

PLPH

PSEN pulse width

1.5t

CLCL

PLIV

PSEN low to valid instruction in

1.5t

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

0.5t

CLCL

AVIV

Address to valid instruction in

2.5t

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

30, 31

RD pulse width

CLCL

100

WLWH

30, 31

WR pulse width

CLCL

100

RLDV

30, 31

RD low to valid data in

2.5t

CLCL

RHDX

30, 31

Data hold after RD

RHDZ

30, 31

Data float after RD

CLCL

LLDV

30, 31

ALE low to valid data in

CLCL

150

AVDV

30, 31

Address to valid data in

4.5t

CLCL

165

LLWL

30, 31

ALE low to RD or WR low

1.5t

CLCL

1.5t

CLCL

+50

125

AVWL

30, 31

Address valid to WR low or RD low

CLCL

QVWX

30, 31

Data valid to WR transition

0.5t

CLCL

WHQX

30, 31

Data hold after WR

0.5t

CLCL

QVWH

Data valid to WR high

3.5t

CLCL

130

RLAZ

30, 31

RD low to address float

WHLH

30, 31

RD or WR high to ALE high

0.5t

CLCL

0.5t

CLCL

+20

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

Shift Register

XLXL

Serial port clock cycle time

CLCL

300

QVXH

Output data setup to clock rising edge

CLCL

133

117

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

CLCL

133

117

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE)

amb

= 0

C to +70

C or 40

C to +85

C, V

= 5 V

10%, V

= 0 V

1, 2, 3

VARIABLE CLOCK

33 MHz CLOCK

SYMBOL

FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1/t

CLCL

Oscillator frequency

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instruction in

CLCL

LLPL

ALE low to PSEN low

CLCL

PLPH

PSEN pulse width

CLCL

PLIV

PSEN low to valid instruction in

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

CLCL

AVIV

Address to valid instruction in

CLCL

PLAZ

PSEN low to address float

Data Memory

RLRH

30, 31

RD pulse width

CLCL

100

WLWH

30, 31

WR pulse width

CLCL

100

RLDV

30, 31

RD low to valid data in

CLCL

RHDX

30, 31

Data hold after RD

RHDZ

30, 31

Data float after RD

CLCL

LLDV

30, 31

ALE low to valid data in

CLCL

150

AVDV

30, 31

Address to valid data in

CLCL

165

105

LLWL

30, 31

ALE low to RD or WR low

CLCL

+50

140

AVWL

30, 31

Address valid to WR low or RD low

CLCL

QVWX

30, 31

Data valid to WR transition

CLCL

WHQX

30, 31

Data hold after WR

CLCL

QVWH

Data valid to WR high

CLCL

130

RLAZ

30, 31

RD low to address float

WHLH

30, 31

RD or WR high to ALE high

CLCL

+25

External Clock

CHCX

High time

CLCL

CLCX

Low time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall time

Shift Register

XLXL

Serial port clock cycle time

12t

CLCL

360

QVXH

Output data setup to clock rising edge

10t

CLCL

133

167

XHQX

Output data hold after clock rising edge

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

10t

CLCL

133

167

Port 0 drivers.

4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always
`t' (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A Address
C Clock
D Input data
H Logic level high
I Instruction (program memory contents)
L Logic level low, or ALE

P PSEN
Q Output data
R RD signal
t Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
Examples: t

AVLL

= Time for address valid to ALE low.

LLPL

= Time for ALE low to PSEN low.

PXIZ

ALE

PSEN

PORT 0

PORT 2

A0A15

A8A15

A0A7

AVLL

PXIX

LLAX

INSTR IN

LHLL

PLPH

LLIV

PLAZ

LLPL

AVIV

SU00006

PLIV

Figure 29. External Program Memory Read Cycle

ALE

PSEN

PORT 0

PORT 2

A0A7

FROM RI OR DPL

DATA IN

A0A7 FROM PCL

INSTR IN

P2.0P2.7 OR A8A15 FROM DPF

A0A15 FROM PCH

WHLH

LLDV

LLWL

RLRH

LLAX

RLAZ

AVLL

RHDX

RHDZ

AVWL

AVDV

RLDV

SU00025

Figure 30. External Data Memory Read Cycle

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

VCC0.5

0.45V

0.2VCC+0.9

0.2VCC0.1

NOTE:
AC inputs during testing are driven at V

0.5 for a logic `1' and 0.45V for a logic `0'.

Timing measurements are made at V

min for a logic `1' and V

max for a logic `0'.

SU00717

Figure 34. AC Testing Input/Output

VLOAD

VLOAD+0.1V

VLOAD0.1V

VOH0.1V

VOL+0.1V

NOTE:

TIMING

REFERENCE

POINTS

For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
V

level occurs. I

20mA.

SU00718

Figure 35. Float Waveform

Frequency at XTAL1 (MHz, 6 clock mode)

(mA)

89C51RB2/RC2/RD2

MAXIMUM ACTIVE I

TYPICAL ACTIVE I

MAXIMUM IDLE

TYPICAL IDLE

SU01300

Figure 36. I

vs. FREQ

Valid only within frequency specifications of the device under test

VCC0.5

0.45V

0.2VCC+0.9

0.2VCC0.1

NOTE:
AC inputs during testing are driven at V

0.5 for a logic `1' and 0.45V for a logic `0'.

Timing measurements are made at V

min for a logic `1' and V

max for a logic `0'.

SU00010

Figure 37. AC Testing Input/Output

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

VLOAD

VLOAD+0.1V

VLOAD0.1V

VOH0.1V

VOL+0.1V

NOTE:

TIMING

REFERENCE

POINTS

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V

level occurs. I

20mA.

SU00011

Figure 38. Float Waveform

RST

XTAL1

XTAL2

(NC)

CLOCK SIGNAL

89C51RB2
89C51RC2
89C51RD2

SU01294

Figure 39. I

Test Condition, Active Mode.

All other pins are disconnected

RST

XTAL1

XTAL2

(NC)

CLOCK SIGNAL

SU01295

89C51RB2
89C51RC2
89C51RD2

Figure 40. I

Test Condition, Idle Mode.

All other pins are disconnected

VCC0.5

0.5V

CHCL

CLCL

CLCH

CLCX

CHCX

SU01297

Figure 41. Clock Signal Waveform for I

Tests in Active

and Idle Modes.

CLCL

= t

CHCL

= 10 ns

VCC

RST

XTAL1

XTAL2

(NC)

SU01296

89C51RB2
89C51RC2
89C51RD2

Figure 42. I

Test Condition, Power Down Mode.

All other pins are disconnected; V

= 2V to 5.5V

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

FLASH EPROM MEMORY

GENERAL DESCRIPTION

The 89C51RB2/RC2/RD2 Flash memory augments EPROM
functionality with in-circuit electrical erasure and programming. The
Flash can be read and written as bytes. The Chip Erase operation will
erase the entire program memory. The Block Erase function can
erase any Flash block. In-system programming and standard parallel
programming are both available. On-chip erase and write timing
generation contribute to a user friendly programming interface.

The 89C51RB2/RC2/RD2 Flash reliably stores memory contents
even after 1000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. In addition, the
combination of advanced tunnel oxide processing and low internal
electric fields for erase and programming operations produces
reliable cycling. The 89C51RB2/RC2/RD2 uses a +5 V V

supply

to perform the Program/Erase algorithms.

FEATURES

Flash EPROM internal program memory with Block Erase.

Internal 1 kB fixed boot ROM, containing low-level in-system
programming routines and a default serial loader. User program
can call these routines to perform In-Application Programming
(IAP). The Boot ROM can be turned off to provide access to the
full 64 kB Flash memory.

Boot vector allows user provided Flash loader code to reside
anywhere in the Flash memory space. This configuration provides
flexibility to the user.

Default loader in Boot ROM allows programming via the serial port
without the need for a user provided loader.

Up to 64 kB external program memory if the internal program
memory is disabled (EA = 0).

Programming and erase voltage +5 V or +12 V.

Read/Programming/Erase:

Byte-wise read (100 ns access time).

Byte Programming (20

s).

Typical erase times:

Block Erase (8 kB or 16 kB) in 3 seconds.

Full Erase (64 kB) in 3 seconds.

Parallel programming with 87C51 compatible hardware interface
to programmer.

In-system programming.

Programmable security for the code in the Flash.

1000 minimum erase/program cycles for each byte.

10-year minimum data retention.

CAPABILITIES OF THE PHILIPS 89C51
FLASH-BASED MICROCONTROLLERS

Flash organization

The 89C51RB2/RC2/RD2 contains 16KB/32KB/64Kbytes of Flash
program memory. This memory is organized as 5 separate blocks.
The first two blocks are 8 kB in size, filling the program memory
space from address 0 through 3FFF hex. The final three blocks are
16 kB in size and occupy addresses from 4000 through FFFF hex.

Figure 43 depicts the Flash memory configurations.

Flash Programming and Erasure

There are three methods of erasing or programming of the Flash
memory that may be used. First, the Flash may be programmed or
erased in the end-user application by calling low-level routines
through a common entry point in the Boot ROM. The end-user
application, though, must be executing code from a different block
than the block that is being erased or programmed. Second, the
on-chip ISP boot loader may be invoked. This ISP boot loader will, in
turn, call low-level routines through the same common entry point in
the Boot ROM that can be used by the end-user application. Third,
the Flash may be programmed or erased using the parallel method
by using a commercially available EPROM programmer. The parallel
programming method used by these devices is similar to that used
by EPROM 87C51, but it is not identical, and the commercially
available programmer will need to have support for these devices.

Boot ROM

When the microcontroller programs its own Flash memory, all of the
low level details are handled by code that is permanently contained
in a 1 kB Boot ROM that is separate from the Flash memory. A user
program simply calls the common entry point with appropriate
parameters in the Boot ROM to accomplish the desired operation.
Boot ROM operations include things like: erase block, program byte,
verify byte, program security lock bit, etc. The Boot ROM overlays
the program memory space at the top of the address space from
FC00 to FFFF hex, when it is enabled. The Boot ROM may be
turned off so that the upper 1 kB of Flash program memory are
accessible for execution.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

FFFF

C000

8000

4000

2000

0000

BLOCK 4

16 kB

BLOCK 3

16 kB

BLOCK 2

16 kB

BLOCK 1

8 kB

BLOCK 0

8 kB

PROGRAM

ADDRESS

BOOT ROM

(1 kB)

FFFF

FC00

SU01298

89C51RD2

89C51RC2

89C51RB2

Figure 43. Flash Memory Configurations

Power-On Reset Code Execution

The 89C51RB2/RC2/RD2 contains two special Flash registers: the
BOOT VECTOR and the STATUS BYTE. At the falling edge of reset,
the 89C51RB2/RC2/RD2 examines the contents of the Status Byte.
If the Status Byte is set to zero, power-up execution starts at
location 0000H, which is the normal start address of the user's
application code. When the Status Byte is set to a value other than
zero, the contents of the Boot Vector is used as the high byte of the
execution address and the low byte is set to 00H. The factory
default setting is 0FCH, corresponds to the address 0FC00H for the
factory masked-ROM ISP boot loader. A custom boot loader can be
written with the Boot Vector set to the custom boot loader.

NOTE:

When erasing the Status Byte or Boot Vector,

both bytes are erased at the same time. It is necessary
to reprogram the Boot Vector after erasing and
updating the Status Byte.

Hardware Activation of the Boot Loader

The boot loader can also be executed by holding PSEN LOW,
EA greater than V

(such as +5 V), and ALE HIGH (or not connected)

at the falling edge of RESET. This is the same effect as having a
non-zero status byte. This allows an application to be built that will
normally execute the end user's code but can be manually forced
into ISP operation.

If the factory default setting for the Boot Vector (0FCH) is changed, it
will no longer point to the ISP masked-ROM boot loader code. If this
happens, the only way it is possible to change the contents of the
Boot Vector is through the parallel programming method, provided
that the end user application does not contain a customized loader
that provides for erasing and reprogramming of the Boot Vector and
Status Byte.

After programming the Flash, the status byte should be programmed
to zero in order to allow execution of the user's application code
beginning at address 0000H.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

+12 V OR + 5 V

+5 V

TxD

RxD

TxD

RxD

RST

XTAL2

XTAL1

SU01299

89C51RB2
89C51RC2
89C51RD2

Figure 44. In-System Programming with a Minimum of Pins

In-System Programming (ISP)

The In-System Programming (ISP) is performed without removing
the microcontroller from the system. The In-System Programming
(ISP) facility consists of a series of internal hardware resources
coupled with internal firmware to facilitate remote programming of
the 89C51RB2/RC2/RD2 through the serial port. This firmware is
provided by Philips and embedded within each
89C51RB2/RC2/RD2 device.

The Philips In-System Programming (ISP) facility has made in-circuit
programming in an embedded application possible with a minimum
of additional expense in components and circuit board area.

The ISP function uses five pins: TxD, RxD, V

, V

, and V

(see

Figure 44). Only a small connector needs to be available to interface
your application to an external circuit in order to use this feature.
The V

supply should be adequately decoupled and V

not

allowed to exceed datasheet limits.

Using the In-System Programming (ISP)

The ISP feature allows for a wide range of baud rates to be used in
your application, independent of the oscillator frequency. It is also
adaptable to a wide range of oscillator frequencies. This is
accomplished by measuring the bit-time of a single bit in a received
character. This information is then used to program the baud rate in
terms of timer counts based on the oscillator frequency. The ISP
feature requires that an initial character (an uppercase U) be sent to
the 89C51RB2/RC2/RD2 to establish the baud rate. The ISP
firmware provides auto-echo of received characters.

Once baud rate initialization has been performed, the ISP firmware
will only accept Intel Hex-type records. Intel Hex records consist of
ASCII characters used to represent hexadecimal values and are
summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the "NN" represents the number of data
bytes in the record. The 89C51RB2/RC2/RD2 will accept up to 16
(10H) data bytes. The "AAAA" string represents the address of the

first byte in the record. If there are zero bytes in the record, this field
is often set to 0000. The "RR" string indicates the record type. A
record type of "00" is a data record. A record type of "01" indicates
the end-of-file mark. In this application, additional record types will
be added to indicate either commands or data for the ISP facility.
The maximum number of data bytes in a record is limited to 16
(decimal). ISP commands are summarized in Table 8.

As a record is received by the 89C51RB2/RC2/RD2, the information
in the record is stored internally and a checksum calculation is
performed. The operation indicated by the record type is not
performed until the entire record has been received. Should an error
occur in the checksum, the 89C51RB2/RC2/RD2 will send an "X"
out the serial port indicating a checksum error. If the checksum
calculation is found to match the checksum in the record, then the
command will be executed. In most cases, successful reception of
the record will be indicated by transmitting a "." character out the
serial port (displaying the contents of the internal program memory
is an exception).

In the case of a Data Record (record type 00), an additional check is
made. A "." character will NOT be sent unless the record checksum
matched the calculated checksum and all of the bytes in the record
were successfully programmed. For a data record, an "X" indicates
that the checksum failed to match, and an "R" character indicates
that one of the bytes did not properly program. It is necessary to
send a type 02 record (specify oscillator frequency) to the
89C51RB2/RC2/RD2 before programming data.

The ISP facility was designed to that specific crystal frequencies
were not required in order to generate baud rates or time the
programming pulses. The user thus needs to provide the
89C51RB2/RC2/RD2 with information required to generate the
proper timing. Record type 02 is provided for this purpose.

WinISP, a software utility to implement ISP programming with a PC,
is available from Philips. Commercial serial ISP programmers are
available from third parties. Please check the Philips web site
(www.semiconductors.philips.com) for additional information.

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

RECORD TYPE

COMMAND/DATA FUNCTION

Miscellaneous Write Functions

:nnxxxx03ffssddcc

Where:

= number of bytes (hex) in record

xxxx

= required field, but value is a "don't care"

= Write Function

= subfunction code

= selection code

= data input (as needed)

= checksum

Subfunction Code = 01 (Erase Blocks)

ff = 01
ss = block code as shown below:
block 0, 0k to 8k, 00H
block 1, 8k to 16k, 20H
block 2, 16k to 32k, 40H
block 3, 32k to 48k, 80H
block 4, 48k to 64k, C0H

Example:

:0200000301C03A erase block 4

Subfunction Code = 04 (Erase Boot Vector and Status Byte)

ff = 04
ss = don't care
dd = don't care

Example:

:020000030400F7 erase boot vector and status byte

Subfunction Code = 05 (Program Security Bits)

ff = 05
ss = 00 program security bit 1 (inhibit writing to Flash)
01 program security bit 2 (inhibit Flash verify)
02 program security bit 3 (disable eternal memory)

Example:

:020000030501F5 program security bit 2

Subfunction Code = 06 (Program Status Byte or Boot Vector)

ff = 06
ss = 00 program status byte
01 program boot vector

Example:

:030000030601FCF7 program boot vector with 0FCH

Subfunction Code = 07 (Full Chip Erase)

Erases all blocks, security bits, and sets status and boot vector to default values

ff = 07
ss = don't care
dd = don't care

Example:

:0100000307F5 full chip erase

Display Device Data or Blank Check Record type 04 causes the contents of the entire Flash array to be sent out
the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that
address. No display of the device contents will occur if security bit 2 has been programmed. The dumping of the device
data to the serial port is terminated by the reception of any character.

General Format of Function 04

:05xxxx04sssseeeeffcc

Where:

= number of bytes (hex) in record

xxxx

= required field, but value is a "don't care"

= "Display Device Data or Blank Check" function code

ssss

= starting address

eeee

= ending address

= subfunction
00 = display data
01 = blank check

= checksum

Example:

:0500000440004FFF0069 display 40004FFF

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

In Application Programming Method

Several In Application Programming (IAP) calls are available for use by
an application program to permit selective erasing and programming of
Flash sectors. All calls are made through a common interface,
PGM_MTP. The programming functions are selected by setting up

the microcontroller's registers before making a call to PGM_MTP at
FFF0H. The oscillator frequency is an integer number rounded down
to the nearest megahertz. For example, set R0 to 11 for 11.0592 MHz.
Results are returned in the registers. The API calls are shown in
Table 9.

Table 9.

IAP calls

IAP CALL

PARAMETER

PROGRAM DATA BYTE

Input Parameters:

R0 = osc freq (integer)
R1 = 02h
DPTR = address of byte to program
ACC = byte to program

Return Parameter

ACC = 00 if pass, !00 if fail

ERASE BLOCK

Input Parameters:

R0 = osc freq (integer)
R1 = 01h
DPH = block code as shown below:
block 0, 0k to 8k, 00H
block 1, 8k to 16k, 20H
block 2, 16k to 32k, 40H
block 3, 32k to 48k, 80H
block 4, 48k to 64k, C0H

DPL = 00h

Return Parameter

none

ERASE BOOT VECTOR

Input Parameters:

R0 = osc freq (integer)
R1 = 04h
DPH = 00h
DPL = don't care

Return Parameter

none

PROGRAM SECURITY BIT

Input Parameters:

R0 = osc freq (integer)
R1 = 05h
DPH = 00h
DPL = 00h security bit # 1 (inhibit writing to Flash)
01h security bit # 2 (inhibit Flash verify)
02h security bit # 3 (disable external memory)

Return Parameter

none

PROGRAM STATUS BYTE

Input Parameters:

R0 = osc freq (integer)
R1 = 06h
DPH = 00h
DPL = 00h program status byte
ACC = status byte

Return Parameter

ACC = status byte

PROGRAM BOOT VECTOR

Input Parameters:

R0 = osc freq (interger)
R1 = 06h
DPH = 00h
DPL = 01h program boot vector
ACC = boot vector

Return Parameter

ACC = boot vector

READ DEVICE DATA

Input Parameters:

R1 = 03h
DPTR = address of byte to read

Return Parameter

ACC = value of byte read

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

IAP CALL

PARAMETER

READ MANUFACTURER ID

Input Parameters:

R0 = osc freq (integer)
R1 = 00h
DPH = 00h
DPL = 00h (manufacturer ID)

Return Parameter

ACC = value of byte read

READ DEVICE ID # 1

Input Parameters:

R0 = osc freq (integer)
R1 = 00h
DPH = 00h
DPL = 01h (device ID # 1)

Return Parameter

ACC = value of byte read

READ DEVICE ID # 2

Input Parameters:

R0 = osc freq (integer)
R1 = 00h
DPH = 00h
DPL = 02h (device ID # 2)

Return Parameter

ACC = value of byte read

READ SECURITY BITS

Input Parameters:

R0 = osc freq (integer)
R1 = 07h
DPH = 00h
DPL = 00h (security bits)

Return Parameter

ACC = value of byte read

READ STATUS BYTE

Input Parameters:

R0 = osc freq (integer)
R1 = 07h
DPH = 00h
DPL = 01h (status byte)

Return Parameter

ACC = value of byte read

READ BOOT VECTOR

Input Parameters:

R0 = osc freq (integer)
R1 = 07h
DPH = 00h
DPL = 02h (boot vector)

Return Parameter

ACC = value of byte read

FULL CHIP ERASE

Input Parameters:

R0 = osc frequency
R1 = 08h
DPH = don't care
DPL = don't care

Return Parameter

none

Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 09-99

Document order number:

939775006427

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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