P89C669

80C51 8-bit microcontroller family with extended memory;
96 kB Flash with 2 kB RAM

Rev. 02 -- 13 November 2003

Product data

General description

The P89C669 represents the first Flash microcontroller based on Philips
Semiconductors' new 51MX core. The P89C669 features 96 kbytes of Flash program
memory and 2 kbytes of data SRAM. In addition, this device is equipped with a
Programmable Counter Array (PCA), a watchdog timer that can be configured to
different time ranges through SFR bits, as well as two enhanced UARTs and byte
based I

C-bus serial interface.

Philips Semiconductors' 51MX (Memory eXtension) core is an accelerated 80C51
architecture that executes instructions at twice the rate of standard 80C51 devices.
The linear address range of the 51MX has been expanded to support up to 8 Mbytes
of program memory and 8 Mbytes of data memory. It retains full program code
compatibility to enable design engineers to re-use 80C51 development tools,
eliminating the need to move to a new, unfamiliar architecture. The 51MX core also
retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced
peripherals and Application Specific Integrated Circuits (ASICs).

The P89C669 provides greater functionality, increased performance and overall lower
system cost. By offering an embedded memory solution combined with the
enhancements to manage the memory extension, the P89C669 eliminates the need
for software work-arounds. The increased program memory enables design
engineers to develop more complex programs in a high-level language like C, for
example, without struggling to contain the program within the traditional 64 kbytes of
program memory. These enhancements also greatly improve C Language efficiency
for code size below 64 kbytes.

The P89C669 device contains a non-volatile Flash program memory that is both
parallel programmable and serial In-System and In-Application Programmable.
In-System Programming (ISP) allows the user to download new code while the
microcontroller sits in the application. In-Application Programming (IAP) means that
the microcontroller fetches new program code and reprograms itself while in the
system. This allows for remote programming over a modem link. A default serial
loader (boot loader) program in ROM allows serial In-System programming of the
Flash memory via the UART without the need for a loader in the Flash code. For
In-Application Programming, the user program erases and reprograms the Flash
memory by use of standard routines contained in ROM.

The 51MX core is described in more detail in the

51MX Architecture Reference.

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

2 of 33

9397 750 12299

Features

2.1 Key features

Extended features of the 51MX Core:

23-bit program memory space and 23-bit data memory space

Linear program and data address range expanded to support up to 8 Mbytes
each

Program counter expanded to 23 bits

Stack pointer extended to 16 bits enabling stack space beyond the 80C51
limitation

New 23-bit extended data pointer and two 24-bit universal pointers greatly
improve C compiler code efficiency in using pointers to access variables in
different spaces

100% binary compatibility with the classic 80C51 so that existing code is
completely reusable

Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

96 kbytes of on-chip program Flash

2 kbytes of on-chip data RAM

Programmable Counter Array (PCA)

Two full-duplex enhanced UARTs

Byte based Fast I

C serial interface (400 kbits/s)

2.2 Key benefits

Increases program/data address range to 8 Mbytes each

Enhances performance and efficiency for C programs

Fully 80C51-compatible microcontroller

Provides seamless and compelling upgrade path from classic 80C51

Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs

Supported by wide range of 80C51 development systems and programming tools
vendors

The P89C669 makes it possible to develop applications at lower cost and with a
reduced time-to-market

2.3 Complete features

Fully static

Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application
Programming (IAP) capability

2 kbytes of on-chip RAM

23-bit program memory space and 23-bit data memory space

Four-level interrupt priority

32 I/O lines (4 ports)

Three Timers: Timer0, Timer1 and Timer2

Two full-duplex enhanced UARTs with baud rate generator

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

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Byte based Fast I

C-bus serial interface (400 kbits/s)

Framing error detection

Automatic address recognition

Power control modes

Clock can be stopped and resumed

Idle mode

Power-down mode

Second DPTR register

Asynchronous port reset

Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five
Capture/Compare modules

Low EMI (inhibit ALE)

Watchdog timer with programmable prescaler for different time ranges
(compatible with 8xC66x with added prescaler)

Ordering information

3.1 Ordering options

Table 1:

Ordering information

Type number

Package

Name

Description

Version

P89C669FA

PLCC44

plastic leaded chip carrier; 44 leads

SOT187-2

P89C669BBD

LQFP44

plastic low profile quad flat package; 44 leads;
body 10

1.4 mm

SOT389-1

Table 2:

Ordering options

Type number

Memory

Temperature range

voltage

range

Frequency

OTP

RAM

P89C669FA

96 kB

2048 B

C to +85

4.5 to 5.5 V

0 to 24 MHz

P89C669BBD

96 kB

2048 B

C to +70

4.5 to 5.5 V

0 to 24 MHz

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P89C669

80C51 8-bit microcontroller family with extended memory

Product data

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Pinning information

6.1 Pinning

6.1.1

Plastic leaded chip carrier

Fig 3.

PLCC44 pin configuration.

P89C669FA

002aaa404

P1.4/CEX1

P1.3/CEX0

P1.2/ECI

P1.1/T2EX

P1.0/T2

(NC/V

)

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P3.6/WR

P3.7/RD

XTAL2

XTAL1

(NC/V

)

P2.0/A8/A16

P2.1/A9/A17

P2.2/A10/A18

P2.3/A11/A19

P2.4/A12/A20

P1.5/CEX2

P1.6/SCL

P1.7/SDA

RST

P3.0/RXD0

RXD1

P3.1/TXD0

P3.2/INT0

P3.3/INT1

P3.4/CEX3/T0

P3.5/CEX4/T1

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

TXD1

ALE

PSEN

P2.7/A15

P2.6/A14/A22

P2.5/A13/A21

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P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

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9397 750 12299

6.1.2

Plastic low profile quad flat package

Fig 4.

LQFP44 pin configuration.

P89C669BBD

002aaa406

P1.4/CEX1

P1.3/CEX0

P1.2/ECI

P1.1/T2EX

P1.0/T2

(NC/V

)

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P3.6/WR

P3.7/RD

XTAL2

XTAL1

(NC/V

)

P2.0/A8/A16

P2.1/A9/A17

P2.2/A10/A18

P2.3/A11/A19

P2.4/A12/A20

P1.5/CEX2

P1.6/SCL

P1.7/SDA

RST

P3.0/RXD0

RXD1

P3.1/TXD0

P3.2/INT0

P3.3/INT1

P3.4/CEX3/T0

P3.5/CEX4/T1

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

TXD1

ALE

PSEN

P2.7/A15

P2.6/A14/A22

P2.5/A13/A21

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P89C669

80C51 8-bit microcontroller family with extended memory

Product data

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6.2 Pin description

Table 3:

Pin description

Symbol

Pin

Type

Description

PLCC

LQFP

P0.0 - P0.7

43 - 36

30 - 37

I/O

Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external
program and data memory. In this application, it uses strong internal pull-ups
when emitting 1s.

P1.0 - P1.7

2 - 9

1 - 3,
40 - 44

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.
Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally pulled LOW
will source current because of the internal pull-ups.

I/O

P1.0, T2

Timer/Counter 2 external count input/Clock out

P1.1, T2EX

Timer/Counter 2 Reload/Capture/Direction Control

P1.2, ECI

External Clock Input to the PCA

I/O

P1.3, CEX0

Capture/Compare External I/O for PCA module 0

I/O

P1.4, CEX1

Capture/Compare External I/O for PCA module 1 (with pull-up on pin)

I/O

P1.5, CEX2

Capture/Compare External I/O for PCA module 2 (with pull-up on pin)

I/O

P1.6, SCL

C serial clock (when I

C is used, this pin is open-drain and requires

external pull-up due to I

C-bus specification)

I/O

P1.7, SDA

C serial data (when I

C is used, this pin is open-drain and requires

external pull-up due to I

C-bus specification)

P2.0 - P2.7

24 - 31

18 - 25

I/O

Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins
that have 1s written to them are pulled HIGH by the internal pull-ups and can be
used as inputs. As inputs, port 2 pins that are externally being pulled LOW will
source current because of the internal pull-ups. (See

Section 9 "Static

characteristics"

, I

). Port 2 emits the high-order address byte during fetches from

external program memory and during accesses to external data memory that
use 16-bit addresses (MOVX @ DPTR) or 23-bit addresses (MOVX @EPTR,
EMOV). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @ Ri),
port 2 emits the contents of the P2 Special Function Register.

Note that when 23-bit address is used, address bits A16-A22 will be outputted to
P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to
P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless of
ALE.

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P89C669

80C51 8-bit microcontroller family with extended memory

Product data

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P3.0 - P3.7

11,
13 - 19

5,
7 - 13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled HIGH by the internal pull-ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source
current because of the internal pull-ups.

P3.0, RXD0

Serial input port 0

P3.1, TXD0

Serial output port 0

P3.2, INT0

External interrupt 0

P3.3, INT1

External interrupt 1

P3.4, T0/CEX3

Timer0 external input/capture/compare external I/O for PCA module 3

P3.5, T1/CEX4

Timer1 external input/capture/compare external I/O for PCA module 3

P3.6, WR

External data memory write strobe

P3.7, RD

External data memory read strobe

RXD1

RXD1

Serial input port 1 (with pull-up on pin)

TXD1

TXD1

Serial output port 1 (with pull-up on pin)

RST

Reset: A HIGH on this pin for two machine cycles, while the oscillator is running,
resets the device. An internal diffused resistor to V

permits a power-on reset

using only an external capacitor to V

ALE

Address Latch Enable: Output pulse for latching the LOW byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of

the oscillator frequency, and can be used for external timing

or clocking. Note that one ALE pulse is skipped during each access to external
data memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set,
ALE will be active only during a MOVX instruction.

PSEN

Program Store Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during fetches from
internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be
externally held LOW to enable the device to fetch code from external program
memory locations. If EA is held HIGH, the device executes from internal program
memory. The value on the EA pin is latched when RST is released and any
subsequent changes have no effect.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

PLCC

LQFP

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80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

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XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as
Idle and Power-down modes.

(NC/V

)

No Connect/Ground: This pin is internally connected to V

on the P89C669. If

connected externally, this pin must only be connected to the same V

as at

pin 22. (Note: Connecting the second pair of V

and V

pins is not required.

However, they may be connected in addition to the primary V

and V

pins to

improve power distribution, reduce noise in output signals, and improve
system-level EMI characteristics.)

(NC/V

)

No Connect/Power Supply: This pin is internally connected to V

on the

P89C669. If connected externally, this pin must only be connected to the same
V

as at pin 44. (Note: Connecting the second pair of V

and V

pins is not

required. However, they may be connected in addition to the primary V

and

pins to improve power distribution, reduce noise in output signals, and

improve system-level EMI characteristics.)

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

PLCC

LQFP

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P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

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Functional description

7.1 Flash memory description

The P89C669 contains 96 kbytes of Flash program memory. It is organized as
12 separate blocks, each block containing 8 kbytes.

The P89C669 Flash memory augments EPROM functionality with in-circuit electrical
erasure and programming. The Flash can be read and written as bytes. The Chip
Erase operation will erase the entire program memory. The Block Erase function can
erase any Flash byte block. In-system programming and standard parallel
programming are both available. On-chip erase and write timing generation contribute
to a user friendly programming interface. The P89C669 Flash reliably stores memory
contents even after 10,000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal electric fields for erase and
programming operations produces reliable cycling. The P89C669 uses a +5 V V

supply to perform the Program/Erase algorithms.

Flash internal program memory with Block Erase.

Internal 4 kbytes Boot Flash, containing low-level in-system programming routines
and a default UART loader. User program can call these routines to perform
In-Application Programming (IAP). The BootFlash can be turned off to provide
access to the full 8 Mbytes memory space.

Boot vector allows user provided Flash loader code to reside anywhere in the
Flash memory space. This configuration provides flexibility to the user.

Default loader in BootFlash allows programming via the UART interface without the
need for a user provided loader.

Up to 8 Mbytes of external program memory if the internal program memory is
disabled (EA = 0).

+5 V programming and erase voltage.

Read/Programming/Erase using ISP/IAP:

Byte Programming (20

s).

Typical quick erase times (including preprogramming time):

Block Erase (8 kbytes) in 1 second.

Full Erase (96 kbytes) in 1 second.

Parallel programming with 87C51-like hardware interface to programmer.

Programmable security for the code in the Flash.

10,000 minimum erase/program cycles for each byte.

10 year minimum data retention.

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80C51 8-bit microcontroller family with extended memory

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7.2 Memory arrangement

P89C669 has 96 kbytes of Flash (MX universal map range: 80:0000-81:7FFF) and
2 kbytes of on-chip RAM:

For more detailed information, please refer to the

P89C669 User Manual.

7.3 Special function registers

Special Function Register (SFR) accesses are restricted in the following ways:

User must not attempt to access any SFR locations not defined.

Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.

SFR bits labeled `-', `0', or `1' can only be written and read as follows:

`-' must be written with `0', but can return any value when read (even if it was

written with `0'). It is a reserved bit and may be used in future derivatives.

`0' must be written with `0', and will return a `0' when read.

`1' must be written with `1', and will return a `1' when read.

Table 4:

Memory arrangement

Data memory

Size (Bytes) and MX
universal memory
map range

Type

Description

P89C669

DATA

memory that can be addressed both directly and
indirectly; can be used as stack

128

(7F:0000-7F:007F)

IDATA

superset of DATA; memory that can be addressed
indirectly (where direct address for upper half is for SFR
only); can be used as stack

256

(7F:0000-7F:00FF)

EDATA

superset of DATA/IDATA; memory that can be addressed
indirectly using Universal Pointers (PR0,1); can be used
as stack

1280

(7F:0000-7F:04FF)

XDATA

memory (on-chip `External Data') that is accessed via
the MOVX/EMOV instructions using DPTR/EPTR

768

(00:0000-00:02FF)

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Table 5:

Special function registers

Name

Description

SFR
addr.

Bit functions and addresses

Reset
value

MSB

LSB

Bit address E7

ACC

[1]

Accumulator

E0H

00H

AUXR

[2]

Auxiliary Function Register

8EH

EXTRAM AO

00H

[6]

AUXR1

[2]

Auxiliary Function Register 1

A2H

ENBOOT -

GF2

DPS

00H

[6]

Bit address F7

[1]

B Register

F0H

00H

BRGCON

[2]

Baud Rate Generator Control

85H

[3]

S0BRGS

BRGEN

00H

[6]

BRGR0

[2][5]

Baud Rate Generator Rate LOW 86H

[3]

00H

BRGR1

[2][5]

Baud Rate Generator Rate HIGH 87H

[3]

00H

[6]

CCAP0H

[2]

Module 0 Capture HIGH

FAH

XXH

CCAP1H

[2]

Module 1 Capture HIGH

FBH

XXH

CCAP2H

[2]

Module 2 Capture HIGH

FCH

XXH

CCAP3H

[2]

Module 3 Capture HIGH

FDH

XXH

CCAP4H

[2]

Module 4 Capture HIGH

FEH

XXH

CCAP0L

[2]

Module 0 Capture LOW

EAH

XXH

CCAP1L

[2]

Module 1 Capture LOW

EBH

XXH

CCAP2L

[2]

Module 2 Capture LOW

ECH

XXH

CCAP3L

[2]

Module 3 Capture LOW

EDH

XXH

CCAP4L

[2]

Module 4 Capture LOW

EEH

XXH

CCAPM0

[2]

Module 0 Mode

DAH

ECOM_0

CAPP_0

CAPN_0

MAT_0

TOG_0

PWM_0

ECCF_0

00H

[6]

CCAPM1

[2]

Module 1 Mode

DBH

ECOM_1

CAPP_1

CAPN_1

MAT_1

TOG_1

PWM_1

ECCF_1

00H

[6]

CCAPM2

[2]

Module 2 Mode

DCH

ECOM_2

CAPP_2

CAPN_2

MAT_2

TOG_2

PWM_2

ECCF_2

00H

[6]

CCAPM3

[2]

Module 3 Mode

DDH

ECOM_3

CAPP_3

CAPN_3

MAT_3

TOG_3

PWM_3

ECCF_3

00H

[6]

CCAPM4

[2]

Module 4 Mode

DEH

ECOM_4

CAPP_4

CAPN_4

MAT_4

TOG_4

PWM_4

ECCF_4

00H

[6]

Bit address DF

CCON

[1] [2]

PCA Counter Control

D8H

CCF4

CCF3

CCF2

CCF1

CCF0

00H

[6]

[2]

PCA Counter HIGH

F9H

00H

[2]

PCA Counter LOW

E9H

00H

CMOD

[2]

PCA Counter Mode

D9H

CIDL

WDTE

CPS1

CPS0

ECF

00H

[6]

DPTR

Data Pointer (2 bytes)

00H

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DPH

Data Pointer HIGH

83H

00H

DPL

Data Pointer LOW

82H

00H

EPL

[2]

Extended Data Pointer LOW

FCH

[3]

00H

EPM

[2]

Extended Data Pointer Middle

FDH

[3]

00H

EPH

[2]

Extended Data Pointer HIGH

FEH

[3]

00H

I2ADR

C Slave Address Register

94H

addr.6

addr.5

addr.4

addr.3

addr.2

addr.1

addr.0

00H

I2CON

C Control Register

91H

I2EN

STA

STO

CRSEL

00H

I2DAT

C Data Register

93H

I2CLH

C Clock Generator HIGH

96H

00H

I2CLL

C Clock Generator LOW

95H

00H

I2STA

C Status Register

92H

code.4

code.3

code.2

code.1

code.0

F8H

Bit address AF

IEN0

[1]

Interrupt Enable 0

A8H

ET2

ES0/

ES0R

ET1

EX1

ET0

EX0

00H

Bit address EF

IEN1

[1]

Interrupt Enable 1

E8H

EI2C

ES1T

ES0T

ES1/

ES1R

00H

[6]

Bit address BF

IP0

[1]

Interrupt Priority

B8H

PPC

PT2

PS0/

PS0R

PT1

PX1

PT0

PX0

00H

IP0H

Interrupt Priority 0 HIGH

B7H

PPCH

PT2H

PS0H/

PS0RH

PT1H

PX1H

PT0H

PX0H

00H

Bit address FF

IP1

[1]

Interrupt Priority 1

F8H

PI2C

PS1T

PS0T

PS1/

PS1R

00H

[6]

IP1H

Interrupt Priority 1 HIGH

F7H

PI2CH

PS1TH

PS0TH

PS1H/

PS1RH

00H

[6]

MXCON

[2]

MX Control Register

FFH

[3]

EAM

ESMM

EIFM

00H

[6]

Table 5:

Special function registers

...continued

Name

Description

SFR
addr.

Bit functions and addresses

Reset
value

MSB

LSB

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Bit address 87

[1]

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

Bit address 97

[1]

Port 1

90H

CEX4

CEX3

CEX2/

SPICLK

CEX1/

MOSI

CEX0

ECI

T2EX

FFH

Bit address A7

[1]

Port 2

A0H

AD15

AD14/

AD22

ADA13/

AD21

AD12/

AD20

AD11/

AD19

AD10/

AD18

AD9/

AD17

AD8/

AD16

FFH

Bit address B7

[1]

Port 3

B0H

INT1

INT0

TxD0

RxD0

FFH

PCON

[2]

Power Control Register

87H

SMOD1

SMOD0

POF

GF1

GF0

IDL

00H/

10H

[4]

Bit address D7

PSW

[1]

Program Status Word

D0H

RS1

RS0

00H

RCAP2H

[2]

Timer2 Capture HIGH

CBH

00H

RCAP2L

[2]

Timer2 Capture LOW

CAH

00H

Bit address 9F

S0CON

[1]

Serial Port 0 Control

98H

SM0_0/

FE_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00H

S0BUF

Serial Port 0 Data Buffer
Register

99H

xxH

S0ADDR

Serial Port 0 Address Register

A9H

00H

S0ADEN

Serial Port 0 Address Enable

B9H

00H

S0STAT

[2]

Serial Port 0 Status

8CH

[3]

DBMOD_0

INTLO_0

CIDIS_0

DBISEL_
0

FE_0

BR_0

OE_0

STINT_0

00H

[6]

Bit address 87

[3]

S1CON

[1] [2]

Serial Port 1 Control

80H

[3]

SM0_1/

FE_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

00H

S1BUF

[2]

Serial Port 1 Data buffer Register 81H

[3]

XXH

S1ADDR

[2]

Serial Port 1 Address Register

82H

[3]

00H

Table 5:

Special function registers

...continued

Name

Description

SFR
addr.

Bit functions and addresses

Reset
value

MSB

LSB

Philips Semiconductor

P89C669

80C51 8-bit micr

ocontr

oller famil

y with e

xtended memor

9397

750

12299

oninklijk

e Philips Electronics N.V

. 2003. All r

ights reser

ed.

Pr
oduct data

Re
v

.
02 -- 13 No

vember 2003

16 of 33

[1]

SFRs are bit addressable.

[2]

SFRs are modified from or added to the 80C51 SFRs.

[3]

Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h).

[4]

Power-on reset is 10H. Other reset is 00H.

[5]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable.

[6]

The unimplemented bits (labeled `-') in the SFRs are X's (unknown) at all times. `1's should NOT be written to these bits, as they may be used for other purposes in future
derivatives. The reset values shown for these bits are `0's although they are unknown when read.

S1ADEN

[2]

Serial Port 1 Address Enable

83H

[3]

00H

S1STAT

[2]

Serial Port 1 Status

84H

[3]

DBMOD_1

INTLO_1

CIDIS_1

DBISEL1

FE_1

BR_1

OE_1

STINT_1

00H

[6]

Stack Pointer (Stack Pointer
LOW Byte)

81H

07H

SPE

[2]

Stack Pointer HIGH

FBH

[3]

00H

Bit address 8F

TCON

[1]

Timer Control Register

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

T2CON

[1] [2]

Timer2 Control Register

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

00H

T2MOD

[2]

Timer2 Mode Control

C9H

T2OE

DCEN

00H

[6]

TH0

Timer 0 HIGH

8CH

00H

TH1

Timer 1 HIGH

8DH

00H

TH2

Timer 2 HIGH

CDH

00H

TL0

Timer 0 LOW

8AH

00H

TL1

Timer 1 LOW

8BH

00H

TL2

Timer 2 LOW

CCH

00H

TMOD

Timer 0 and 1 Mode

89H

GATE

C/T

GATE

C/T

00H

WDTRST

[2]

Watchdog Timer Reset

A6H

FFH

WDCON

[2]

Watchdog Timer Control

8FH

[3]

WDPRE2 WDPRE1 WDPRE0 00H

[6]

Table 5:

Special function registers

...continued

Name

Description

SFR
addr.

Bit functions and addresses

Reset
value

MSB

LSB

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

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7.4 Security bits

The P89C669 has security bits to protect users' firmware codes. With none of the
security bits programmed, the code in the program memory can be verified. When
only security bit 1 (see

Table 6

) is programmed, MOVC instructions executed from

external program memory are disabled from fetching code bytes from the internal
memory. EA is latched on Reset and all further programming of EPROM is disabled.
When security bits 1 and 2 are programmed, in addition to the above, verify mode is
disabled. When all three security bits are programmed, all of the conditions above
apply and all external program memory execution is disabled.

[1]

P - programmed. U - unprogrammed.

[2]

Any other combination of security bits is not defined.

Limiting values

[1]

The following applies to the Limiting values:

a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in

Section 9 "Static characteristics"

and

Section 10 "Dynamic characteristics"

of this specification is not implied.

b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless

otherwise noted.

Table 6:

EPROM security bits

Security Bits

[1][2]

Bit 1

Bit 2

Bit 3

Protection description

No program security features enabled. Flash is
programmable and verifiable.

MOVC instructions executed from external
program memory are disabled from fetching code
bytes from internal memory, EA is sampled and
latched on Reset, and further programming of the
EPROM is disabled.

Same as 2, also verification is disabled.

Same as 3, external execution is disabled.

Table 7:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

amb

operating temperature

under bias

+70

+85

stg

storage temperature range

+150

input voltage on EA/V

pin to V

+13

input voltage on any other pin to V

0.5

+ 0.5

, I

maximum I

per I/O pin

power dissipation

based on package heat
transfer, not device power
consumption

1.5

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

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Static characteristics

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), 5 V, unless otherwise stated.

[2]

Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V

of ALE and ports 1, 3 and 4. The noise is

due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus
operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be
desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I

can exceed these

conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

[3]

Capacitive loading on ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the V

0.7 V specification when

the address bits are stabilizing.

[4]

Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from `1' to `0'. The transition current reaches
its maximum value when V

is approximately 2 V for 4.5 V < V

< 5.5 V.

[5]

See

Figure 10

through

Figure 13

for I

test conditions. f

osc

is the oscillator frequency in MHz.

[6]

This value applies to T

amb

= 0

C to +70

[7]

Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[8]

Under steady state (non-transient) conditions, I

must be externally limited as follows:

a) Maximum I

per port pin: 15 mA

b) Maximum I

per 8-bit port: 26 mA

Table 8:

DC electrical characteristics

amb

= 0

C to

C for commercial, unless otherwise specified; V

= 4.5 V to 5.5 V unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

[1]

Max

Unit

LOW-level input voltage

0.5

0.2V

0.1

HIGH-level input voltage
(ports 0, 1, 2, 3, 4, EA)

0.2V

+ 0.9 -

+ 0.5

IH1

HIGH-level input voltage,
XTAL1, RST

0.7V

+ 0.5

LOW-level output voltage,
ports 1, 2, 3, 4

[8]

= 4.5 V; I

= 1.6 mA

0.4

OL1

LOW-level output voltage,
port 0, ALE, PSEN

[7][8]

= 4.5 V; I

= 3.2 mA

0.4

HIGH-level output voltage,
ports 1, 2, 3, 4

= 4.5 V; I

30 A

0.7

OH1

HIGH-level output voltage
(port 0 in external bus
mode), ALE

[9]

, PSEN

[3]

= 4.5 V;

3.2 mA

0.7

Logical 0 input current,
ports 1, 2, 3, 4

= 0.4 V

Logical 1-to-0 transition
current, ports 1, 2, 3, 4

[8]

4.5 V < V

< 5.5 V;

= 2.0 V

[4]

650

Input leakage current, port 0

0.45 < V

< V

0.3

Power supply current

[5]

Active mode

[5]

= 5.5 V

7 + 2.7

osc

[MHz]

Idle mode

[5]

4 + 1.3

osc

[MHz]

Power-down mode or clock
stopped (see

Figure 13

for

conditions)

100

RST

Internal reset pull-down
resistor

225

Pin capacitance

[10]

(except EA)

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

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c) Maximum total I

for all outputs: 71 mA

If I

exceeds the test condition, V

may exceed the related specification. Pins are not guaranteed to sink current greater than the

listed test conditions.

[9]

ALE is tested to V

OH1

, except when ALE is off then V

is the voltage specification.

[10] Pin capacitance is characterized but not tested.

10. Dynamic characteristics

Table 9:

AC electrical characteristics

amb

= 0

C to +70

C for commercial unless otherwise specified. Formulae including t

CLCL

assume oscillator signal with

50/50 duty cycle.

[1][2][3]

Symbol

Figure

Parameter

4.5 V < V

< 5.5 V

Unit

Variable clock

[4]

OSC

= 24 MHz

[4]

Min

Max

Min

Max

OSC

Oscillator frequency

MHz

CLCL

Clock cycle

41.5

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE LOW

0.5t

CLCL

LLAX

Address hold after ALE LOW

0.5t

CLCL

LLIV

ALE LOW to valid instruction in

CLCL

LLPL

ALE LOW to PSEN LOW

0.5t

CLCL

PLPH

PSEN pulse width

1.5t

CLCL

PLIV

PSEN LOW to valid instruction in

1.5t

CLCL

PXIX

Input instruction hold after PSEN

PXIZ

Input instruction float after PSEN

0.5t

CLCL

AVIV

Address to valid instruction in
(non-Extended Addressing Mode)

2.5t

CLCL

AVIV1

Address (A16-A22) to valid instruction
in (Extended Addressing Mode)

1.5t

CLCL

PLAZ

PSEN LOW to address float

Data Memory

RLRH

RD pulse width

CLCL

105

WLWH

WR pulse width

CLCL

105

RLDV

RD LOW to valid data in

2.5t

CLCL

RHDX

Data hold after RD

RHDZ

Data float after RD

CLCL

LLDV

ALE LOW to valid data in

CLCL

131

AVDV

Address to valid data in (non-Extended
Addressing Mode)

4.5t

CLCL

157

AVDV1

Address (A16-A22) to valid data in
(Extended Addressing Mode)

3.5t

CLCL

110

LLWL

ALE LOW to RD or WR LOW

1.5t

CLCL

1.5t

CLCL

+ 20

AVWL

Address valid to WR or RD LOW
(non-Extended Addressing Mode)

CLCL

AVWL1

Address (A16-A22) valid to WR or RD
LOW (Extended Addressing Mode)

CLCL

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

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20 of 33

9397 750 12299

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[3]

Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.

[4]

Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.

QVWX

Data valid to WR transition

0.5t

CLCL

WHQX

Data hold after WR

0.5t

CLCL

QVWH

Data valid to WR HIGH

3.5t

CLCL

135

RLAZ

RD LOW to address float

WHLH

RD or WR HIGH to ALE HIGH

0.5t

CLCL

0.5t

CLCL

+ 10

External Clock

CHCX

HIGH time

CLCL

CLCX

LOW time

CLCL

CHCX

CLCH

Rise time

CHCL

Fall Time

Shift Register

XLXL

Serial port clock cycle time

CLCL

250

QVXH

Output data set-up to clock rising edge

CLCL

198

XHQX

Output data hold after clock rising edge t

CLCL

XHDX

Input data hold after clock rising edge

XHDV

Clock rising edge to input data valid

CLCL

173

Table 9:

AC electrical characteristics

...continued

amb

= 0

C to +70

C for commercial unless otherwise specified. Formulae including t

CLCL

assume oscillator signal with

50/50 duty cycle.

[1][2][3]

Symbol

Figure

Parameter

4.5 V < V

< 5.5 V

Unit

Variable clock

[4]

OSC

= 24 MHz

[4]

Min

Max

Min

Max

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

21 of 33

9397 750 12299

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[3]

Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.

[4]

Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.

10.1 Explanation of AC symbols

Each timing symbol has five characters. The first character is always `t' ( = time). The
other characters, depending on their positions, indicate the name of a signal or the
logical status of that signal. The designations are:

A -- Address

C -- Clock

D -- Input data

H -- Logic level HIGH

I -- Instruction (program memory contents)

L -- Logic level LOW, or ALE

P -- PSEN

Q -- Output data

R -- RD signal

t -- Time

V -- Valid

W -- WR signal

X -- No longer a valid logic level

Z -- Float

Table 10:

C-bus interface characteristics

Symbol

Parameter

Conditions

Input

Output

HD;STA

START condition hold time

CLCL

> 4.0

LOW

SCL LOW time

CLCL

> 4.7

HIGH

SCL HIGH time

CLCL

> 4.0

SCL rise time

SCL fall time

0.3

< 0.3

SU;DAT1

Data set-up time

250 ns

> 10t

CLCL

SU;DAT2

SDA set-up time

before repeated START
condition

250 ns

> 1

SU;DAT3

SDA set-up time

before STOP condition

250 ns

> 4t

CLCL

HD;DAT

Data hold time

0 ns

> 4t

CLCL

- t

SU;STA

Repeated START set-up
time

CLCL

> 4.7

SU;STO

STOP condition set-up time

CLCL

> 4.0

BUF

Bus free time

CLCL

> 4.7

SDA rise time

SDA fall time

300 ns

< 0.3

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

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9397 750 12299

Examples:

AVLL

-- Time for address valid to ALE LOW.

LLPL

-- Time for ALE LOW to PSEN LOW.

10.2 Timing diagrams

Fig 5.

External program memory read cycle.

tPLPH

tPXIZ

tLLIV

tAVIV1

tAVIV

P2.0-P2.7 OR A8-A15

INSTR IN

A0-A7

tAVLL

tLLAX

tPXIX

tLLPL

tPLIV

tPLAZ

tLHLL

A0-A7

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

ALE

PORT 0

PORT 2

PSEN

002aaa150

Fig 6.

External data memory read cycle.

tRHDZ

tAVDV1

tAVWL1

tAVWL

tLLWL

tWHLH

tRLAZ

tRLDV

DATA in

A0-A7 FROM PCL

INSTR IN

tAVLL

tLLAX

tRHDX

tLLDV

tRLRH

A0-A7

ALE

PORT 0

PORT 2

PSEN

002aaa151

P2.0-P2.7 OR A8-A15

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

tAVDV

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

26 of 33

9397 750 12299

12. Package outline

Fig 14. SOT187-2.

UNIT

min.

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

4.57
4.19

0.51

3.05

0.53
0.33

0.021
0.013

16.66
16.51

1.27

17.65
17.40

2.16

0.18

0.1

0.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT187-2

(1)

16.66
16.51

17.65
17.40

(1)

max.

(1)

max.

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.02

0.12

0.25

0.01

0.656
0.650

0.05

0.695
0.685

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.656
0.650

0.695
0.685

16.00
14.99

0.63
0.59

16.00
14.99

0.63
0.59

0.085

0.032
0.026

0.048
0.042

detail X

(A )

Z D

Z E

pin 1 index

112E10

MS-018

EDR-7319

10 mm

scale

99-12-27
01-11-14

inches

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

27 of 33

9397 750 12299

Fig 15. SOT389-1.

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.15
0.05

1.45
1.35

0.25

0.45
0.30

0.20
0.12

10.1

9.9

0.8

12.15
11.85

1.14
0.85

7
0

0.2

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT389-1

136E08

MS-026

00-01-19
02-06-07

(1)

10.1

9.9

12.15
11.85

1.14
0.85

detail X

(A )

2.5

5 mm

scale

pin 1 index

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm

SOT389-1

Philips Semiconductors

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80C51 8-bit microcontroller family with extended memory

Product data

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13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still
be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In
these situations reflow soldering is recommended. In these situations reflow
soldering is recommended.

13.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270

C depending on solder

paste material. The top-surface temperature of the packages should preferably be
kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal
results:

Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.

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For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle

to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250

C or

265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.

13.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320

13.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

Table 11:

Suitability of surface mount IC packages for wave and reflow soldering
methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5][6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

30 of 33

9397 750 12299

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217

C measured in the atmosphere of the reflow

oven. The package body peak temperature must be kept as low as possible.

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

9397 750 12299

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

Product data

Rev. 02 -- 13 November 2003

32 of 33

Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Licenses

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Purchase of Philips I

C components

Purchase of Philips I

C components conveys a license

under the Philips' I

C patent to use the components in the

C system provided the system conforms to the I

specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 13 November 2003

Document order number: 9397 750 12299

Contents

Philips Semiconductors

P89C669

80C51 8-bit microcontroller family with extended memory

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2

Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.3

Complete features . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

3.1

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

6.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.1

Plastic leaded chip carrier . . . . . . . . . . . . . . . . 6

6.1.2

Plastic low profile quad flat package. . . . . . . . . 7

6.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional description . . . . . . . . . . . . . . . . . . 11

7.1

Flash memory description . . . . . . . . . . . . . . . 11

7.2

Memory arrangement . . . . . . . . . . . . . . . . . . . 12

7.3

Special function registers . . . . . . . . . . . . . . . . 12

7.4

Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Static characteristics. . . . . . . . . . . . . . . . . . . . 18

Dynamic characteristics . . . . . . . . . . . . . . . . . 19

10.1

Explanation of AC symbols . . . . . . . . . . . . . . . 21

10.2

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 22

Test information . . . . . . . . . . . . . . . . . . . . . . . . 24

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28

13.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28

13.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29

13.5

Package related soldering information . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 32

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89C669FA

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89C669FA