P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM

Rev. 03 -- 17 December 2004

Product data

General description

The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin
packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC912/913/914 in order
to reduce component count, board space, and system cost.

Features

1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.

128-byte RAM data memory.

Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.

23-bit system timer that can also be used as a Real-Time clock.

Two analog comparators with selectable inputs and reference source.

Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC913, P89LPC914).

SPI communication port.

Internal RC oscillator (factory calibrated to

1 %) option allows operation without

external oscillator components. The RC oscillator option is selectable and fine
tunable.

2.4 V to 3.6 V V

operating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

Up to 12 I/O pins when using internal oscillator and reset options.

Additional features

14-pin TSSOP packages.

A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz
(167 ns to 333 ns at 12 MHz). This is six times the performance of the standard
80C51 running at the same clock frequency. A lower clock frequency for the same
performance results in power savings and reduced EMI.

In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

2 of 63

9397 750 14468

Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.

Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.

Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.

Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1

A (total Power-down with voltage comparators disabled).

Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.

Configurable on-chip oscillator with frequency range options selected by user
programmed Flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz (P89LPC912,
P89LPC913).

Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.

Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.

Port `input pattern match' detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.

LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.

Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.

Only power and ground connections are required to operate the
P89LPC912/913/914 when internal reset option is selected.

Four interrupt priority levels.

Four keypad interrupt inputs.

Second data pointer.

Schmitt trigger port inputs.

Emulation support.

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

8 of 63

9397 750 14468

6.2 Pin description

Table 3:

P89LPC912 pin description

Symbol

Pin

Type

Description

P0.2, P0.4 to
P0.6

I/O

Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input A.

KBI2 -- Keyboard input 2.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input A.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

I/O

P0.6 -- Port 0 bit 6.

CMP1 -- Comparator 1 output.

KBI6 -- Keyboard input 6.

P1.2, P1.5

I/O
(P1.2);
I (P1.5)

Port 1: Port 1 is a 2-bit I/O port with P1.2 having a user-configurable output type as
noted below. During reset Port 1 latches are configured in the input only mode with
the internal pull-up disabled. The operation of the P1.2 input and outputs depends
upon the port configuration selected. Refer to

Section 9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details. P1.2 is an open drain when used as

an output. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.2 -- Port 1 bit 2. (Open drain when used as an output.)

I/O

T0 -- Timer/counter 0 external count input or overflow output. (Open drain when used
as outputs.).

P1.5 -- Port 1 bit 5. (Input only.)

RST -- External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the reset
input function of P1.5 must be enabled. An external circuit is required to hold
the device in reset at power-up until V

has reached its specified level. When

system power is removed V

will fall below the minimum specified operating

voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V

falls below the minimum specified operating voltage.

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

9 of 63

9397 750 14468

P2.2 to P2.5

I/O

Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

I/O

P2.2 -- Port 2 bit 2.

I/O

MOSI -- SPI master out slave in. When configured as master, this pin is output, when
configured as slave, this pin is input.

I/O

P2.3 -- Port 2 bit 3.

I/O

MISO -- SPI master in slave out. When configured as master, this pin is input, when
configured as slave, this pin is output.

I/O

P2.4 -- Port 2 bit 4.

SS -- SPI Slave select.

I/O

P2.5 -- Port 2 bit 5.

I/O

SPICLK -- SPI clock. When configured as master, this pin is output, when configured
as slave, this pin is input.

P3.0 to P3.1

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

I/O

P3.0 -- Port 3 bit 0.

XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).

CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the Real-Time clock/system timer.

I/O

P3.1 -- Port 3 bit 1.

XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the Real-Time clock/system timer.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.

Table 3:

P89LPC912 pin description

...continued

Symbol

Pin

Type

Description

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

10 of 63

9397 750 14468

Table 4:

P89LPC913 pin description

Symbol

Pin

Type

Description

P0.2,
P0.4 to P0.6

I/O

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input A.

KBI2 -- Keyboard input 2.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input A.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

I/O

P0.6 -- Port 0 bit 6.

CMP1 -- Comparator 1 output.

KBI6 -- Keyboard input 6.

P1.0, P1.1,
P1.5

I/O
(P1.0,
P1.1);
I (P1.5)

Port 1: Port 1 is a 3-bit I/O port with a user-configurable output type, except for P1.5
noted below. During reset Port 1 latches are configured in the input only mode with
the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs
and outputs depends upon the port configuration selected. Each of the configurable
port pins are programmed independently. Refer to

Section 9.11.1 "Port

configurations"

and

Table 13 "DC electrical characteristics"

for details. P1.5 is input

only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.0 -- Port 1 bit 0.

TxD -- Transmitter output for the serial port.

I/O

P1.1 -- Port 1 bit 1.

RxD -- Receiver input for the serial port.

P1.5 -- Port 1 bit 5 (input only).

RST -- External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V

has reached its specified level.

When system power is removed V

will fall below the minimum specified

operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V

falls below the minimum specified operating voltage.

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

11 of 63

9397 750 14468

P2.2, P2.3,
P2.5

I/O

Port 2: Port 2 is a 3-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below:

I/O

P2.2 -- Port 2 bit 2.

I/O

MOSI -- SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input.

I/O

P2.3 -- Port 2 bit 3.

I/O

MISO -- SPI master in slave out. When configured as master, this pin is input, when
configured as slave, this pin is output.

I/O

P2.5 -- Port 2 bit 5.

I/O

SPICLK -- SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input.

P3.0 to P3.1

I/O

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

I/O

P3.0 -- Port 3 bit 0.

XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).

I/O

P3.1 -- Port 3 bit 1.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.

Table 4:

P89LPC913 pin description

...continued

Symbol

Pin

Type

Description

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 -- 17 December 2004

12 of 63

9397 750 14468

Table 5:

P89LPC914 pin description

Symbol

Pin

Type

Description

P0.2,
P0.4 to P0.6

I/O

Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

9.11.1 "Port configurations"

and

Table 13 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input A.

KBI2 -- Keyboard input 2.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input A.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

I/O

P0.6 -- Port 0 bit 6.

CMP1 -- Comparator 1 output.

KBI6 -- Keyboard input 6.

P1.0 to P1.2,
P1.5

I/O
(P1.0 to
P1.2);
I (P1.5)

Port 1: Port 1 is a 4-bit I/O port with a user-configurable output type, except for
three pins noted below. During reset Port 1 latches are configured in the input only
mode with the internal pull-up disabled. The operation of the configurable Port 1
pins as inputs and outputs depends upon the port configuration selected. Each of
the configurable port pins are programmed independently. Refer to

Section 9.11.1

"Port configurations"

and

Table 13 "DC electrical characteristics"

for details. P1.2 is

an open drain when used as an output. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.0 -- Port 1 bit 0.

TxD -- Transmitter output for the serial port.

I/O

P1.1 -- Port 1 bit 1.

RxD -- Receiver input for the serial port.

I/O

P1.2 -- Port 1 bit 2. (Open drain when used as an output.)

I/O

T0 -- Timer/counter 0 external count input or overflow output. (Open drain when
used as outputs.)

P1.5 -- Port 1 bit 5 (input only).

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Philips Semiconductor

P89LPC912/913/914

8-bit micr

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Table 7:

P89LPC912 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

ENT0

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

CMP1

Comparator 1 control register

ACH

CE1

CN1

OE1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CN2

CO2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer high

83H

00000000

DPL

Data pointer low

82H

00000000

FMADRH

Program Flash address high

E7H

00000000

FMADRL

Program Flash address low

E6H

00000000

FMCON

Program Flash Control (Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control (Write)

FMCMD.

FMCMD.5 FMCMD.

FMCMD.

FMDATA

Program Flash data

E5H

00000000

Bit address

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

ESPI

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PT1

PT0

[1]

x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRTH

PBOH

PT1H

PT0H

[1]

x0000000

Bit address

IP1*

Interrupt priority 1

F8H

PSPI

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 high

F7H

PSPIH

PCH

PKBIH

[1]

00x00000

KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

Philips Semiconductor

P89LPC912/913/914

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KBMASK

Keypad interrupt mask register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMP1/

KB6

CMPREF/

KB5

CIN1A/

KB4

CIN2A/

KB2

[1]

Bit address

P1*

Port 1

90H

RST

[1]

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

[1]

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.2)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.6)

(P0M2.5)

(P0M2.4)

(P0M2.2)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.2)

[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.2)

[1]

00x0xx00

P2M1

Port 2 output mode 1

A4H

(P2M1.5)

(P2M1.4) (P2M1.3) (P2M1.2)

11111111

P2M2

Port 2 output mode 2

A5H

(P2M2.5)

(P2M2.4) (P2M2.3) (P2M2.2)

00000000

P3M1

Port 3 output mode 1

B1H

(P3M1.1) (P3M1.0) 03

[1]

xxxxxx11

P3M2

Port 3 output mode 2

B2H

(P3M2.1) (P3M2.0) 00

[1]

xxxxxx00

PCON

Power control register

87H

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

SPPD

[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.2

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_WD

R_SF

R_EX

[2]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1][5]

011xxx00

RTCH

Real-time clock register high

D2H

[5]

00000000

RTCL

Real-time clock register low

D3H

[5]

00000000

Stack pointer

81H

00000111

Table 7:

P89LPC912 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductor

P89LPC912/913/914

8-bit micr

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.

[3]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[4]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[5]

The only reset source that affects these SFRs is power-on reset.

SPCTL

SPI control register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00000100

SPSTAT

SPI status register

E1H

SPIF

WCOL

00xxxxxx

SPDAT

SPI data register

E3H

00000000

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T0M2

xxx0xxx0

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 high

8CH

00000000

TH1

Timer 1 high

8DH

00000000

TL0

Timer 0 low

8AH

00000000

TL1

Timer 1 low

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[4] [5]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[3] [5]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 7:

P89LPC912 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductor

P89LPC912/913/914

8-bit micr

ocontr

oller

s with tw

o-c

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k 80C51 core

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. 2004. All r

ights reser

ed.

Pr
oduct data

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03 -- 17 December 2004

19 of 63

Table 8:

P89LPC913 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

BRGR0

[2]

Baud rate generator rate low

BEH

00000000

BRGR1

[2]

Baud rate generator rate high

BFH

00000000

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

[6]

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CN1

OE1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CN2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer high

83H

00000000

DPL

Data pointer low

82H

00000000

FMADRH

Program Flash address high

E7H

00000000

FMADRL

Program Flash address low

E6H

00000000

FMCON

Program Flash Control (Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control (Write)

FMCMD.

FMCMD.5 FMCMD.

FMCMD.

FMDATA

Program Flash data

E5H

00000000

Bit address

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EST

ESPI

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PT0

[1]

x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRTH

PBOH

PSH/

PSRH

PT1H

PT0H

[1]

x0000000

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Bit address

IP1*

Interrupt priority 1

F8H

PST

PSPI

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 high

F7H

PSTH

PSPIH

PCH

PKBIH

[1]

00x00000

KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

KBMASK

Keypad interrupt mask register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMP1/

KB6

CMPREF/

KB5

CIN1A/

KB4

CIN2A/

KB2

[1]

Bit address

P1*

Port 1

90H

RST

RxD

TxD

[1]

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

[1]

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.2)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.6)

(P0M2.5)

(P0M2.4)

(P0M2.2)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.1) (P1M1.0) D3

[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.1) (P1M2.0) 00

[1]

00x0xx00

P2M1

Port 2 output mode 1

A4H

(P2M1.5)

(P2M1.3) (P2M1.2)

11111111

P2M2

Port 2 output mode 2

A5H

(P2M2.5)

(P2M2.3) (P2M2.2)

00000000

P3M1

Port 3 output mode 1

B1H

(P3M1.1) (P3M1.0) 03

[1]

xxxxxx11

P3M2

Port 3 output mode 2

B2H

(P3M2.1) (P3M2.0) 00

[1]

xxxxxx00

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

SPPD

SPD

[1]

00000000

Table 8:

P89LPC913 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.2

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1][6]

011xxx00

RTCH

Real-time clock register high

D2H

[6]

00000000

RTCL

Real-time clock register low

D3H

[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial port data buffer register

99H

xxxxxxxx

Bit address

SCON

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

SSTAT

Serial port extended status
register

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Stack pointer

81H

00000111

SPCTL

SPI control register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00000100

SPSTAT

SPI status register

E1H

SPIF

WCOL

00xxxxxx

SPDAT

SPI data register

E3H

00000000

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 high

8CH

00000000

TH1

Timer 1 high

8DH

00000000

TL0

Timer 0 low

8AH

00000000

TL1

Timer 1 low

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

Table 8:

P89LPC913 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 8:

P89LPC913 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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Table 9:

P89LPC914 Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

EBRR

ENT0

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

BRGR0

[2]

Baud rate generator rate low

BEH

00000000

BRGR1

[2]

Baud rate generator rate high

BFH

00000000

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

[6]

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CN1

OE1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CN2

CO2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer high

83H

00000000

DPL

Data pointer low

82H

00000000

FMADRH

Program Flash address high

E7H

00000000

FMADRL

Program Flash address low

E6H

00000000

FMCON

Program Flash Control (Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control (Write)

FMCMD.

FMCMD.5 FMCMD.

FMCMD.

FMCMD.1

FMCMD.

FMDATA

Program Flash data

E5H

00000000

Bit address

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

ET0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EST

ESPI

EKBI

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PT0

[1]

x0000000

IP0H

Interrupt priority 0 high

B7H

PWDRTH

PBOH

PSH/

PSRH

PT1H

PT0H

[1]

x0000000

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Bit address

IP1*

Interrupt priority 1

F8H

PST

PSPI

PKBI

[1]

00x00000

IP1H

Interrupt priority 1 high

F7H

PSTH

PSPIH

PCH

PKBIH

[1]

00x00000

KBCON

Keypad control register

94H

PATN_SEL

KBIF

[1]

xxxxxx00

KBMASK

Keypad interrupt mask register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

CMP1/

KB6

CMPREF/

KB5

CIN1A/

KB4

CIN2A/

KB2

[1]

Bit address

P1*

Port 1

90H

RST

RxD

TxD

[1]

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.2)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.6)

(P0M2.5)

(P0M2.4)

(P0M2.2)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.2)

(P1M1.1)

(P1M1.0) D3

[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.2)

(P1M2.1)

(P1M2.0) 00

[1]

00x0xx00

P2M1

Port 2 output mode 1

A4H

(P2M1.5)

(P2M1.4) (P2M1.3) (P2M1.2)

11111111

P2M2

Port 2 output mode 2

A5H

(P2M2.5)

(P2M2.4) (P2M2.3) (P2M2.2)

00000000

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

SPPD

SPD

[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.2

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1][6]

011xxx00

RTCH

Real-time clock register high

D2H

[6]

00000000

RTCL

Real-time clock register low

D3H

[6]

00000000

SADDR

Serial port address register

A9H

00000000

Table 9:

P89LPC914 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any of them is written if BRGEN = 1, result is unpredictable.

[3]

The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial port data buffer register

99H

xxxxxxxx

Bit address

SCON

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

SSTAT

Serial port extended status
register

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Stack pointer

81H

00000111

SPCTL

SPI control register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00000100

SPSTAT

SPI status register

E1H

SPIF

WCOL

00xxxxxx

SPDAT

SPI data register

E3H

00000000

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T0M2

xxx0xxx0

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

00000000

TH0

Timer 0 high

8CH

00000000

TH1

Timer 1 high

8DH

00000000

TL0

Timer 0 low

8AH

00000000

TL1

Timer 1 low

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 9:

P89LPC914 Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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Functional description

Remark: Please refer to the

P89LPC912/913/914 User's Manual for a more detailed

functional description.

9.1 Enhanced CPU

The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at 6 times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles,
and most instructions execute in one or two machine cycles.

9.2 Clocks

9.2.1

Clock definitions

The P89LPC912/913/914 device has several internal clocks as defined below:

OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see

Figure 10

, and

) and can also be optionally divided to a

slower frequency (see

Section 9.7 "CPU Clock (CCLK) modification: DIVM register"

Note: f

osc

is defined as the OSCCLK frequency.

CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).

RCCLK -- The internal 7.373 MHz RC oscillator output.

PCLK -- Clock for the various peripheral devices and is CCLK/2

9.2.2

CPU clock (OSCCLK)

The P89LPC912/913/914 provide user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the FLASH is programmed and
include an on-chip Watchdog oscillator and an on-chip RC oscillator.

In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an
external crystal or an external clock source. The crystal oscillator can be optimized
for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

9.2.3

Low speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.

9.2.4

Medium speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.

9.2.5

High speed oscillator option (P89LPC912, P89LPC913)

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V

has

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reached its specified level. When system power is removed V

will fall below

the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V

falls below the minimum

specified operating voltage.

9.2.6

Clock output (P89LPC912, P89LPC913)

The P89LPC912 supports a user selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC912. This output is enabled by the ENCLK bit in the TRIM register. The
frequency of this clock output is

that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

9.3 On-chip RC oscillator option

The P89LPC912/913/914 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz,

2.5 %.

End-user applications can write to the TRIM register to adjust the on-chip RC
oscillator to other frequencies.

9.4 Watchdog oscillator option

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.

9.5 External clock input option (P89LPC912, P89LPC913)

In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V

has

reached its specified level. When system power is removed V

will fall below

the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V

falls below the minimum

specified operating voltage.

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9.6 CPU Clock (CCLK) wake-up delay

The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it
stabilizes, depending to the clock source used. If the clock source is any of the three
crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus
60 to 100

s. If the clock source is either the internal RC oscillator, Watchdog

oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100

9.7 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.

9.8 Low power select

The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1'
to lower the power consumption further. On any reset, CLKLP is `0' allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.

9.9 Memory organization

The various P89LPC912/913/914 memory spaces are as follows:

DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.

Fig 12. Block diagram of oscillator control (P89LPC914).

002aaa483

RTC

CPU

WDT

SPI

DIVM

CCLK

OSCCLK

PCLK

TIMER 0 and

TIMER 1

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

Oscillator

clock

CPU

clock

Peripheral clock

UART

BAUD RATE

GENERATOR

CCLK

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SFR

Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.

CODE

64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.

9.10 Interrupts

The P89LPC912/913/914 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources.

The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.

The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and
1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,
Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.

9.10.1

External interrupt inputs

The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an
external interrupt input.

If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the
interrupt will cause the processor to wake-up and resume operation. Refer to

Section

9.13 "Power reduction modes"

for details.

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[1]

Required for operation above 12 MHz.

The P89LPC914 has 3 I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O
pins available depends on the reset option chosen, as shown in

Table 11

[1]

Required for external clock frequency above 12 MHz.

9.11.1

Port configurations

Except as listed below, every I/O pin on the P89LPC912/913/914 may be configured
by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional
(standard 80C51 port outputs), push-pull, open drain, and input-only. Two
configuration registers for each port select the output type for each port pin.

P1.5/RST can only be an input and cannot be configured.

P1.2/T0 may only be configured to be either input-only or open drain (P89LPC912,
P89LPC914).

9.11.2

Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC912/913/914 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to V

, causing extra power consumption. Therefore, applying

5 V in quasi-bidirectional mode is discouraged.

Table 10:

Number of I/O pins available (P89LPC912, P89LPC913)

Clock source

Reset option

Number of
I/O pins
(14-pin
package)

On-chip oscillator or watchdog
oscillator

No external reset (except during
power-up)

External RST pin supported

External clock input

No external reset (except during
power-up)

External RST pin supported

Low/medium/high speed oscillator
(external crystal or resonator)

No external reset (except during
power-up)

External RST pin supported

[1]

Table 11:

Number of I/O pins available (P89LPC914)

Reset option

Number of I/O pins
(14-pin package)

No external reset (except during power-up)

External RST pin supported

[1]

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A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

9.11.3

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic `0'. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to V

An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

9.11.4

Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.

9.11.5

Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic `1'. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.

9.11.6

Port 0 analog functions

The P89LPC912/913/914 incorporates two Analog Comparators. In order to give the
best analog function performance and to minimize power consumption, pins that are
being used for analog functions must have the digital outputs and digital inputs
disabled.

Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in

Section 9.11.4 "Input-only configuration"

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On
any reset, the PT0AD bits default to `0's to enable digital functions.

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9.11.7

Additional port features

After power-up, all pins are in Input-Only mode. After power-up all I/O pins except
P1.5, may be configured by software.

Pin P1.5 is input only.

P1.2/T0 is configurable for either input-only or open-drain (P89LPC912,
P89LPC914).

Every output on the P89LPC912/913/914 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which
must not be exceeded. Please refer to

Table 13 "DC electrical characteristics"

for

detailed specifications.

All port pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.

9.12 Power monitoring functions

The P89LPC912/913/914 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.

9.12.1

Brownout detection

The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however, it may alternatively be configured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the brownout condition occurs when V

falls below

the brownout trip voltage, V

(see

Table 13 "DC electrical characteristics"

), and is

negated when V

rises above V

. If the P89LPC912/913/914 device is to operate

with a power supply that can be below 2.7 V, BOE should be left in the
unprogrammed state so that the device can operate at 2.4 V, otherwise continuous
brownout reset may prevent the device from operating.

For correct activation of Brownout detect, the V

rise and fall times must be

observed. Please see

Table 13 "DC electrical characteristics"

for specifications.

9.12.2

Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.

9.13 Power reduction modes

The P89LPC912/913/914 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.

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9.13.1

Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.

9.13.2

Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC912/913/914 exits Power-down mode via any reset, or certain interrupts.
In Power-down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage V

RAM

. This retains the RAM contents at the point where

Power-down mode was entered. SFR contents are not guaranteed after V

has

been lowered to V

RAM

, therefore it is highly recommended to wake up the processor

via reset in this case. V

must be raised to within the operating range before the

Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.

9.13.3

Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.

9.14 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.

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Reset can be triggered from the following sources:

External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz.)

Power-on detect

Brownout detect

Watchdog Timer

Software reset

UART break character detect reset (P80LPC913, P89LPC914).

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a `0' to the corresponding bit. More than one flag bit
may be set:

During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.

For any other reset, previously set flag bits that have not been cleared will remain
set.

9.15 Timers/counters 0 and 1

The P89LPC912/913/914 devices have two general purpose counter/timers which
are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to
automatically toggle the T0 pin upon timer overflow has been added (P89LPC912,
P89LPC914). In the `Timer' function, the register is incremented every machine cycle.
In the `Counter' function, the register of Timer 0 is incremented in response to a
1-to-0 transition at its external input pin, T0. This external input is sampled once very
machine cycle.

Timer 0 has four operating modes (modes 0, 1, 2, and 3) on the P89LPC913).

Timer 0 has five operating modes (modes 0, 1, 2, 3, and 6 on the P89LPC912 and
P89LPC914.

Timer 1 has four operating modes (modes 0, 1, 2, and 3) on all devices. Modes 0, 1,
and 2 are the same for both Timers/Counters. Mode 3 is different.

9.15.1

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

9.15.2

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

9.15.3

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.

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9.15.4

Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

9.15.5

Mode 6 (P89LPC912, P89LPC914)

In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.

9.15.6

Timer overflow toggle output (P89LPC912, P89LPC914)

Timers 0 can be configured to automatically toggle the T0 output whenever a timer
overflow occurs. The same device pins that are used for the T0 count input is also
used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.

9.16 Real-Time clock/system timer

The P89LPC912/913/914 devices have a simple Real-Time clock that allows a user
to continue running an accurate timer while the rest of the device is powered-down.
The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is
a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all `0's, the counter will be reloaded again and the RTCF
flag will be set.

On the P89LPC914 the clock source for this counter is the CPU clock (CCLK). On the
P89LPC912 and P89LPC913 devices, the clock source for this counter can either be
the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not
being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then
the RTC will use CCLK as its clock source.

Only power-on reset will reset the Real-Time clock and its associated SFRs to the
default state.

9.17 UART (P89LPC913, P89LPC914)

The P89LPC913 and P89LPC914 devices have an enhanced UART that is
compatible with the conventional 80C51 UART except that Timer 2 overflow cannot
be used as a baud rate source. The P89LPC913 does include an independent Baud
Rate Generator. The baud rate can be selected from the oscillator (divided by a
constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to
the baud rate generation, enhancements over the standard 80C51 UART include
Framing Error detection, automatic address recognition, selectable double buffering
and several interrupt options. The UART can be operated in 4 modes: shift register,
8-bit UART, 9-bit UART, and CCLK/32 or CCLK/16.

9.17.1

Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at

of the CPU clock

frequency.

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9.17.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical `0'), 8 data bits (LSB first), and a stop bit (logical `1'). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator
(described in

Section 9.17.5 "Baud rate generator and selection"

9.17.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical `0'),
8 data bits (LSB first), a programmable 9

data bit, and a stop bit (logical `1'). When

data is transmitted, the 9

data bit (TB8 in SCON) can be assigned the value of `0' or

`1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9

data bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either

the CCLK frequency, as determined by the SMOD1 bit in PCON.

9.17.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical `0'), 8 data bits (LSB first), a programmable 9

data bit, and a stop bit

(logical `1'). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or
the Baud Rate Generator (described in section

Section 9.17.5 "Baud rate generator

and selection"

9.17.5

Baud rate generator and selection

The P89LPC913 and P89LPC914 devices have an independent Baud Rate
Generator. The baud rate is determined by a baud-rate preprogrammed into the
BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that
works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can
be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see

Figure 15

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.

9.17.6

Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is `1', framing errors can be made available in SCON.7, respectively. If
SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is `0'.

Fig 15. Baud rate sources for UART (Modes 1, 3).

Baud Rate Modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

002aaa419

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9.17.7

Break detect

Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device.

9.17.8

Double buffering

The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = `0'), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = `0').

9.17.9

Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.

9.17.10

The 9

bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.

9.18 Serial Peripheral Interface (SPI)

P89LPC912/913/914 provides another high-speed serial communication
interface--the SPI interface. SPI is a full-duplex, high-speed, synchronous
communication bus with two operation modes: Master mode and Slave mode. Up to
4.5 Mbit/s can be supported in Master or 3 Mbit/s in Slave mode. It has a Transfer
Completion Flag and Write Collision Flag Protection.

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9.19 Analog comparators

Two analog comparators are provided on the P89LPC912/913/914. Input and output
options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logical `1' when the positive input is
greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be configured to
cause an interrupt when the output value changes. Comparator 1 may be output to a
port pin.

The overall connections to both comparators are shown in

Figure 21

. The

comparators function to V

= 2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator
interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate
interrupt service.

9.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as V

REF

, is 1.23 V

10 %.

9.21 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. If both comparators enable interrupts, after entering the
interrupt service routine, the user needs to read the flags to determine which
comparator caused the interrupt.

Possible comparator configurations are shown in

Figure 22

Fig 21. Comparator input and output connections.

Comparator 1

CN1

(P0.4) CIN1A

(P0.5) CMPREF

VREF

OE1

Change Detect

CO1

CMF1

Interrupt

002aaa496

CMP1 (P0.6)

Change Detect

CMF2

Comparator 2

CN2

(P0.2) CIN2A

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9.22 Comparator and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down
mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of
the comparator output state will generate an interrupt and wake up the processor. If
the comparator output to a pin is enabled, the pin should be configured in the
push-pull mode in order to obtain fast switching times while in Power-down mode.
The reason is that with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin does not take
place.

Comparators consume power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparators via PCONA.5, or put the device in Total Power-down mode.

9.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.

CN1, OE1 = 0 0

CN1, OE1 = 0 1

CN1, OE1 = 1 0

CN1, OE1 = 1 1

CN2 = 0

CN2 = 1

Fig 22. Comparator configurations.

CIN1A

CMPREF

002aaa490

CO1

CIN1A

CMPREF

002aaa491

CO1

CMP1

CIN1A

VREF (1.23 V)

002aaa492

CO1

CIN1A

VREF (1.23 V)

002aaa493

CO1

CMP1

CIN2A

CMPREF

002aaa494

CO2

CIN2A

VREF (1.23 V)

002aaa495

CO2

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In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery-powered systems that need to carefully
manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.

9.24 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt.

Figure 23

shows the

watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
a few

s to a few seconds. Please refer to the

P89LPC912/913/914 User's Manual for

more details.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 23. Watchdog timer in Watchdog mode (WDTE = `1').

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

CONTROL REGISTER

PRESCALER

002aaa423

SHADOW
REGISTER
FOR WDCON

8-BIT DOWN

COUNTER

WDL (C1H)

Watchdog

oscillator

PCLK

MOV WFEED1, #0A5H
MOV WFEED2, #05AH

RESET
see note (1)

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9.25 Additional features

9.25.1

Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.

9.25.2

Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic `0' so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.

9.26 Flash program memory

9.26.1

General description

The P89LPC912/913/914 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP) and byte erase allows code memory to be used for non-volatile
data storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC912/913/914 Flash reliably stores memory
contents even after 100,000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. The P89LPC912/913/914 uses
V

as the supply voltage to perform the Program/Erase algorithms.

9.26.2

Features

Programming and erase over the full operating voltage range.

Byte-erase allowing code memory to be used for data storage.

Read/Programming/Erase using ICP.

Any flash program/erase operation in 2 ms.

Programming with industry-standard commercial programmers.

Programmable security for the code in the Flash for each sector.

More than 100,000 minimum erase/program cycles for each byte.

10-year minimum data retention.

9.26.3

Flash organization

The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each
sector can be further divided into 16-byte pages. In addition to sector erase, page
erase, and byte erase, a 16-byte page register is included which allows from
1 to 16 bytes of a given page to be programmed at the same time, substantially
reducing overall programming time. In addition, erasing and reprogramming of
user-programmable configuration bytes including UCFG1, the Boot Status Bit, and
the Boot Vector is supported.

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9.26.4

Flash programming and erasing

Different methods of erasing or programming of the Flash are available. The Flash
may be programmed or erased in the end-user application (IAP-Lite) under control of
the application's firmware. Another option is to use the In-Circuit Programming (ICP)
mechanism. This ICP system provides for programming through a serial clock- serial
data interface using a commercially available EPROM programmer which supports
this device. This device does not provide for direct verification of code memory
contents. Instead this device provides a 32-bit CRC result on either a sector or the
entire 1 kB of user code space.

9.26.5

In-circuit programming (ICP)

In-Circuit Programming is performed without removing the microcontroller from the
system. The In-Circuit Programming facility consists of internal hardware resources
to facilitate remote programming of the P89LPC912/913/914 through a two-wire
serial interface. The Philips In-Circuit Programming facility has made in-circuit
programming in an embedded application, using commercially available
programmers, possible with a minimum of additional expense in components and
circuit board area. The ICP function uses five pins. Only a small connector (with V

, RST, clock, and data signals) needs to be available to interface your application

to a commercial programmer in order to use this feature. Additional details may be
found in the

P89LPC912/913/914 User's Manual.

9.26.6

In-application programming (IAP-Lite)

In-Application Programming is performed in the application under the control of the
microcontroller's firmware. The IAP-Lite facility consists of internal hardware
resources to facilitate programming and erasing. The Philips In-Application
Programming Lite has made in-application programming in an embedded application
possible without additional components. This is accomplished through the use of four
SFRs consisting of a control/status register, a data register, and two address
registers. Additional details may be found in the

P89LPC912/913/914 User's Manual.

9.26.7

Using flash as data storage

The Flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a
MOVC instruction is not allowed to read code memory contents of a secured sector).
Thus any byte in a non-secured sector may be used for non-volatile data storage.

9.26.8

User configuration bytes

Some user-configurable features of the P89LPC912/913/914 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the Flash byte UCFG1. Please see the
P89LPC912/913/914 User's Manual for additional details.

9.26.9

User sector security bytes

There are four User Sector Security Bytes, each corresponding to one sector. Please
see the

P89LPC912/913/914 User's Manual for additional details.

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10. Limiting values

[1]

The following applies to Limiting values:

a) Stresses above those listed under

Table 12

may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in

Table 13 "DC electrical characteristics"

Table 14 "AC

characteristics"

and

Table 15 "AC characteristics (P89LPC912, P89LPC913)"

of this specification are not implied.

b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless

otherwise noted.

Table 12:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

Parameter

Conditions

Min

Max

Unit

amb(bias)

operating bias ambient temperature

+125

stg

storage temperature range

+150

xtal

voltage on XTAL1, XTAL2 pin to V

as applicable

+ 0.5

voltage on any other pin (except
XTAL1, XTAL2) to V

0.5

+5.5

OH(I/O)

HIGH-level output current per I/O pin

OL(I/O)

LOW-level output current per I/O pin

I/O(tot)(max)

maximum total I/O current

120

tot(pack)

total power dissipation per package

based on package heat
transfer, not device power
consumption

1.5

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11. Static characteristics

Table 13:

DC electrical characteristics

= 2.4 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

[1]

Max

Unit

DD(oper)

power supply current,
operating (P89LPC912,
P89LPC913)

3.6 V; 12 MHz

[2]

3.6 V; 18 MHz

[2]

DD(idle)

power supply current, Idle
mode (P89LPC912,
P89LPC913)

3.6 V; 12 MHz

[2]

1.5

5.6

3.6 V; 18 MHz

[2]

DD(oper)

power supply current,
operating (P89LPC914)

3.6 V; 7.373 MHz

[3]

DD(idle)

power supply current, Idle
mode (P89LPC914)

3.6 V; 7.373 MHz

[3]

DD(PD)

Power supply current,
Power-down mode, voltage
comparators powered-down

3.6 V

[2][3]

DD(TPD)

Power supply current, Total
Power-down mode

3.6 V

[2][3]

(dV

/dt)

rise rate

mV/

(dV

/dt)

fall rate

mV/

RAM

RAM keep-alive voltage

1.5

th(HL)

negative-going threshold
voltage (Schmitt input)

0.22V

0.4V

th(LH)

positive-going threshold
voltage (Schmitt input)

0.6V

0.7V

hys

hysteresis voltage

0.2V

LOW-level output voltage,
all ports

= 20 mA

0.6

1.0

= 10 mA

0.3

0.5

= 3.2 mA

0.2

0.3

HIGH-level output voltage,
all ports

8 mA;

push-pull mode

1.0

3.2 mA;

push-pull mode

0.7

0.4

quasi-bidirectional mode

0.3

0.2

input/output pin capacitance

[4]

logical 0 input current,
all ports

= 0.4 V

[5]

input leakage current, all ports V

= V

or V

[6]

logical 1-to-0 transition
current, all ports

= 2.0 V at

= 3.6 V

[7][8]

450

RST

internal reset pull-up resistor

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12. Dynamic characteristics

Table 14:

AC characteristics

= 2.4 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 12 MHz

Unit

Min

Max

Min

Max

RCOSC

internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to

1 % at T

amb

= 25

7.189

7.557

7.189

7.557

MHz

WDOSC

internal Watchdog oscillator
frequency (nominal f = 400 kHz)

320

520

320

520

kHz

Crystal oscillator (P89LPC912, P89LPC913)

osc

oscillator frequency

MHz

CLCL

clock cycle

see

Figure 29

CLKP

CLKLP active frequency

MHz

Glitch filter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except
P1.5/RST

signal acceptance, any pin except
P1.5/RST

External clock (P89LPC912, P89LPC913)

CHCX

HIGH time

see

Figure 29

CLCL

CLCX

LOW time

see

Figure 29

CLCL

CHCX

CLCH

rise time

see

Figure 29

CHCL

fall time

see

Figure 29

Shift register (UART mode 0 - P89LPC913, P89LPC914)

XLXL

serial port clock cycle time

see

Figure 28

16 t

CLCL

1333

QVXH

output data set-up to clock rising
edge

see

Figure 28

13 t

CLCL

1083

XHQX

output data hold after clock rising
edge

see

Figure 28

CLCL

+ 20

103

XHDX

input data hold after clock rising
edge

see

Figure 28

DVXH

input data valid to clock rising edge see

Figure 28

150

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SPI interface

SPI

Operating frequency

2.0 MHz (Slave)

CCLK

2.0

MHz

3.0 MHz (Master)

CCLK

MHz

SPICYC

Cycle time

see

Figure 24

2.0 MHz (Slave)

CCLK

500

3.0 MHz (Master)

CCLK

SPILEAD

Enable lead time (Slave)

see

Figure 26

2.0 MHz

250

SPILAG

Enable lag time (Slave)

see

Figure 26

2.0 MHz

250

SPICLKH

SPICLK high time

see

Figure 24

Master

CCLK

340

Slave

CCLK

190

SPICLKL

SPICLK low time

see

Figure 24

Master

CCLK

340

Slave

CCLK

190

SPIDSU

Data set-up time (Master or Slave) see

Figure 24

100

SPIDH

Data hold time (Master or Slave)

see

Figure 24

100

SPIA

Access time (Slave)

see

Figure 26

120

SPIDIS

Disable time (Slave)

see

Figure 26

2.0 MHz

240

SPIDV

Enable to output data valid

see

Figure 24

2.0 MHz

240

3.0 MHz

167

SPIOH

Output data hold time

see

Figure 24

Table 14:

AC characteristics

...continued

= 2.4 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 12 MHz

Unit

Min

Max

Min

Max

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Table 15:

AC characteristics (P89LPC912, P89LPC913)

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

RCOSC

internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to

1 % at T

amb

= 25

7.189

7.557

7.189

7.557

MHz

WDOSC

internal Watchdog oscillator
frequency (nominal f = 400 kHz)

320

520

320

520

kHz

Crystal oscillator

osc

oscillator frequency

[2]

MHz

CLCL

clock cycle

see

Figure 29

CLKP

CLKLP active frequency

MHz

Glitch filter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except
P1.5/RST

signal acceptance, any pin except
P1.5/RST

External clock

CHCX

HIGH time

see

Figure 29

CLCL

CLCX

LOW time

see

Figure 29

CLCL

CHCX

CLCH

rise time

see

Figure 29

CHCL

fall time

see

Figure 29

SPI interface

SPI

Operating frequency

3.0 MHz (Slave)

CCLK

MHz

4.5 MHz (Master)

CCLK

4.5

MHz

SPICYC

Cycle time

see

Figure 24

3.0 MHz (Slave)

CCLK

333

4.5 MHz (Master)

CCLK

222

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SPILEAD

Enable lead time (Slave)

see

Figure 26

3.0 MHz

250

SPILAG

Enable lag time (Slave)

see

Figure 26

3.0 MHz

250

SPICLKH

SPICLK high time

see

Figure 24

Master

CCLK

111

Slave

CCLK

167

SPICLKL

SPICLK low time

see

Figure 24

Master

CCLK

111

Slave

CCLK

167

SPIDSU

Data set-up time (Master or Slave) see

Figure 24

100

SPIDH

Data hold time (Master or Slave)

see

Figure 24

100

SPIA

Access time (Slave)

see

Figure 26

SPIDIS

Disable time (Slave)

see

Figure 26

3.0 MHz

160

SPIDV

Enable to output data valid

see

Figure 24

3.0 MHz

160

4.5 MHz

111

SPIOH

Output data hold time

see

Figure 24

SPIR

Rise time

see

Figure 24

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

Table 15:

AC characteristics (P89LPC912, P89LPC913)

...continued

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

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[1]

Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.

[2]

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V

has reached its specified level. When system power is removed V

will fall below the

minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage.

SPIF

Fall time

see

Figure 24

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

Table 15:

AC characteristics (P89LPC912, P89LPC913)

...continued

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

Fig 24. SPI master timing (CPHA = 0).

tCLCL

tSPICLKH

tSPICLKL

Master LSB/MSB out

Master MSB/LSB out

tSPIDH

tSPIDSU

tSPICLKL

tSPICLKH

tSPIF

tSPIOH

tSPIDV

tSPIR

tSPIDV

tSPIF

tSPIR

SPICLK

(CPOL = 0)

(output)

002aaa156

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB in

MSB/LSB in

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Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

16. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

17. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

18. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 17 December 2004

Document order number: 9397 750 14468

Contents

Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.1

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1

Product comparison . . . . . . . . . . . . . . . . . . . . . . . . . 15

Special function registers. . . . . . . . . . . . . . . . . . . . . 15

Functional description . . . . . . . . . . . . . . . . . . . . . . . 26

9.1

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.1

Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.2

CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.3

Low speed oscillator option (P89LPC912,
P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.4

Medium speed oscillator option
(P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . 26

9.2.5

High speed oscillator option (P89LPC912,
P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.2.6

Clock output (P89LPC912, P89LPC913) . . . . . . . . . 27

9.3

On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 27

9.4

Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 27

9.5

External clock input option (P89LPC912,
P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.6

CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 29

9.7

CPU Clock (CCLK) modification: DIVM register . . . 29

9.8

Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.9

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 29

9.10

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.10.1

External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 30

9.11

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.11.1

Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.11.2

Quasi-bidirectional output configuration. . . . . . . . . . 32

9.11.3

Open-drain output configuration. . . . . . . . . . . . . . . . 33

9.11.4

Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 33

9.11.5

Push-pull output configuration . . . . . . . . . . . . . . . . . 33

9.11.6

Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 33

9.11.7

Additional port features . . . . . . . . . . . . . . . . . . . . . . 34

9.12

Power monitoring functions . . . . . . . . . . . . . . . . . . . 34

9.12.1

Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.12.2

Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.13

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 34

9.13.1

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.13.2

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.13.3

Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 35

9.14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.15

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 36

9.15.1

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.15.2

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.15.3

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.15.4

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.15.5

Mode 6 (P89LPC912, P89LPC914) . . . . . . . . . . . . . 37

9.15.6

Timer overflow toggle output (P89LPC912,
P89LPC914) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.16

Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 37

9.17

UART (P89LPC913, P89LPC914) . . . . . . . . . . . . . . 37

9.17.1

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.17.2

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.17.3

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.17.4

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.17.5

Baud rate generator and selection . . . . . . . . . . . . . . 38

9.17.6

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.17.7

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.17.8

Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.17.9

Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 39

9.17.10

The 9

bit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.18

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . 39

9.18.1

Typical SPI configurations. . . . . . . . . . . . . . . . . . . . . 41

9.19

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.20

Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 43

9.21

Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 43

9.22

Comparator and power reduction modes . . . . . . . . . 44

9.23

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 44

9.24

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.25

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.25.1

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.25.2

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.26

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 46

9.26.1

General description. . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.26.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.26.3

Flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.26.4

Flash programming and erasing . . . . . . . . . . . . . . . . 47

9.26.5

In-circuit programming (ICP). . . . . . . . . . . . . . . . . . . 47

9.26.6

In-application programming (IAP-Lite) . . . . . . . . . . . 47

9.26.7

Using flash as data storage . . . . . . . . . . . . . . . . . . . 47

9.26.8

User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 47

9.26.9

User sector security bytes . . . . . . . . . . . . . . . . . . . . 47

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 51

Comparator electrical characteristics . . . . . . . . . . . 59

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC912

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC912