P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core
4 kB/8 kB 3 V Flash with 256-byte data RAM

Rev. 05 -- 15 December 2004

Product data

General description

The P89LPC930/931 are single-chip microcontrollers designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC930/931 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC930/931 in order to reduce component count, board space, and system
cost.

Features

A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is 6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.

2.4 V to 3.6 V V

operating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.

Byte-erase allowing code memory to be used for data storage.

Flash program operation completes in 2 ms.

Flash erase operation completes in 2 ms.

256-byte RAM data memory.

Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.

Real-Time clock that can also be used as a system timer.

Two analog comparators with selectable inputs and reference source.

Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.

400 kHz byte-wide I

C-bus communication port.

SPI communication port.

Eight keypad interrupt inputs, plus two additional external interrupt inputs.

Four interrupt priority levels.

Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values.

Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 -- 15 December 2004

2 of 55

9397 750 14472

Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.

Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.

Configurable on-chip oscillator with frequency range and RC oscillator options
(selected by user programmed Flash configuration bits). The RC oscillator (factory
calibrated to

1 %) option allows operation without external oscillator

components. Oscillator options support frequencies from 20 kHz to the maximum
operating frequency of 18 MHz. The RC oscillator option is selectable and fine
tunable.

Programmable port output configuration options:

Quasi-bidirectional

Open drain

Push-pull

Input-only

Port `input pattern match' detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.

Second data pointer.

Schmitt trigger port inputs.

LED drive capability (20 mA) on all port pins. Maximum combined I/O current of
100 mA.

Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.

23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip
oscillator and reset options.

Only power and ground connections are required to operate the P89LPC930/931
using on-chip oscillator and on-chip reset options.

Serial Flash programming allows in-circuit production coding. Flash security bits
prevent reading of sensitive programs.

In-Application Programming of the Flash code memory. This allows changing the

code in a running application.

Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a low interrupt input starts execution). Typical Power-down
current is 1

A (total Power-down with voltage comparators disabled).

28-pin TSSOP package.

Emulation support.

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 -- 15 December 2004

6 of 55

9397 750 14472

5.2 Pin description

Table 3:

Pin description

Symbol

Pin

Type

Description

P0.0 - P0.7

3, 26, 25,
24, 23, 22,
20, 19

I/O

Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

8.11.1 "Port configurations"

and

Table 7 "DC electrical characteristics"

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

I/O

P0.0 -- Port 0 bit 0.

CMP2 -- Comparator 2 output.

KBI0 -- Keyboard input 0.

I/O

P0.1 -- Port 0 bit 1.

CIN2B -- Comparator 2 positive input B.

KBI1 -- Keyboard input 1.

I/O

P0.2 -- Port 0 bit 2.

CIN2A -- Comparator 2 positive input A.

KBI2 -- Keyboard input 2.

I/O

P0.3 -- Port 0 bit 3.

CIN1B -- Comparator 1 positive input B.

KBI3 -- Keyboard input 3.

I/O

P0.4 -- Port 0 bit 4.

CIN1A -- Comparator 1 positive input A.

KBI4 -- Keyboard input 4.

I/O

P0.5 -- Port 0 bit 5.

CMPREF -- Comparator reference (negative) input.

KBI5 -- Keyboard input 5.

I/O

P0.6 -- Port 0 bit 6.

CMP1 -- Comparator 1 output.

KBI6 -- Keyboard input 6.

I/O

P0.7 -- Port 0 bit 7.

I/O

T1 -- Timer/counter 1 external count input or overflow output.

KBI7 -- Keyboard input 7.

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 -- 15 December 2004

7 of 55

9397 750 14472

P1.0 - P1.7

18, 17, 12,
11, 10, 6,
5, 4

I/O, I

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for
three pins as noted below. During reset Port 1 latches are configured in the input only
mode with the internal pull-up disabled. The operation of the configurable Port 1 pins
as inputs and outputs depends upon the port configuration selected. Each of the
configurable port pins are programmed independently. Refer to

Section 8.11.1 "Port

configurations"

and

Table 7 "DC electrical characteristics"

for details. P1.2 - P1.3 are

open drain when used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

I/O

P1.0 -- Port 1 bit 0.

TxD -- Transmitter output for the serial port.

I/O

P1.1 -- Port 1 bit 1.

RXD -- Receiver input for the serial port.

I/O

P1.2 -- Port 1 bit 2 (open-drain when used as output).

I/O

T0 -- Timer/counter 0 external count input or overflow output (open-drain when used
as output).

I/O

SCL -- I

C serial clock input/output.

P1.3 -- Port 1 bit 3 (open-drain when used as output).

INT0 -- External interrupt 0 input.

I/O

SDA -- I

C serial data input/output.

P1.4 -- Port 1 bit 4.

INT1 -- External interrupt 1 input.

P1.5 -- Port 1 bit 5 (input only).

RST -- External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V

has reached its specified level.

When system power is removed V

will fall below the minimum specified

operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V

falls below the minimum specified operating voltage.

I/O

P1.6 -- Port 1 bit 6.

I/O

P1.7 -- Port 1 bit 7.

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 -- 15 December 2004

8 of 55

9397 750 14472

P2.0 - P2.7

1, 2, 13,
14, 15, 16,
27, 28

I/O

Port 2: Port 2 is a 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
This port is not available in 20-pin package and is configured automatically as
outputs to conserve power. The alternate functions for these pins must not be
enabled.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described below.

I/O

P2.0 -- Port 2 bit 0.

I/O

P2.1 -- Port 2 bit 1.

I/O

P2.2 -- Port 2 bit 2.

I/O

MOSI -- SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input.

I/O

P2.3 -- Port 2 bit 3.

I/O

MISO -- SPI master in slave out. When configured as master, this pin is input, when
configured as slave, this pin is output.

I/O

P2.4 -- Port 2 bit 4.

SS -- SPI Slave select.

I/O

P2.5 -- Port 2 bit 5.

I/O

SPICLK -- SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input.

I/O

P2.6 -- Port 2 bit 6.

I/O

P2.7 -- Port 2 bit 7.

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 -- 15 December 2004

9 of 55

9397 750 14472

[1]

Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.

P3.0 - P3.1

9, 8

I/O

Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to

Section

8.11.1 "Port configurations"

and

Table 7 "DC electrical characteristics"

for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

I/O

P3.0 -- Port 3 bit 0.

XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is
selected via the FLASH configuration).

CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer.

I/O

P3.1 -- Port 3 bit 1.

XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the real time clock/system timer.

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power Down modes.

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

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P89LPC930/931

8-bit micr

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Table 4:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

DPS

[1]

000000x0

Bit address

B register

F0H

00000000

BRGR0

[2]

Baud rate generator rate
LOW

BEH

00000000

BRGR1

[2]

Baud rate generator rate
HIGH

BFH

00000000

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

[6]

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CP1

CN1

OE1

CO1

CMF1

[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CP2

CN2

OE2

CO2

CMF2

[1]

xx000000

DIVM

CPU clock divide-by-M
control

95H

00000000

DPTR

Data pointer (2 bytes)

DPH

Data pointer HIGH

83H

00000000

DPL

Data pointer LOW

82H

00000000

FMADRH

Program Flash address HIGH

E7H

00000000

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash Control
(Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash Control
(Write)

FMCMD.

FMDATA

Program Flash data

E5H

00000000

I2ADR

C slave address register

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

00000000

Bit address

I2CON*

C control register

D8H

I2EN

STA

STO

CRSEL

x00000x0

I2DAT

C data register

DAH

Philips Semiconductor

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I2SCLH

Serial clock generator/SCL
duty cycle register HIGH

DDH

00000000

I2SCLL

Serial clock generator/SCL
duty cycle register LOW

DCH

00000000

I2STAT

C status register

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

11111000

Bit address

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EST

ESPI

EKBI

EI2C

[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PSH/

PSRH

PT1H

PX1H

PT0H

PX0H

[1]

x0000000

Bit address

IP1*

Interrupt priority 1

F8H

PST

PSPI

PKBI

PI2C

[1]

00x00000

IP1H

Interrupt priority 1 HIGH

F7H

PSTH

PSPIH

PCH

PKBIH

PI2CH

[1]

00x00000

KBCON

Keypad control register

94H

PATN
_SEL

KBIF

[1]

xxxxxx00

KBMASK

Keypad interrupt mask
register

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Bit address

P0*

Port 0

80H

T1/KB7

CMP1

/KB6

CMPREF

/KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

[1]

Bit address

P1*

Port 1

90H

RST

INT1

INT0/

SDA

T0/SCL

RXD

TXD

[1]

Bit address

P2*

Port 2

A0H

SPICLK

MISO

MOSI

[1]

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

[1]

Table 4:

Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

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P89LPC930/931

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P0M1

Port 0 output mode 1

84H

(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.7) (P1M1.6)

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.7) (P1M2.6)

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

[1]

00x0xx00

P2M1

Port 2 output mode 1

A4H

(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

[1]

11111111

P2M2

Port 2 output mode 2

A5H

(P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

00000000

P3M1

Port 3 output mode 1

B1H

(P3M1.1) (P3M1.0) 03

[1]

xxxxxx11

P3M2

Port 3 output mode 2

B2H

(P3M2.1) (P3M2.0) 00

[1]

xxxxxx00

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

I2PD

SPPD

SPD

[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

[1]

[6]

011xxx00

RTCH

Real-time clock register HIGH

D2H

[6]

00000000

RTCL

Real-time clock register LOW

D3H

[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial port data buffer register

99H

xxxxxxxx

Bit address

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

SSTAT

Serial port extended status
register

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Stack pointer

81H

00000111

SPCTL

SPI Control Register

E2H

SSIG

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

00000100

SPSTAT

SPI Status Register

E1H

SPIF

WCOL

00xxxxxx

SPDAT

SPI Data Register

E3H

00000000

Table 4:

Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductor

P89LPC930/931

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[1]

All ports are in input only (high impedance) state after power-up.

[2]

BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled '-') are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are '0's although they are unknown when read.

[3]

The RSTSRC register reflects the cause of the P89LPC930/931 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.

[4]

After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will
not affect WDTOF.

[5]

On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6]

The only reset source that affects these SFRs is power-on reset.

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T1M2

T0M2

xxx0xxx0

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

Table 4:

Special function registers

...continued

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

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Functional description

Remark: Please refer to the

P89LPC930/931 User's Manual for a more detailed

functional description.

8.1 Enhanced CPU

The P89LPC930/931 uses an enhanced 80C51 CPU which runs at 6 times the speed
of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1

Clock definitions

The P89LPC930/931 device has several internal clocks as defined below:

OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see

Figure 4

) and can also be optionally divided to a slower frequency

(see

Section 8.7 "CPU CLOCK (CCLK) modification: DIVM register"

Note: f

osc

is defined as the OSCCLK frequency.

CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).

RCCLK -- The internal 7.373 MHz RC oscillator output.

PCLK -- Clock for the various peripheral devices and is CCLK/2

8.2.2

CPU clock (OSCCLK)

The P89LPC930/931 provides several user-selectable oscillator options in generating
the CPU clock. This allows optimization for a range of needs from high precision to
lowest possible cost. These options are configured when the FLASH is programmed
and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator
using an external crystal, or an external clock source. The crystal oscillator can be
optimized for low, medium, or high frequency crystals covering a range from 20 kHz
to 12 MHz.

8.2.3

Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.

8.2.4

Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.

8.2.5

High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V

has

reached its specified level. When system power is removed V

will fall below

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the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V

falls below the minimum

specified operating voltage.

8.2.6

Clock output

The P89LPC930/931 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC930/931. This output is enabled by the ENCLK bit in the TRIM register. The
frequency of this clock output is

that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC930/931 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz,

1% at room

temperature. End-user applications can write to the Trim register to adjust the on-chip
RC oscillator to other frequencies.

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option

In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V

has

reached its specified level. When system power is removed V

will fall below

the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V

falls below the minimum

specified operating voltage.

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8.6 CPU CLock (CCLK) wake-up delay

The P89LPC930/931 has an internal wake-up timer that delays the clock until it
stabilizes depending to the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK
cycles plus 60 to 100

s. If the clock source is either the internal RC oscillator,

Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus
60 to 100

8.7 CPU CLOCK (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down up to 256 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.

8.8 Low power select

The P89LPC930/931 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the
power consumption further. On any reset, CLKLP is `0' allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC930/931 memory spaces are as follows:

DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.

IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.

SFR

Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.

CODE

64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC930/931 has 4 kB/ 8 kB of on-chip Code memory.

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8.10 Interrupts

The P89LPC930/931 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The
P89LPC930/931 supports 13 interrupt sources: external interrupts 0 and 1, timers 0
and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,
watchdog/real-time clock, I

C, keyboard, and comparators 1 and 2, and SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.

8.10.1

External interrupt inputs

The P89LPC930/931 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.

If an external interrupt is enabled when the P89LPC930/931 is put into Power-down
or Idle mode, the interrupt will cause the processor to wake-up and resume operation.
Refer to

Section 8.13 "Power reduction modes"

for details.

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8.11.1

Port configurations

All but three I/O port pins on the P89LPC930/931 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for
each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.

8.11.2

Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH,
it is weakly driven, allowing an external device to pull the pin LOW. When the pin is
driven LOW, it is driven strongly and able to sink a fairly large current. These features
are somewhat similar to an open-drain output except that there are three pull-up
transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC930/931 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to V

, causing extra power consumption. Therefore, applying

5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

8.11.3

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic `0'. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to V

An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.

8.11.4

Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.

8.11.5

Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic `1'. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.6

Port 0 analog functions

The P89LPC930/931 incorporates two Analog Comparators. In order to give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.

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8.11.7

Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different
from the LPC76x series of devices.

After power-up, all I/O pins except P1.5, may be configured by software.

Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only
or open-drain.

Every output on the P89LPC930/931 has been designed to sink typical LED drive
current. However, there is a maximum total output current for all ports which must not
be exceeded. Please refer to

Table 7 "DC electrical characteristics"

for detailed

specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit
noise generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.

8.12 Power monitoring functions

The P89LPC930/931 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on Detect and
Brownout detect.

8.12.1

Brownout detection

The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor
reset, however it may alternatively be configured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the brownout condition occurs when V

falls below

the brownout trip voltage, V

(see

Table 7 "DC electrical characteristics"

), and is

negated when V

rises above V

. If the P89LPC930/931 device is to operate with

a power supply that can be below 2.7 V, BOE should be left in the unprogrammed
state so that the device can operate at 2.4 V, otherwise continuous brownout reset
may prevent the device from operating.

For correct activation of Brownout detect, the V

rise and fall times must be

observed. Please see

Table 7 "DC electrical characteristics"

for specifications.

8.12.2

Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to
work as power comes up initially, before the power supply voltage reaches a level
where Brownout detect can work. The POF flag in the RSTSRC register is set to
indicate an initial power-up condition. The POF flag will remain set until cleared by
software.

8.13 Power reduction modes

The P89LPC930/931 supports three different power reduction modes. These modes
are Idle mode, Power-down mode, and total Power-down mode.

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8.13.1

Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate
Idle mode.

8.13.2

Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.
The P89LPC930/931 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the RAM keep-alive
voltage V

RAM

. This retains the RAM contents at the point where Power-down mode

was entered. SFR contents are not guaranteed after V

has been lowered to V

RAM

therefore it is highly recommended to wake up the processor via reset in this case.
V

must be raised to within the operating range before the Power-down mode is

exited.

Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during Power-down. These include: Brownout detect,
Watchdog Timer, Comparators (note that Comparators can be powered-down
separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is
disabled unless both the RC oscillator has been selected as the system clock and the
RTC is enabled.

8.13.3

Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry
and the voltage comparators are also disabled to conserve additional power. The
internal RC oscillator is disabled unless both the RC oscillator has been selected as
the system clock and the RTC is enabled. If the internal RC oscillator is used to clock
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.

8.14 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.

Remark: During a power cycle, V

must fall below V

POR

(see

Table 7 "DC electrical

characteristics" on page 42

) before power is reapplied, in order to ensure a power-on

reset.

Reset can be triggered from the following sources:

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External reset pin (during power-up or if user configured via UCFG1. This option
must be used for an oscillator frequency above 12 MHz.)

Power-on detect

Brownout detect

Watchdog Timer

Software reset

UART break character detect reset

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a `0' to the corresponding bit. More than one flag bit
may be set:

During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.

For any other reset, previously set flag bits that have not been cleared will remain
set.

8.14.1

Reset vector

Following reset, the P89LPC930/931 will fetch instructions from either address 0000h
or the Boot address. The Boot address is formed by using the Boot Vector as the high
byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on
(see

P89LPC930/931 User's Manual). Otherwise, instructions will be fetched from

address 0000H.

8.15 Timers/counters 0 and 1

The P89LPC930/931 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to
operate either as timers or event counter. An option to automatically toggle the T0
and/or T1 pins upon timer overflow has been added.

In the `Timer' function, the register is incremented every machine cycle.

In the `Counter' function, the register is incremented in response to a 1-to-0 transition
at its corresponding external input pin, T0 or T1. In this function, the external input is
sampled once during every machine cycle.

Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,
2 and 6 are the same for both Timers/Counters. Mode 3 is different.

8.15.1

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.15.2

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

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8.15.3

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.

8.15.4

Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.15.5

Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.

8.15.6

Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic `1'
prior to the first timer overflow when this mode is turned on.

8.16 Real-Time clock/system timer

The P89LPC930/931 has a simple Real-Time clock that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all `0's, the counter will be reloaded again and the RTCF
flag will be set. The clock source for this counter can be either the CPU clock (CCLK)
or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU
clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.

8.17 UART

The P89LPC930/931 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud
rate source. The P89LPC930/931 does include an independent Baud Rate
Generator. The baud rate can be selected from the oscillator (divided by a constant),
Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud
rate generation, enhancements over the standard 80C51 UART include Framing
Error detection, automatic address recognition, selectable double buffering and
several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit
UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

8.17.1

Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at

of the CPU clock

frequency.

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8.17.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic `0'),
8 data bits (LSB first), and a stop bit (logic `1'). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section 8.17.5 "Baud rate generator and selection"

8.17.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic `0'),
8 data bits (LSB first), a programmable 9

data bit, and a stop bit (logic `1'). When

data is transmitted, the 9

data bit (TB8 in SCON) can be assigned the value of `0' or

`1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9

data bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

8.17.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic `0'),
8 data bits (LSB first), a programmable 9

data bit, and a stop bit (logic `1'). In fact,

Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate
Generator (described in section

Section 8.17.5 "Baud rate generator and selection"

8.17.5

Baud rate generator and selection

The P89LPC930/931 enhanced UART has an independent Baud Rate Generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and
BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a
similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for
other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see

Figure 6

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.

8.17.6

Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is `1', framing errors can be made available in SCON.7 respectively. If
SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is `0'.

Fig 6.

Baud rate sources for UART (Modes 1, 3).

Baud Rate Modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

002aaa419

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8.17.7

Break detect

Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device and force the device into ISP mode.

8.17.8

Double buffering

The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = `0'), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = `0').

8.17.9

Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.

8.17.10

The 9

bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.

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8.20 Analog comparators

Two analog comparators are provided on the P89LPC930/931. Input and output
options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logic 1 (which may be read in a
register and/or routed to a pin) when the positive input (one of two selectable pins) is
greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a `0'. Each comparator may be configured to cause
an interrupt when the output value changes.

The overall connections to both comparators are shown in

Figure 13

. The

comparators function to V

= 2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator
interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate
interrupt service.

When a comparator is disabled the comparator's output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator flag, CMFx, after disabling the
comparator.

8.20.1

Internal reference voltage

An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as V

REF

, is 1.23 V

10%.

Fig 13. Comparator input and output connections.

Comparator 1

CP1

CN1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

VREF

OE1

Change Detect

CO1

CMF1

Interrupt

002aaa422

CMP1 (P0.6)

Change Detect

CMF2

Comparator 2

OE2

CO2

CMP2 (P0.0)

CP2

CN2

(P0.2) CIN2A

(P0.1) CIN2B

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8.20.2

Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag
is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. If both comparators enable interrupts, after entering the
interrupt service routine, the user needs to read the flags to determine which
comparator caused the interrupt.

8.20.3

Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down
mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of
the comparator output state will generate an interrupt and wake up the processor. If
the comparator output to a pin is enabled, the pin should be configured in the
push-pull mode in order to obtain fast switching times while in power-down mode. The
reason is that with the oscillator stopped, the temporary strong pull-up that normally
occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the
normal operating mode. This fact should be taken into account when system power
consumption is an issue. To minimize power consumption, the user can disable the
comparators via PCONA.5, or put the device in Total Power-down mode.

8.21 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can
be used for bus address recognition or keypad recognition. The user can configure
the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)
is used to define a pattern that is compared to the value of Port 0. The Keypad
Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when
the condition is matched while the Keypad Interrupt function is active. An interrupt will
be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register
(KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x
series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then
any key connected to Port 0 which is enabled by the KBMASK register will cause the
hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt
may be used to wake up the CPU from Idle or Power-down modes. This feature is
particularly useful in handheld, battery-powered systems that need to carefully
manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held
longer than 6 CCLKs.

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8.22 Watchdog timer

The watchdog timer causes a system reset when it underflows as a result of a failure
to feed the timer prior to the timer reaching its terminal count. It consists of a
programmable 12-bit prescaler, and an 8-bit down counter. The down counter is
decremented by a tap taken from the prescaler. The clock source for the prescaler is
either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can
only be reset by a power-on reset. When the Watchdog feature is disabled, it can be
used as an interval timer and may generate an interrupt.

Figure 14

shows the

watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte
sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,
the watchdog is disabled. The watchdog timer has a time-out period that ranges from
a few

s to a few seconds. Please refer to the

P89LPC930/931 User's Manual for

more details.

8.23 Additional features

8.23.1

Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.

8.23.2

Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic `0' so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 14. Watchdog timer in Watchdog mode (WDTE = `1').

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

CONTROL REGISTER

PRESCALER

002aaa423

SHADOW
REGISTER
FOR WDCON

8-BIT DOWN

COUNTER

WDL (C1H)

Watchdog

oscillator

PCLK

MOV WFEED1, #0A5H
MOV WFEED2, #05AH

RESET
see note (1)

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8.24 Flash program memory

8.24.1

General description

The P89LPC930/931 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be read, erased, or written as bytes. The Sector and
Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip
Erase operation will erase the entire program memory. In-System Programming and
standard parallel programming are both available. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The P89LPC930/931
Flash reliably stores memory contents even after more than 100,000 erase and
program cycles. The cell is designed to optimize the erase and programming
mechanisms. The P89LPC930/931 uses V

as the supply voltage to perform the

Program/Erase algorithms.

8.24.2

Features

Byte-erase allowing code memory to be used for data storage.

Internal fixed boot ROM, containing low-level In-Application Programming (IAP)
routines.

User programs can call these routines to perform In-Application Programming
(IAP).

Default loader providing In-System Programming via the serial port, located in
upper end of user program memory.

Boot vector allows user-provided Flash loader code to reside anywhere in the
Flash memory space, providing flexibility to the user.

Programming and erase over the full operating voltage range.

Programming/Erase using ISP/IAP.

Any flash program/erase operation in 2 ms.

Parallel programming with industry-standard commercial programmers.

Programmable security for the code in the Flash for each sector.

More than 100,000 typical erase/program cycles for each byte.

10 year minimum data retention.

8.24.3

Using Flash as data storage

The Flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a
MOVC instruction is not allowed to read code memory contents of a secured sector).
Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.24.4

ISP and IAP capabilities of the P89LPC930/931

Flash organization:

The P89LPC930/931 program memory consists of eight 1 KB

sectors. Each sector can be further divided into 64-byte pages. In addition to sector
erase and page erase, a 64-byte page register is included which allows from 1 to 64
bytes of a given page to be programmed at the same time, substantially reducing
overall programming time. An In-Application Programming (IAP) interface is provided
to allow the end user's application to erase and reprogram the user code memory. In

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addition, erasing and reprogramming of user-programmable bytes including UCFG1,
the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory,
the upper 512 bytes of user code space contains a serial In-System Programming
(ISP) routine allowing for the device to be programmed in circuit through the serial
port.

Flash programming and erasing:

There are three methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling low-level routines
through a common entry point. Second, the on-chip ISP boot loader may be invoked.
This ISP boot loader will, in turn, call low-level routines through the same common
entry point that can be used by the end-user application. Third, the Flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device. This device does not provide for
direct verification of code memory contents. Instead this device provides a 32-bit
CRC result on either a sector or the entire 8 kbytes of user code space.

Boot ROM:

When the microcontroller programs its own Flash memory, all of the low

level details are handled by code that is contained in a Boot ROM that is separate
from the Flash memory. A user program simply calls the common entry point in the
Boot ROM with appropriate parameters to accomplish the desired operation. The
Boot ROM include operations such as erase sector, erase page, program page, CRC,
program security bit, etc. The Boot ROM occupies the program memory space at the
top of the address space from FF00 to FEFF hex, thereby not conflicting with the user
program memory space.

Power-on reset code execution:

The P89LPC930/931 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the
P89LPC930/931 examines the contents of the Boot Status Bit. If the Boot Status Bit
is set to zero, power-up execution starts at location 0000H, which is the normal start
address of the user's application code. When the Boot Status Bit is set to a value
other than zero, the contents of the Boot Vector is used as the high byte of the
execution address and the low byte is set to 00H. The factory default setting is 01EH
(0EH for the LPC930), corresponds to the address 1E00H (0E00h for the LPC930) for
the default ISP boot loader. This boot loader is pre-programmed at the factory into
this address space and can be erased by the user. Users who wish to use this
loader should take cautions to avoid erasing the 1 kbyte sector from 1C00H to
1FFFH (0C00H to 0FFFH for the LPC930). Instead, the page erase function can
be used to erase the eight (four for the LPC930) 64-byte pages located from
1C00H to 1DFFH (0C00H to 0DFFH for the LPC930). A custom boot loader can be
written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader:

The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the
P89LPC930/931 User's Manual for specific information). This has the same effect as
having a non-zero status byte. This allows an application to be built that will normally
execute user code but can be manually forced into ISP operation. If the factory default
setting for the Boot Vector (1EH for the lPC931, 0EH for the LPC930) is changed, it
will no longer point to the factory pre-programmed ISP boot loader code. If this
happens, the only way it is possible to change the contents of the Boot Vector is
through the parallel programming method, provided that the end user application
does not contain a customized loader that provides for erasing and reprogramming of

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the Boot Vector and Boot Status Bit. After programming the Flash, the status byte
should be programmed to zero in order to allow execution of the user's application
code beginning at address 0000H.

In-System Programming (ISP):

In-System Programming is performed without

removing the microcontroller from the system. The In-System Programming facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC930/931 through the serial port. This
firmware is provided by Philips and embedded within each P89LPC930/931 device.
The Philips In-System Programming facility has made in-system programming in an
embedded application possible with a minimum of additional expense in components
and circuit board area. The ISP function uses five pins (V

, V

, TxD, RxD, and

RST). Only a small connector needs to be available to interface your application to an
external circuit in order to use this feature.

In-Application Programming (IAP):

Several In-Application Programming (IAP) calls

are available for use by an application program to permit selective erasing, reading,
and programming of Flash sectors, pages, security bits, configuration bytes, and
device id. All calls are made through a common interface, PGM_MTP. The
programming functions are selected by setting up the microcontroller's registers
before making a call to PGM_MTP at FF00H.

8.25 User configuration bytes

A number of user-configurable features of the P89LPC930/931 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the Flash byte UCFG1. Please see the
P89LPC930/931 User's Manual for additional details.

8.26 User sector security bytes

There are eight User Sector Security Bytes, each corresponding to one sector.
Please see the

P89LPC930/931 User's Manual for additional details.

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Limiting values

[1]

The following applies to Limiting values:

a) Stresses above those listed under

Table 6

may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in

Table 7 "DC electrical characteristics"

Table 8 "AC

characteristics"

and

Table 9 "AC characteristics"

of this specification are not implied.

b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless

otherwise noted.

Table 6:

Limiting values

[1]

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

amb(bias)

operating bias ambient temperature

+125

stg

storage temperature range

+150

xtal

voltage on XTAL1, XTAL2 pin to V

+ 0.5

voltage on any other pin to V

0.5

+5.5

OH(I/O)

HIGH-level output current per I/O pin

OL(I/O)

LOW-level output current per I/O pin

I/O(tot)(max)

maximum total I/O current

100

tot(pack)

total power dissipation per package

based on package heat
transfer, not device power
consumption

1.5

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10. Static characteristics

Table 7:

DC electrical characteristics

= 2.4 V to 3.6 V unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

[1]

Max

Unit

DD(oper)

power supply current, operating 3.6 V; 12 MHz

[2]

3.6 V; 18 MHz

[2]

DD(idle)

power supply current, Idle
mode

3.6 V; 12 MHz

[2]

3.25

3.6 V; 18 MHz

[2]

DD(PD)

power supply current,
Power-down mode, voltage
comparators powered-down

3.6 V

[2]

DD(TPD)

power supply current, Total
Power-down mode

3.6 V

[2]

(dV

/dt)

rise rate

mV/

(dV

/dt)

fall rate

mV/

POR

Power-on reset detect voltage

0.2

RAM

RAM keep-alive voltage

1.5

th(HL)

negative-going threshold
voltage

except SCL, SDA

0.22V

0.4V

LOW-level input voltage

SCL, SDA only

0.5

0.3V

th(LH)

positive-going threshold voltage except SCL, SDA

0.6V

0.7V

HIGH-level input voltage

SCL, SDA only

0.7V

5.5

hys

hysteresis voltage

Port 1

0.2V

LOW-level output voltage; all
ports, all modes except Hi-Z

= 20 mA;

= 2.4 V to 3.6 V

[3]

0.6

1.0

= 3.2 mA;

= 2.4 V to 3.6 V

[3]

0.2

0.3

HIGH-level output voltage, all
ports

= 2.4 V to 3.6 V;

quasi-bidirectional mode

0.3

0.2

3.2 mA;

= 2.4 V to 3.6 V;

push-pull mode

0.7

0.4

20 mA;

= 2.4 V to 3.6 V;

push-pull mode

0.8V

input/output pin capacitance

[4]

logic 0 input current, all ports

= 0.4 V

[5]

input leakage current, all ports

= V

or V

[6]

logic 1-to-0 transition current,
all ports

= 2.0 V at

= 3.6 V

[7]

450

RST

internal reset pull-up resistor

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11. Dynamic characteristics

Table 8:

AC characteristics

= 2.4 V to 3.6 V unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 12 MHz

Unit

Min

Max

Min

Max

RCOSC

internal RC oscillator frequency

7.189

7.557

7.189

7.557

MHz

WDOSC

internal watchdog oscillator
frequency

320

520

320

520

kHz

osc

oscillator frequency

MHz

CLCL

clock cycle

see

Figure 20

CLKP

CLKLP active frequency

MHz

Glitch filter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except
P1.5/RST

signal acceptance, any pin except
P1.5/RST

External clock

CHCX

HIGH time

see

Figure 20

CLCL

CLCX

LOW time

see

Figure 20

CLCL

CHCX

CLCH

rise time

see

Figure 20

CHCL

fall time

see

Figure 20

Shift register (UART mode 0)

XLXL

serial port clock cycle time

16 t

CLCL

1333

QVXH

output data set-up to clock rising
edge

13 t

CLCL

1083

XHQX

output data hold after clock rising
edge

CLCL

+ 20

103

XHDX

input data hold after clock rising
edge

DVXH

input data valid to clock rising edge

150

SPI interface

SPI

Operating frequency

2.0 MHz (Slave)

CCLK

2.0

MHz

3.0 MHz (Master)

CCLK

MHz

SPICYC

Cycle time

see Figures

2.0 MHz (Slave)

CCLK

500

3.0 MHz (Master)

CCLK

SPILEAD

Enable lead time (Slave)

see Figures

2.0 MHz

250

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[1]

Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.

SPILAG

Enable lag time (Slave)

see Figures

2.0 MHz

250

SPICLKH

SPICLK high time

see Figures

Master

CCLK

340

Slave

CCLK

190

SPICLKL

SPICLK low time

see Figures

Master

CCLK

340

Slave

CCLK

190

SPIDSU

Data set-up time (Master or Slave) see Figures

100

SPIDH

Data hold time (Master or Slave)

see Figures

100

SPIA

Access time (Slave)

see Figures

120

SPIDIS

Disable time (Slave)

see Figures

2.0 MHz

240

SPIDV

Enable to output data valid

see Figures

2.0 MHz

240

3.0 MHz

167

SPIOH

Output data hold time

see Figures

SPIR

Rise time

see Figures

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

SPIF

Fall time

see Figures

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

Table 8:

AC characteristics

...continued

= 2.4 V to 3.6 V unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 12 MHz

Unit

Min

Max

Min

Max

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Table 9:

AC characteristics

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

RCOSC

internal RC oscillator frequency

7.189

7.557

7.189

7.557

MHz

WDOSC

internal Watchdog oscillator
frequency

320

520

320

520

kHz

osc

oscillator frequency

[2]

MHz

CLCL

clock cycle

see

Figure 20

CLKP

CLKLP active frequency

MHz

Glitch filter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except
P1.5/RST

signal acceptance, any pin except
P1.5/RST

External clock

CHCX

HIGH time

see

Figure 20

CLCL

CLCX

LOW time

see

Figure 20

CLCL

CHCX

CLCH

rise time

see

Figure 20

CHCL

fall time

see

Figure 20

Shift register (UART mode 0)

XLXL

serial port clock cycle time

16 t

CLCL

888

QVXH

output data set-up to clock rising
edge

13 t

CLCL

722

XHQX

output data hold after clock rising
edge

CLCL

+ 20

XHDX

input data hold after clock rising
edge

DVXH

input data valid to clock rising edge

150

SPI interface

SPI

Operating frequency

3.0 MHz (Slave)

CCLK

MHz

4.5 MHz (Master)

CCLK

4.5

MHz

SPICYC

Cycle time

see Figures

3.0 MHz (Slave)

CCLK

333

4.5 MHz (Master)

CCLK

222

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SPILEAD

Enable lead time (Slave)

see Figures

3.0 MHz

250

SPILAG

Enable lag time (Slave)

see Figures

3.0 MHz

250

SPICLKH

SPICLK high time

see Figures

Master

CCLK

111

Slave

CCLK

167

SPICLKL

SPICLK low time

see Figures

Master

CCLK

111

Slave

CCLK

167

SPIDSU

Data set-up time (Master or Slave) see Figures

100

SPIDH

Data hold time (Master or Slave)

see Figures

100

SPIA

Access time (Slave)

see Figures

SPIDIS

Disable time (Slave)

see Figures

3.0 MHz

160

SPIDV

Enable to output data valid

see Figures

3.0 MHz

160

4.5 MHz

111

SPIOH

Output data hold time

see Figures

SPIR

Rise time

see Figures

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

Table 9:

AC characteristics

...continued

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

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[1]

Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.

[2]

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V

has reached its specified level. When system power is removed V

will fall below the

minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage.

SPIF

Fall time

see Figures

SPI outputs (SPICLK, MOSI,
MISO)

100

SPI inputs (SPICLK, MOSI,
MISO, SS)

2000

Table 9:

AC characteristics

...continued

= 3.0 V to 3.6 V, unless otherwise specified.

amb

C to +85

C for industrial, unless otherwise specified.

[1]

Symbol

Parameter

Conditions

Variable clock

osc

= 18 MHz

Unit

Min

Max

Min

Max

Fig 15. SPI master timing (CPHA = 0).

tCLCL

tSPICLKH

tSPICLKL

Master LSB/MSB out

Master MSB/LSB out

tSPIDH

tSPIDSU

tSPICLKL

tSPICLKH

tSPIF

tSPIOH

tSPIDV

tSPIR

tSPIDV

tSPIF

tSPIR

SPICLK

(CPOL = 0)

(output)

002aaa156

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB in

MSB/LSB in

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Contact information

For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Licenses

Level

Data sheet status

[1]

Product status

[2][3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Purchase of Philips I

C components

Purchase of Philips I

C components conveys a license

under the Philips' I

C patent to use the components in the

C system provided the system conforms to the I

specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.

The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.

Date of release: 15 December 2004

Document order number: 9397 750 14472

Contents

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special function registers. . . . . . . . . . . . . . . . . . . . . 11

Functional description . . . . . . . . . . . . . . . . . . . . . . . 16

8.1

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1

Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2

CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.3

Low speed oscillator option . . . . . . . . . . . . . . . . . . . 16

8.2.4

Medium speed oscillator option . . . . . . . . . . . . . . . . 16

8.2.5

High speed oscillator option . . . . . . . . . . . . . . . . . . . 16

8.2.6

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.3

On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 17

8.4

Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 17

8.5

External clock input option . . . . . . . . . . . . . . . . . . . . 17

8.6

CPU CLock (CCLK) wake-up delay . . . . . . . . . . . . . 19

8.7

CPU CLOCK (CCLK) modification: DIVM register . . 19

8.8

Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.9

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 19

8.10

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.10.1

External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 20

8.11

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.11.1

Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.11.2

Quasi-bidirectional output configuration. . . . . . . . . . 22

8.11.3

Open-drain output configuration. . . . . . . . . . . . . . . . 22

8.11.4

Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 22

8.11.5

Push-pull output configuration . . . . . . . . . . . . . . . . . 22

8.11.6

Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 22

8.11.7

Additional port features . . . . . . . . . . . . . . . . . . . . . . 24

8.12

Power monitoring functions . . . . . . . . . . . . . . . . . . . 24

8.12.1

Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.12.2

Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.13

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 24

8.13.1

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.13.2

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.13.3

Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 25

8.14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.14.1

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 26

8.15.1

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15.2

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15.3

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.4

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.5

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.6

Timer overflow toggle output . . . . . . . . . . . . . . . . . . 27

8.16

Real-Time clock/system timer . . . . . . . . . . . . . . . . . 27

8.17

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.17.1

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.17.2

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.3

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.4

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.5

Baud rate generator and selection . . . . . . . . . . . . . . 28

8.17.6

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.7

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.17.8

Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.17.9

Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 29

8.17.10

The 9

bit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.18

C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 30

8.19

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . 31

8.19.1

Typical SPI configurations. . . . . . . . . . . . . . . . . . . . . 33

8.20

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.20.1

Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 35

8.20.2

Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 36

8.20.3

Comparators and power reduction modes . . . . . . . . 36

8.21

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 36

8.22

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23.1

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23.2

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.24

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 38

8.24.1

General description. . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.24.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.24.3

Using Flash as data storage . . . . . . . . . . . . . . . . . . . 38

8.24.4

ISP and IAP capabilities of the P89LPC930/931 . . . 38

8.25

User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 40

8.26

User sector security bytes . . . . . . . . . . . . . . . . . . . . 40

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 42

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 44

Comparator electrical characteristics . . . . . . . . . . . 51

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC930FDH

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: P89LPC930FDH