1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

CONTENTS

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING INFORMATION

5.1

Pinning

5.2

Pin description

FREQUENCY GENERATOR

6.1

Frequency generator derivative registers

6.2

Melody output (P1.7/MDY)

6.3

Frequency registers

6.4

DTMF frequencies

6.5

Modem frequencies

6.6

Musical scale frequencies

EEPROM AND TIMER 2 ORGANIZATION

7.1

EEPROM registers

7.2

EEPROM latches

7.3

EEPROM flags

7.4

EEPROM macros

7.5

EEPROM access

7.6

Timer 2

DERIVATIVE INTERRUPTS

TIMING

RESET

IDLE MODE

STOP MODE

INSTRUCTION SET RESTRICTIONS

OVERVIEW OF PORT AND
POWER-ON-RESET CONFIGURATION

OTP PROGRAMMING

SUMMARY OF DERIVATIVE REGISTERS

HANDLING

LIMITING VALUES

DC CHARACTERISTICS

AC CHARACTERISTICS

PACKAGE OUTLINES

SOLDERING

22.1

Reflow soldering

22.2

Wave soldering

22.3

DIP

22.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

FEATURES

8-bit CPU, ROM, RAM, EEPROM and I/O; in a single
28-lead or 32-lead package

8 kbytes user-programmable ROM (One-Time
Programmable)

128 bytes RAM

128 bytes Electrically Erasable Programmable
Read-Only Memory (EEPROM)

Over 100 instructions (based on MAB8048) all of 1 or 2
cycles

20 quasi-bidirectional I/O port lines

8-bit programmable Timer/event counter 1

8-bit reloadable Timer 2

Three single-level vectored interrupts:

external

8-bit programmable Timer/event counter 1

derivative; triggered by reloadable Timer 2

Two test inputs, one of which also serves as the external
interrupt input

DTMF, modem, musical tone generator

Reference for supply and temperature-independent
tone output

Filtering for low output distortion (CEPT compatible)

Melody output for ringer application

Power-on-reset

Stop and Idle modes

Supply voltage: 1.8 to 6 V (DTMF tone output and
EEPROM erase/write from 2.5 V)

Clock frequency: 1 to 16 MHz (3.58 MHz for DTMF
suggested)

Operating temperature:

25 to +70

Manufactured in silicon gate CMOS process.

GENERAL DESCRIPTION

This data sheet details the specific properties of the
PCD3755A, PCD3755E and PCD3755F. The devices
differ in their Port and Power-on-reset configurations.
References to `PCD3755x' apply to all three types.
The devices are members of the PCD33xxA family of
microcontrollers.
The shared properties of the family are described in the
"PCD33xxA family" data sheet, which should be read in
conjunction with this publication.

The PCD3755A, PCD3755E and PCD3755F are
One-Time Programmable (OTP) microcontrollers
designed primarily for telephony applications.They include
an on-chip generator for dual tone multifrequency (DTMF),
modem and musical tones. In addition to dialling,
generated frequencies can be made available as square
waves (P1.7/MDY) for melody generation, providing ringer
operation.

The PCD3755A, PCD3755E and PCD3755F also
incorporate 128 bytes of EEPROM. The EEPROM can be
used for storing telephone numbers, particularly for
implementing redial functions.

The Power-on-reset circuitry is extra accurate to
accommodate parallel telephones and fax equipment.

The instruction set is similar to that of the MAB8048 and is
a sub-set of that listed in the

"PCD33xxA family" data

sheet.

ORDERING INFORMATION (see note 1)

Note

1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type

number will also specify the required program and the ROM mask options.

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

PCD3755xP

DIP28

plastic dual in-line package; 28 leads (600 mil)

SOT117-1

PCD3755xT

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

PCD3755xH

LQFP32

plastic low profile quad flat package; 32 leads; body 7

1.4 mm

SOT358-1

1997

Apr

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator

8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

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BLOCK DIAGRAM

handbook, full pagewidth

MBG639

PORT 0

FLIP-FLOP

PORT 0

BUFFER

HIGHER

PROGRAM

COUNTER

LOWER

PROGRAM

COUNTER

PROGRAM

STATUS

WORD

MEMORY

BANK

FLIP-FLOPS

RESIDENT

OTP-ROM

8 kbytes

DECODE

P0.0 to P0.7

TIMER/
EVENT

COUNTER

INTERNAL

CLOCK

FREQ.

PORT 1

BUFFER

PORT 1

FLIP-FLOP

P1.0 to P1.6

PORT 2

BUFFER

PORT 2

FLIP-FLOP

P2.0 to P2.3

P1.7/MDY

MELODY

CONTROL

TONE

FILTER

OSCILLATOR

RAM

ADDRESS

ACCUMULATOR

TEMPORARY

ARITHMETIC

INSTRUCTION

AND

DECODER

DECIMAL

ADJUST

CONTROL AND TIMING

XTAL2

XTAL1

RESET

CE/T0

STOP

IDLE

INTERRUPT

INITIALIZE

CONDITIONAL

BRANCH

LOGIC

CE/T0

TIMER

FLAG

CARRY

ACC

ACC BIT

TEST

MULTIPLEXER

8 LEVEL STACK

(VARIABLE LENGTH)

OPTIONAL SECOND

DATA STORE

D
E
C
O
D
E

timer interrupt

external interrupt

RESIDENT RAM ARRAY

128 bytes

derivative

interrupt

LOGIC UNIT

T 1

LGF

HGF

SINE WAVE

GENERATOR

INTERRUPT

LOGIC

EEPROM

DATA

TRANSFER

EEPROM

ADDRESS

EEPROM

CONTROL

TIMER 2

RELOAD

EEPROM
128 bytes

PCD3755x

POWER-ON-RESET

VPOR

RESET

Fig.1 Block diagram.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

5.2

Pin description

Table 1

SOT117-1 and SOT136-1 packages (for information on parallel I/O ports, see Chapter 14)

Table 2

SOT358-1 package (for information on parallel I/O ports, see Chapter 14)

SYMBOL

PIN

TYPE

DESCRIPTION

P1.1 to P0.7

1 to 7

I/O

7 bits of Port 0: 8-bit quasi-bidirectional I/O port

Test 1 or count input of 8-bit Timer/event counter 1

XTAL1

crystal oscillator or external clock input

XTAL2

crystal oscillator output

RESET

reset input

CE/T0

Chip Enable or Test 0

P1.0 to P1.6

13 to 19

I/O

7 bits of Port 1: 8-bit quasi-bidirectional I/O port

P1.7/MDY

I/O

1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output

P2.0

I/O

1 bit of Port 2: 4-bit quasi-bidirectional I/O port

ground

TONE

DTMF output

positive supply voltage

P2.1 to P2.3

25 to 27

I/O

3 bits of Port 2: 4-bit quasi-bidirectional I/O port

P0.0

I/O

1 bit of Port 0: 8-bit quasi-bidirectional I/O port

SYMBOL

PIN

TYPE

DESCRIPTION

n.c.

1, 13, 17, 28

not connected

P0.5 to P0.7

2 to 4

I/O

3 bits of Port 0: 8-bit quasi-bidirectional I/O port

Test 1 or count input of 8-bit Timer/event counter 1

XTAL1

crystal oscillator or external clock input

XTAL2

crystal oscillator output

RESET

reset input

CE/T0

Chip Enable or Test 0

P1.0 to P1.6

10 to 12,

14 to 16, 18

I/O

7 bits of Port 1: 8-bit quasi-bidirectional I/O port

P1.7/MDY

I/O

1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output

P2.0

I/O

1 bit of Port 2: 4-bit quasi-bidirectional I/O port

ground

TONE

DTMF output

positive supply voltage

P2.1 to P2.3

24 to 26

I/O

3 bits of Port 2: 4-bit quasi-bidirectional I/O port

P0.0 to P0.4

27, 29 to 32

I/O

5 bits of Port 0: 8-bit quasi-bidirectional I/O port

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

FREQUENCY GENERATOR

A versatile frequency generator section is provided (see
Fig.4). For normal operation, use a 3.58 MHz quartz
crystal or PXE resonator. The frequency generator
includes precision circuitry for dual tone multifrequency
(DTMF) signals, which is typically used for tone dialling
telephone sets.

Their frequencies are provided in purely sinusoidal form on
the TONE output or as square waves on the P1.7/MDY
output.

The TONE output can alternatively issue twelve modem
frequencies for data rates between 300 and 1200 bits/s.

In addition to DTMF and modem frequencies, two octaves
of musical scale in steps of semitones are available.

In case no tones are generated the TONE output is in
3-state mode.

6.1

Frequency generator derivative registers

6.1.1

IGH AND

ROUP

REQUENCY REGISTERS

Table 3 gives the addresses, mnemonics and access types of the High Group Frequency (HGF) and Low Group
Frequency (LGF) registers.

Table 3

Hexadecimal addresses, mnemonics, access types and bit mnemonics of the frequency registers

6.1.2

ELODY

ONTROL

EGISTER

(MDYCON)

MDYCON is a R/W register.

Table 4

Melody Control Register (address 13H)

Table 5

Description of MDYCON bits

REGISTER

ADDRESS

REGISTER

MNEMONIC

ACCESS

TYPE

BIT MNEMONICS

11H

HGF

12H

LGF

EMO

BIT

MNEMONIC

DESCRIPTION

7 to 1

These bits are set to a logic 0.

EMO

Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line.
If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port
instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read
in and the port flip-flop may be written by port instructions. However, the port flip-flop of
P1.7/MDY must remain set to avoid conflicts between melody and port outputs.
When the HGF contents are zero while EMO = 1, P1.7/MDY is in the logic HIGH state.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

6.2

Melody output (P1.7/MDY)

The melody output (P1.7/MDY) is very useful for
generating musical tones when a purely sinusoidal signal
is not required, such as for ringer applications.

The square wave (duty cycle =

or 52%) will include

the attenuated harmonics of the base frequency, which is
defined by the contents of the HGF register (Table 3).
However, even higher frequency tones may be produced
since the low-pass filtering on the TONE output is not
applied to the P1.7/MDY output. This results in the
minimum decimal value x in the HGF register being 2 for
the P1.7/MDY output, rather than 60 for the TONE output
- the value shown in equation (1). A sinusoidal TONE
output is produced at the same time as the melody square
wave, but due to the filtering, the higher frequency sine
waves with x < 60 will not appear at the TONE output.

Since the melody output is shared with P1.7, the port
flip-flop of P1.7 has to be set HIGH before using the
melody output. This is to avoid conflicts between melody
and port outputs. The melody output drive depends on the
configuration of port P1.7/MDY; see Chapter 14, Table 24.

6.3

Frequency registers

The two frequency registers HGF and LGF define two
frequencies. From these, the digital sine synthesizers
together with the Digital-to-Analog Converters (DACs)
construct two sine waves. Their amplitudes are precisely
scaled according to the bandgap voltage reference. This
ensures tone output levels independent of supply voltage
and temperature.

The amplitude of the Low group frequency sine wave is
attenuated by 2 dB compared to the amplitude of the High
group frequency sine wave. The two sine waves are
summed and then filtered by an on-chip switched
capacitor and RC low-pass filters. These guarantee that all
DTMF tones generated fulfil the CEPT recommendations
with respect to amplitude, frequency deviation, total
harmonic distortion and suppression of unwanted
frequency components.

The value 00H in a frequency register stops the
corresponding digital sine synthesizer. If both frequency
registers contain 00H, the whole frequency generator is
shut off, resulting in lower power consumption.

The frequency of the sine wave generated `f' is dependent
on the clock frequency `f

xtal

' and the decimal value `x' held

in the frequency registers (HGF and LGF). The variables
are related by the equation:

(1)

The frequency limitation given by x

60 is due to the

low-pass filters which would attenuate higher frequency
sine waves.

xtal

23 x

(

)

[

]

---------------------------------

where

255

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

6.4

DTMF frequencies

Assuming an oscillator frequency f

xtal

= 3.58 MHz, the

DTMF standard frequencies can be implemented as
shown in Table 6.

The relationships between telephone keyboard symbols,
DTMF frequency pairs and the frequency register contents
are given in Table 7.

Table 6

DTMF standard frequencies and their
implementation; value = LGF, HGF contents

Table 7

Dialling symbols, corresponding DTMF
frequency pairs and frequency register contents

VALUE

(HEX)

FREQUENCY (Hz)

DEVIATION

STANDARD

GENERATED

(%)

(Hz)

697

697.90

0.13

0.90

770

770.46

0.06

0.46

852

850.45

0.18

1.55

941

943.23

0.24

2.23

1209

1206.45

0.21

2.55

1336

1341.66

0.42

5.66

1477

1482.21

0.35

5.21

1633

1638.24

0.32

5.24

TELEPHONE

KEYBOARD

SYMBOLS

DTMF FREQ.

PAIRS

(Hz)

LGF

VALUE

(HEX)

HGF

VALUE

(HEX)

(941, 1336)

(697, 1209)

(697, 1336)

(697, 1477)

(770, 1209)

(770, 1336)

(770, 1477)

(852, 1209)

(852, 1336)

(852, 1477)

(697, 1633)

(770, 1633)

(852, 1633)

(941, 1633)

(941, 1209)

(941, 1477)

6.5

Modem frequencies

Again assuming an oscillator frequency f

xtal

= 3.58 MHz,

the standard modem frequencies can be implemented as
in Table 8. It is suggested to define the frequency by the
HGF register while the LGF register contains 00H,
disabling Low Group Frequency generation.

Table 8

Standard modem frequencies and their
implementation

Notes

1. Standard is V.21.

2. Standard is Bell 103.

3. Standard is Bell 202.

4. Standard is V.23.

HGF

VALUE

(HEX)

FREQUENCY (Hz)

DEVIATION

MODEM

GENERATED

(%)

(Hz)

980

(1)

978.82

0.12

1.18

1180

(1)

1179.03

0.08

0.97

1070

(2)

1073.33

0.31

3.33

1270

(2)

1265.30

0.37

4.70

1200

(3)

1197.17

0.24

2.83

2200

(3)

2192.01

0.36

7.99

1300

(4)

1296.94

0.24

3.06

2100

(4)

2103.14

0.15

3.14

1650

(1)

1655.66

0.34

5.66

1850

(1)

1852.77

0.15

2.77

2025

(2)

2021.20

0.19

3.80

2225

(2)

2223.32

0.08

1.68

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

6.6

Musical scale frequencies

Finally, two octaves of musical scale in steps of semitones
can be realized, again assuming an oscillator frequency
f

xtal

= 3.58 MHz (Table 9). It is suggested to define the

frequency by the HGF register while the LGF contains
00H, disabling Low Group Frequency generation.

Table 9

Musical scale frequencies and their
implementation

Note

1. Standard scale based on A4 @ 440 Hz.

NOTE

HGF

VALUE

(HEX)

FREQUENCY (Hz)

STANDARD

(1)

GENERATED

D#5

622.3

622.5

659.3

659.5

698.5

697.9

F#5

740.0

741.1

784.0

782.1

G#5

830.6

832.3

880.0

879.3

A#5

923.3

931.9

987.8

985.0

1046.5

1044.5

C#6

1108.7

1111.7

1174.7

1179.0

D#6

1244.5

1245.1

1318.5

1318.9

1396.9

1402.1

F#6

1480.0

1482.2

1568.0

1572.0

G#6

1661.2

1655.7

1760.0

1768.5

A#6

1864.7

1875.1

1975.5

1970.0

2093.0

2103.3

C#7

2217.5

2223.3

2349.3

2358.1

D#7

2489.0

2470.4

EEPROM AND TIMER 2 ORGANIZATION

The PCD3755A, PCD3755E and PCD3755F have
128 bytes of Electrically Erasable Programmable
Read-Only Memory (EEPROM). Such non-volatile storage
provides data retention without the need for battery
backup. In telecom applications, the EEPROM is used for
storing redial numbers and for short dialling of frequently
used numbers. More generally, EEPROM may be used for
customizing microcontrollers, such as to include a PIN
code or a country code, to define trimming parameters, to
select application features from the range stored in ROM.

The most significant difference between a RAM and an
EEPROM is that a bit in EEPROM, once written to a
logic 1, cannot be cleared by a subsequent write
operation. Successive write accesses actually perform a
logical OR with the previously stored information.
Therefore, to clear a bit, the whole byte must be erased
and re-written with the particular bit cleared. Thus, an
erase-and-write operation is the EEPROM equivalent of a
RAM write operation.

Whereas read access times to an EEPROM are
comparable to RAM access times, write and erase
accesses are much slower at 5 ms each. To make these
operations more efficient, several provisions are available
in the PCD3755A, PCD3755E and PCD3755F.

First, the EEPROM array is structured into 32 four-byte
pages (see Fig.5) permitting access to 4 bytes in parallel
(write page, erase/write page and erase page). It is also
possible to erase and write individual bytes. Finally, the
EEPROM address register provides auto-incrementing,
allowing very efficient read and write accesses to
sequential bytes.

To simplify the erase and write timing, the derivative 8-bit
down-counter (Timer 2) with reload register is provided.
In addition to EEPROM timing, Timer 2 can be used for
general real-time tasks, such as for measuring signal
duration and for defining pulse widths.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

7.1

EEPROM registers

7.1.1

EEPROM C

ONTROL

EGISTER

(EPCR)

The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register.

Table 10 EEPROM Control Register (address 04H, access type R/W)

Table 11 Description of EPCR bits

Table 12 Mode selection; X = don't care

STT2

ET2I

T2F

EWP

MC3

MC2

MC1

BIT

MNEMONIC

DESCRIPTION

STT2

Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2
decrements from reload value.

ET2I

Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1,
then T2F event can request interrupt.

T2F

Timer 2 flag. Set when T2 underflows (or by program); reset by program.

EWP

Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or
write and Timer 2). Reset at the end of EEPROM erase and/or write.

MC3

Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as
shown in Table 12

MC2

MC1

This bit is set to a logic 0.

EWP

MC3

MC2

MC1

DESCRIPTION

read byte

increment mode

write page

erase/write page

erase page

not allowed

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

7.1.2

EEPROM

ADDRESS REGISTER

(ADDR)

The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed.

As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This
behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write
accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero.

Table 13 EEPROM Address Register (address 01H, access type R/W)

Table 14 Description of ADDR bits

7.1.3

EEPROM D

ATA

EGISTER

(DATR)

Table 15 EEPROM Data Register (address 03H; access type R/W)

Table 16 Description of DATR bits

7.1.4

EEPROM

TEST REGISTER

(TST)

The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the
device user.

AD6

AD5

AD4

AD3

AD2

AD1

AD0

BIT

MNEMONIC

DESCRIPTION

This bit is set to a logic 0.

6 to 2

AD6 to AD2

AD2 to AD6 select one of 32 pages.

1 to 0

AD1 to AD0

AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and
AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0
and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment
mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1
increments after every write to an EEPROM latch, thus enhancing access to sequential
EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when
AD0 and AD1 are both a logic 1.

BIT

MNEMONIC

DESCRIPTION

7 to 0

D7 to D0

The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from
DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write
operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits AD0
and AD1 of ADDR.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

7.2

EEPROM latches

The four EEPROM latches (EEPROM Latch 0 to 3; Fig.5)
cannot be read by user software. Due to their construction,
the latches can only be preset, but not cleared. Successive
write operations through DATR to the EEPROM latches
actually perform a logical OR with the previously stored
data in EEPROM. The EEPROM latches are reset at the
conclusion of any EEPROM cycle.

7.3

EEPROM flags

The four EEPROM flags (F0 to F3; Fig.5) cannot be
directly accessed by user software. An EEPROM flag is
set as a side-effect when the corresponding EEPROM
latch is written through DATR. The EEPROM flags are
reset at the conclusion of any EEPROM cycle.

7.4

EEPROM macros

The instruction sequence used in an EEPROM access
should be treated as an indivisible entity. Erroneous
programs result if ADDR, DATR, RELR or EPCR are
inadvertently changed during an EEPROM cycle or its
setup. Special care should be taken if the program may
asynchronously divert due to an interrupt. Particularly,
a new access to the EEPROM may only be initiated when
no write, erase or erase/write cycles are in progress.
This can be verified by reading bit EWP (register EPCR).

For write, erase and erase/write cycles, it is assumed that
the Timer 2 Reload Register (RELR) has been loaded with
the appropriate value for a 5 ms delay, which depends on
f

xtal

(see Table 23). The end of a write, erase or erase/write

cycle will be signalled by a cleared EWP and by a Timer 2
interrupt provided that ET2I = 1 and that the derivative
interrupt is enabled.

7.5

EEPROM access

One read, one write, one erase/write and one erase
access are defined by bits EWP and MC1 to MC3 in the
EPCR register; see Table 10.

Read byte retrieves the EEPROM byte addressed by
ADDR when DATR is read. Read cycles are
instantaneous.

Write and erase cycles take 5 ms, however. Erase/write is
a combination of an erase and a subsequent write cycle,
consequently taking 10 ms.

As their names imply, write page, erase page and
erase/write page are applied to a whole EEPROM page.
Therefore, bits AD0 and AD1 of register ADDR (see
Table 13), defining the byte location within an EEPROM

page, are irrelevant during write and erase cycles.
However, write and erase cycles need not affect all bytes
of the page. The EEPROM flags F0 to F3 (see Fig.5)
determine which bytes within the EEPROM page are
affected by the erase and/or write cycles. A byte whose
corresponding EEPROM flag is zero remains unchanged.

With erase page, a byte is erased if its corresponding
EEPROM flag is set. With write page, data in EEPROM
Latch 0 to 3 (Fig.5) are ORed to the individual page bytes
if and only if the corresponding EEPROM flags are set.

In an erase/write cycle, F0 to F3 select which page bytes
are erased and ORed with the corresponding EEPROM
latches.

ORing, in this event, means that the EEPROM latches are
copied to the selected page bytes.

The described page-wise organization of erase and write
cycles allows up to four bytes to be individually erased or
written within 5 ms. This advantage necessitates a
preparation step, called page setup, before the actual
erase and/or write cycle can be executed.

Page setup controls EEPROM latches and EEPROM
flags. This will be described in the Sections 7.5.1 to 7.5.5.

7.5.1

AGE SETUP

Page setup is a preparation step required before write
page, erase page and erase/write page cycles.
As previously described, these page operations include
single-byte write, erase and erase/write as a special event.
EEPROM flags F0 to F3 determine which page bytes will
be affected by the mentioned page operations. EEPROM
Latch 0 to 3 must be preset through DATR to specify the
write cycle data to EEPROM and to set the EEPROM flags
as a side-effect. Obviously, the actual preset value of the
EEPROM latches is irrelevant for erase page. Preset of
one, two, three or all four EEPROM latches and the
corresponding EEPROM flags can be performed by
repeatedly defining ADDR and writing to DATR (see
Table 17).

If more than one EEPROM latch must be preset, the
subcounter consisting of AD0 and AD1 can be induced to
auto-increment after every write to DATR, thus stepping
through all EEPROM latches. For this purpose, increment
mode (Table 12) must be selected. Auto-incrementing
stops at EEPROM Latch 3. It is not mandatory to start at
EEPROM Latch 0 as in shown in Table 18.

Note that AD2 to AD6 are irrelevant during page setup.
They will usually specify the intended EEPROM page,
anticipating the subsequent page cycle.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

From now on, it will be assumed that AD2 to AD6 will
contain the intended EEPROM page address after page
setup.

Table 17 Page setup; preset

Table 18 Page setup; auto-incrementing

7.5.2

EAD BYTE

Since ADDR auto-increments after a read cycle regardless
of the page boundary, successive bytes can efficiently be
read by repeating the last instruction.

Table 19 Read byte

7.5.3

RITE PAGE

The write cycle performs a logical OR between the data in
the EEPROM latches and that in the addressed EEPROM
page.

INSTRUCTION

RESULT

MOV A, #addr

address of EEPROM latch

MOV ADDR, A

send address to ADDR

MOV A, #data

load write, erase/write or erase data

MOV DATR, A

send data to addressed EEPROM
latch

INSTRUCTION

RESULT

MOV A, #MC2

increment mode control word

MOV EPCR, A

select increment mode

MOV A, #baddr

EEPROM Latch 0 address
(AD0 = AD1 = 0)

MOV ADDR, A

send EEPROM Latch 0 address to
ADDR

MOV A, R0

load 1

byte from Register 0

MOV DATR, A

send 1

byte to EEPROM Latch 0

MOV A, R1

load 2

byte from Register 1

MOV DATR, A

send 2

byte to EEPROM Latch 1

MOV A, R2

load 3

byte from Register 2

MOV DATR, A

send 3

byte to EEPROM Latch 2

MOV A, R3

load 4

byte from Register 3

MOV DATR, A

send 4

byte to EEPROM Latch 3

INSTRUCTION

RESULT

MOV A, #RDADDR load read address

MOV ADDR, A

send address to ADDR

MOV A, DATR

read EEPROM data

To actually copy the data from the EEPROM latches,
the corresponding bytes in the page should previously
have been erased.

The EEPROM latches are preset as described in
Section 7.5.1. The actual transfer to the EEPROM is then
performed as shown in Table 20.

The last instruction also starts Timer 2. The data in the
EEPROM latches are ORed with that in the corresponding
page bytes within 5 ms. A single-byte write is simply a
special case of `write page'.

ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by bits AD2
to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1).
This allows efficient coding of multi-page write operations.

Table 20 Write page

7.5.4

RASE

WRITE PAGE

The EEPROM latches are preset as described in
Section 7.5.1. The page byte corresponding to the
asserted flags (among F0 to F3) are erased and re-written
with the contents of the respective EEPROM latches.

The last instruction also starts Timer 2. Erasure takes
5 ms upon which Timer Register T2 reloads for another
5 ms cycle for writing. The top cycles together take 10 ms.
A single-byte erase/write is simply a special event of
`erase/write page'.

ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by AD2 to
AD6) and to EEPROM Latch 0 (by AD0 and AD1).
This allows efficient coding of multi-page erase/write
operations.

Table 21 Erase/write page

INSTRUCTION

RESULT

MOV A, #EWP + MC2

`write page' control word

MOV EPCR, A

start `write page' cycle

INSTRUCTION

RESULT

MOV A, #EWP + MC3

`erase/write page' control word

MOV EPCR, A

start `erase/write page' cycle

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

7.5.5

RASE PAGE

The EEPROM flags are set as described in Section 7.5.1.
The corresponding page bytes are erased.

The last instruction also starts Timer 2. Erasure takes
5 ms. A single-byte erase is simply a special case of `erase
page'.

Note that ADDR does not auto-increment after an erase
cycle.

Table 22 Erase page

7.6

Timer 2

Timer 2 is a 8-bit down-counter decremented at a rate of

480

xtal

. It may be used either for EEPROM timing or as

a general purpose timer. Conflicts between the two
applications should be carefully avoided.

7.6.1

IMER

FOR

EEPROM

TIMING

When used for EEPROM timing, Timer 2 serves to
generate the 5 ms intervals needed for erasing or writing

the EEPROM. At the decrement rate of

480

xtal

, the

reload value for a 5 ms interval is a function of f

xtal

Table 23 summarizes the required reload values for a
number of oscillator frequencies.

Timer 2 is started by setting bit EWP in the EPCR.
The Timer Register T2 is loaded with the reload value from
RELR. T2 decrements to zero.

For an erase/write cycle, underflow of T2 indicates the end
of the erase operation. Therefore, Timer Register T2 is
reloaded from RELR for another 5 ms interval during
which the flagged EEPROM latches are copied to the
corresponding bytes in the page addressed by ADDR.

INSTRUCTION

RESULT

MOV A, #EWP + MC3 + MC2 + MC1 `erase page'

control word

MOV EPCR, A

start `erase
page' cycle

The second underflow of an erase/write cycle and the first
underflow of write page and erase page conclude the
corresponding EEPROM cycle. Timer 2 is stopped, T2F is
set whereas EWP and MC1 to MC3 are cleared.

Table 23 Reload values as a function of f

xtal

Note

1. The reload value is (5

480

xtal

)

xtal

in MHz.

7.6.2

IMER

AS A GENERAL PURPOSE TIMER

When used for purposes other than EEPROM timing,
Timer 2 is started by setting STT2. The Timer Register T2
(see Table 26) is loaded with the reload value from RELR.
T2 decrements to zero. On underflow, T2 is reloaded from
RELR, T2F is set and T2 continues to decrement.

Timer 2 can be stopped at any time by clearing STT2.
The value of T2 is then held and can be read out. After
setting STT2 again, Timer 2 decrements from the reload
value. Alternatively, it is possible to read T2 `on the fly' i.e.
while Timer 2 is operating.

xtal

(MHz)

RELOAD VALUE

(1)

(HEX)

3.58

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

DERIVATIVE INTERRUPTS

One derivative interrupt event is defined. It is controlled by
bits T2F and ET2I in the EPCR (see Tables 10 and 11).

The derivative interrupt event occurs when T2F is set. This
request is honoured under the following circumstances:

No interrupt routine proceeds

No external interrupt request is pending

The derivative interrupt is enabled

ET2I is set.

The derivative interrupt routine must include instructions
that will remove the cause of the derivative interrupt by
explicitly clearing T2F. If the derivative interrupt is not
used, T2F may directly be tested by the program.
Obviously, T2F can also be asserted under program
control, e.g. to generate a software interrupt.

TIMING

Although thePCD3755A, PCD3755E and PCD3755F
operate over a clock frequency range from 1 to 16 MHz,
f

xtal

= 3.58 MHz will usually be chosen to take full

advantage of the frequency generator section.

10 RESET

In addition to the conditions given in the

"PCD33xxA

Family" data sheet, all derivative registers are cleared in
the reset state.

11 IDLE MODE

In Idle mode, the frequency generator, the EEPROM and
the Timer 2 sections remain operative. Therefore, the
IDLE instruction may be executed while an erase and/or
write access to EEPROM is in progress.

12 STOP MODE

Since the oscillator is switched off, the frequency
generator, the EEPROM and the Timer 2 sections receive
no clock. It is suggested to clear both the HGF and the
LGF registers before entering Stop mode. This will cut off
the biasing of the internal amplifiers, considerably
reducing current requirements.

The Stop mode must not be entered while an erase
and/or write access to EEPROM is in progress. The STOP
instruction may only be executed when EWP in EPCR is
zero. The Timer 2 section is frozen during Stop mode.
After exit from Stop mode by a HIGH level on CE/T0,
Timer 2 proceeds from the held state.

13 INSTRUCTION SET RESTRICTIONS

As RAM space is restricted to 128 bytes, care should be
taken to avoid accesses to non-existing RAM locations.

14 OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION

Table 24 Port and Power-on-reset configuration

See note 1 and 2.

Notes

1. Port output drive: 1 = standard I/O; 2 = open-drain I/O, see

"PCD33xxA Family" data sheet.

2. Port state after reset: S = Set (HIGH) and R = Reset (LOW).

3. The Melody Output drive type is push-pull.

TYPE

PORT 0

PORT 1

PORT 2

POR

PCD3755A

1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R

(3)

1.3 V

PCD3755E

1S 1S 1S 1S 1S 1S 1S 1S 2S 2S 2S 2S 2S 2S 1S 1S

(3)

2.0 V

PCD3755F

1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R

(3)

2.0 V

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

15 OTP PROGRAMMING

The programming of the PCD3755x and PCD3756x OTPs
is based on the OM4260 programmer (Ceibo MP-51),
available from Philips. The OM4260 works in conjunction
with various adapters supporting the different package
types available as listed in Table 25.

The low-voltage OTP program memory used is of
Anti-Fuse-PROM type and can not be erased after
programming.

Thus, the complete OTP memory cannot be tested by the
factory, but only partially via a special test array.
The average expected yield is 97%.

Detailed information on the OTP programming is available
in the

"PCD3755x Application Note", which is available via

your Philips Sales office.

Table 25 OTP programming overview

Note

1. As the OM5037 is only a socket converter, the OM5007 is also needed to program the PCD3755x/56x in the LQFP32

package.

DEVICE

PHILIPS TYPE NUMBER

CEIBO TYPE NUMBER

SUPPORTED PACKAGE

Ceibo MP-51

OM4260

MP-51 programmer base

PCD3755x/56x

OM5007

PCD3755A / 56A adapter DIP

DIP28

PCD3755x/56x

OM5030

PCD3755A / 56A adapter SO

SO28

PCD3755x/56x

OM5037

(1)

PCD3755A / 56A adapter QFP32 LQFP32

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

16 SUMMARY OF DERIVATIVE REGISTERS

Table 26 Register map

17 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see

"Data Handbook IC14, Section: Handling MOS devices").

18 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

ADDR.

(HEX)

REGISTER

R/W

not used

EEPROM Address Register
(ADDR)

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W

not used

EEPROM Data Register
(DATR)

R/W

EEPROM Control Register
(EPCR)

STT2

ET21

TF2

EWP

MC3

MC2

MC1

R/W

Timer 2 Reload Register
(RELR)

R/W

Timer 2 Register
(T2)

T2.7

T2.6

T2.5

T2.4

T2.3

T2.2

T2.1

T2.0

Test Register
(TST)

only for test purposes; not to be accessed by the device user

08 to 10

not used

High Group Frequency Register
(HGF)

Low Group Frequency Register
(LGF)

Melody Control Register
(MDYCON)

EMO

R/W

14 to FF

not used

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.8

+7.0

all input voltages

0.5

+ 0.5

DC input current

+10

DC output current

+10

tot

total power dissipation

125

power dissipation per output

ground supply current

+50

stg

storage temperature

+150

operating junction temperature

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

19 DC CHARACTERISTICS
V

= 1.8 to 6 V; V

= 0 V; T

amb

25 to +70

C; all voltages with respect to V

; f

xtal

= 3.58 MHz; unless otherwise

specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

see Fig.6

operating

note 1

1.8

RAM data retention in Stop
mode

1.0

operating supply current

see Figs 7 and 8; note 2

= 3 V; value HGF or LGF

0.8

1.6

= 3 V

0.35

0.7

= 5 V; f

xtal

= 10 MHz

1.5

4.0

= 5 V; f

xtal

= 16 MHz

2.4

6.0

DD(idle)

supply current (Idle mode)

see Figs 9 and 10; note 2

= 3 V; value HGF or LGF

0.7

1.4

= 3 V

0.25

0.5

= 5 V; f

xtal

= 10 MHz

1.1

3.4

= 5 V; f

xtal

= 16 MHz

1.7

5.0

DD(stp)

supply current (Stop mode)

see Fig.11; note 3

= 1.8 V; T

amb

= 25

1.0

5.5

= 1.8 V; T

amb

= 70

Inputs

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

input leakage current

Port outputs

LOW level port sink current

= 3 V; V

= 0.4 V; see Fig.12

0.7

3.5

HIGH level pull-up output source
current

= 3 V; V

= 2.7 V; see Fig.13

= 3 V; V

= 0 V; see Fig.13

140

300

OH1

HIGH level push-pull output
source current

= 3 V; V

= 2.6 V; see Fig.14

0.7

3.5

Tone output (see Fig.15; note 4)

HG(RMS)

HGF voltage (RMS)

158

181

205

LG(RMS)

LGF voltage (RMS)

125

142

160

frequency deviation

0.6

+0.6

DC voltage level

0.5V

output impedance

100

500

pre-emphasis of group

1.5

2.0

2.5

THD

total harmonic distortion

amb

= 25

C; note 5

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

Notes

1. TONE output, EEPROM erase and write require V

2.5 V.

2. V

= V

; V

= V

; open-drain outputs connected to V

; all other outputs open; value HGF = LGF = 0, unless

otherwise specified.

a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit.

b) Typical values: T

amb

= 25

C; crystal connected between XTAL1 and XTAL2.

3. V

= V

; V

= V

; RESET, T1 and CE/T0 at V

; crystal connected between XTAL1 and XTAL2; pins T1 and

CE/T0 at V

4. Values are specified for DTMF frequencies only (CEPT).

5. Related to the Low Group Frequency (LGF) component (CEPT).

6. After final testing the value of each EEPROM bit is a logic 1, but this cannot be guaranteed after board assembly.

7. Verified on sampling basis.

EEPROM (notes 1 and 6)

t/w

endurance (erase/write cycles)

note 7

ret

data retention time

years

Power-on-reset (see Fig.16)

POR

Power-on-reset level

PCD3755A

0.8

1.3

1.8

PCD3755E

1.5

2.0

2.5

PCD3755F

1.5

2.0

2.5

Oscillator (see Fig.17)

transconductance

= 5 V

0.2

0.4

1.0

feedback resistor

0.3

1.0

3.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

handbook, halfpage

MLA493

VDD (V)

fxtal

(MHz)

guaranteed
operating range

Fig.6

Maximum clock frequency (f

xtal

) as a

function of supply voltage (V

Fig.7

Typical operating supply current (I

) as a

function of supply voltage (V

Measured with crystal between XTAL1 and XTAL2.

handbook, halfpage

VDD (V)

MGB827

IDD

(mA)

16 MHz

3.58 MHz
HGF or LGF

10 MHz

3.58 MHz

Fig.8

Typical operating supply current (I

) as a

function of clock frequency (f

xtal

Measured with function generator on XTAL1.

handbook, halfpage

MGB828

IDD

(mA)

fxtal (MHz)

3 V

5 V

Fig.9

Typical supply current in Idle mode (I

DD(idle)

)

as a function of supply voltage (V

Measured with crystal between XTAL1 and XTAL2.

handbook, halfpage

VDD (V)

MGB829

IDD(idle)

(mA)

16 MHz

3.58 MHz
HGF or LGF

10 MHz

3.58 MHz

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

21 PACKAGE OUTLINES

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT117-1

92-11-17
95-01-14

min.

max.

1.7
1.3

0.53
0.38

0.32
0.23

36.0
35.0

14.1
13.7

3.9
3.4

0.25

2.54

15.24

15.80
15.24

17.15
15.90

1.7

5.1

0.51

4.0

0.066
0.051

0.020
0.014

0.013
0.009

1.41
1.34

0.56
0.54

0.15
0.13

0.01

0.10

0.60

0.62
0.60

0.68
0.63

0.067

0.20

0.020

0.16

051G05

MO-015AH

(e )

seating plane

pin 1 index

10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

handbook, full pagewidth

DIP28: plastic dual in-line package; 28 leads (600 mil)

SOT117-1

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

2.65

0.30
0.10

2.45
2.25

0.49
0.36

0.32
0.23

18.1
17.7

7.6
7.4

1.27

10.65
10.00

1.1
1.0

0.9
0.4

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1
0.4

SOT136-1

detail X

(A )

0.25

075E06

MS-013AE

pin 1 index

0.10

0.012
0.004

0.096
0.089

0.019
0.014

0.013
0.009

0.71
0.69

0.30
0.29

0.050

1.4

0.055

0.419
0.394

0.043
0.039

0.035
0.016

0.01

0.25

0.01

0.004

0.043
0.016

0.01

10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

22 SOLDERING

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

22.1

Reflow soldering

Reflow soldering techniques are suitable for all LQFP and
SO packages. Reflow soldering requires solder paste (a
suspension of fine solder particles, flux and binding agent)
to be applied to the printed-circuit board by screen printing,
stencilling or pressure-syringe dispensing before package
placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

22.2

Wave soldering

22.2.1

LQFP

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP32 (SOT401-1),
LQFP48 (SOT313-2), LQFP64 (SOT314-2 and
SOT414-1), LQFP80 (SOT315-1) or
LQFP100 (SOT407-1).

22.2.2

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

22.2.3

ETHOD

(LQFP

AND

SO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

22.3

DIP

22.3.1

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

22.4

Repairing soldered joints

Fix LQFP and SO by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

For DIP, apply a low voltage soldering iron (less than 24 V)
to the lead(s) of the package, below the seating plane or
not more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

1997 Apr 16

Philips Semiconductors

Product specification

8-bit microcontrollers with DTMF
generator, 8 kbytes OTP and 128 bytes

PCD3755A; PCD3755E;

PCD3755F

23 DEFINITIONS

24 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA54

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Printed in The Netherlands

417027/1200/04/pp32

Date of release: 1997 Apr 16

Document order number:

9397 750 02065

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