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Электронный компонент: PCD8544U

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DATA SHEET
Product specification
File under Integrated Circuits, IC17
1999 Apr 12
INTEGRATED CIRCUITS
PCD8544
48
84 pixels matrix LCD
controller/driver
1999 Apr 12
2
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
APPLICATIONS
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
6.1
Pin functions
6.1.1
R0 to R47 row driver outputs
6.1.2
C0 to C83 column driver outputs
6.1.3
V
SS1
, V
SS2
: negative power supply rails
6.1.4
V
DD1
, V
DD2
: positive power supply rails
6.1.5
V
LCD1
, V
LCD2
: LCD power supply
6.1.6
T1, T2, T3 and T4: test pads
6.1.7
SDIN: serial data line
6.1.8
SCLK: serial clock line
6.1.9
D/C: mode select
6.1.10
SCE: chip enable
6.1.11
OSC: oscillator
6.1.12
RES: reset
7
FUNCTIONAL DESCRIPTION
7.1
Oscillator
7.2
Address Counter (AC)
7.3
Display Data RAM (DDRAM)
7.4
Timing generator
7.5
Display address counter
7.6
LCD row and column drivers
7.7
Addressing
7.7.1
Data structure
7.8
Temperature compensation
8
INSTRUCTIONS
8.1
Initialization
8.2
Reset function
8.3
Function set
8.3.1
Bit PD
8.3.2
Bit V
8.3.3
Bit H
8.4
Display control
8.4.1
Bits D and E
8.5
Set Y address of RAM
8.6
Set X address of RAM
8.7
Temperature control
8.8
Bias value
8.9
Set V
OP
value
9
LIMITING VALUES
10
HANDLING
11
DC CHARACTERISTICS
12
AC CHARACTERISTICS
12.1
Serial interface
12.2
Reset
13
APPLICATION INFORMATION
14
BONDING PAD LOCATIONS
14.1
Bonding pad information
14.2
Bonding pad location
15
TRAY INFORMATION
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
1999 Apr 12
3
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
1
FEATURES
Single chip LCD controller/driver
48 row, 84 column outputs
Display data RAM 48
84 bits
On-chip:
Generation of LCD supply voltage (external supply
also possible)
Generation of intermediate LCD bias voltages
Oscillator requires no external components (external
clock also possible).
External RES (reset) input pin
Serial interface maximum 4.0 Mbits/s
CMOS compatible inputs
Mux rate: 48
Logic supply voltage range V
DD
to V
SS
: 2.7 to 3.3 V
Display supply voltage range V
LCD
to V
SS
6.0 to 8.5 V with LCD voltage internally generated
(voltage generator enabled)
6.0 to 9.0 V with LCD voltage externally supplied
(voltage generator switched-off).
Low power consumption, suitable for battery operated
systems
Temperature compensation of V
LCD
Temperature range:
-
25 to +70
C.
2
GENERAL DESCRIPTION
The PCD8544 is a low power CMOS LCD controller/driver,
designed to drive a graphic display of 48 rows and
84 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption.
The PCD8544 interfaces to microcontrollers through a
serial bus interface.
The PCD8544 is manufactured in n-well CMOS
technology.
3
APPLICATIONS
Telecommunications equipment.
4
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PCD8544U
-
chip with bumps in tray; 168 bonding pads + 4 dummy pads
-
1999 Apr 12
4
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
5
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGL629
COLUMN DRIVERS
DATA LATCHES
DISPLAY DATA RAM
(DDRAM)
48
84
ADDRESS COUNTER
DATA
REGISTER
ROW DRIVERS
SHIFT REGISTER
RESET
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
OSCILLATOR
I/O BUFFER
BIAS
VOLTAGE
GENERATOR
VLCD
GENERATOR
VLCD2
VLCD1
VDD1 to VDD2
VSS1 to VSS2
T2
T1
T3
T4
SCLK
SDIN
SCE
D/C
RES
OSC
C1 to C83
R0 to R47
PCD8544
1999 Apr 12
5
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
6
PINNING
Note
1. For further details, see Fig.18 and Table 7.
6.1
Pin functions
6.1.1
R0
TO
R47
ROW DRIVER OUTPUTS
These pads output the row signals.
6.1.2
C0
TO
C83
COLUMN DRIVER OUTPUTS
These pads output the column signals.
6.1.3
V
SS1
, V
SS2
:
NEGATIVE POWER SUPPLY RAILS
Supply rails V
SS1
and V
SS2
must be connected together.
6.1.4
V
DD1
, V
DD2
:
POSITIVE POWER SUPPLY RAILS
Supply rails V
DD1
and V
DD2
must be connected together.
SYMBOL
DESCRIPTION
R0 to R47
LCD row driver outputs
C0 to C83
LCD column driver outputs
V
SS1
, V
SS2
ground
V
DD1
, V
DD2
supply voltage
V
LCD1
, V
LCD2
LCD supply voltage
T1
test 1 input
T2
test 2 output
T3
test 3 input/output
T4
test 4 input
SDIN
serial data input
SCLK
serial clock input
D/C
data/command
SCE
chip enable
OSC
oscillator
RES
external reset input
dummy1, 2, 3, 4 not connected
6.1.5
V
LCD1
, V
LCD2
: LCD
POWER SUPPLY
Positive power supply for the liquid crystal display. Supply
rails V
LCD1
and V
LCD2
must be connected together.
6.1.6
T1, T2, T3
AND
T4:
TEST PADS
T1, T3 and T4 must be connected to V
SS
, T2 is to be left
open. Not accessible to user.
6.1.7
SDIN:
SERIAL DATA LINE
Input for the data line.
6.1.8
SCLK:
SERIAL CLOCK LINE
Input for the clock signal: 0.0 to 4.0 Mbits/s.
6.1.9
D/C:
MODE SELECT
Input to select either command/address or data input.
6.1.10
SCE:
CHIP ENABLE
The enable pin allows data to be clocked in. The signal is
active LOW.
6.1.11
OSC:
OSCILLATOR
When the on-chip oscillator is used, this input must be
connected to V
DD
. An external clock signal, if used, is
connected to this input. If the oscillator and external clock
are both inhibited by connecting the OSC pin to V
SS
, the
display is not clocked and may be left in a DC state.
To avoid this, the chip should always be put into
Power-down mode before stopping the clock.
6.1.12
RES:
RESET
This signal will reset the device and must be applied to
properly initialize the chip. The signal is active LOW.
1999 Apr 12
6
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
7
FUNCTIONAL DESCRIPTION
7.1
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
DD
. An external
clock signal, if used, is connected to this input.
7.2
Address Counter (AC)
The address counter assigns addresses to the display
data RAM for writing. The X-address X
6
to X
0
and the
Y-address Y
2
to Y
0
are set separately. After a write
operation, the address counter is automatically
incremented by 1, according to the V flag.
7.3
Display Data RAM (DDRAM)
The DDRAM is a 48
84 bit static RAM which stores the
display data. The RAM is divided into six banks of 84 bytes
(6
8
84 bits). During RAM access, data is transferred
to the RAM through the serial interface. There is a direct
correspondence between the X-address and the column
output number.
7.4
Timing generator
The timing generator produces the various signals
required to drive the internal circuits. Internal chip
operation is not affected by operations on the data buses.
7.5
Display address counter
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD through the column
outputs. The display status (all dots on/off and
normal/inverse video) is set by bits E and D in the `display
control' command.
7.6
LCD row and column drivers
The PCD8544 contains 48 row and 84 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 2 shows typical waveforms. Unused
outputs should be left unconnected.
1999 Apr 12
7
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.2 Typical LCD driver waveforms.
V
state1
(t) = C1(t) - R0(t).
V
state2
(t) = C1(t) - R1(t).
MGL637
ROW 0
R0 (t)
ROW 1
R1 (t)
COL 0
C0 (t)
COL 1
C1 (t)
VLCD
V2
V3
V4
V5
VSS
VLCD
VSS
VLCD
VSS
VLCD
VLCD
V3 - VSS
VLCD - V2
V3 - V2
0 V
VLCD
V3 - VSS
VLCD - V2
V3 - V2
0 V
-
VLCD
V4 - VLCD
VSS - V5
V4 - V5
0 V
-
VLCD
V4 - VLCD
VSS - V5
V4 - V5
0 V
VSS
V2
V3
V4
V5
V2
V3
V4
V5
V2
V3
V4
V5
frame n
frame n
+
1
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
... 47
... 47
Vstate1(t)
Vstate2(t)
Vstate1(t)
Vstate2(t)
1999 Apr 12
8
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.3 DDRAM to display mapping.
top of LCD
MGL636
DDRAM
bank 0
R0
R8
R16
R24
R32
R40
R47
bank 1
bank 2
bank 3
bank 4
bank 5
LCD
1999 Apr 12
9
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
7.7
Addressing
Data is downloaded in bytes into the 48 by 84 bits RAM
data display matrix of PCD8544, as indicated in
Figs. 3, 4, 5 and 6. The columns are addressed by the
address pointer. The address ranges are: X 0 to 83
(1010011), Y 0 to 5 (101). Addresses outside these
ranges are not allowed. In the vertical addressing mode
(V = 1), the Y address increments after each byte (see
Fig.5). After the last Y address (Y = 5), Y wraps around
to 0 and X increments to address the next column. In the
horizontal addressing mode (V = 0), the X address
increments after each byte (see Fig.6). After the last
X address (X = 83), X wraps around to 0 and
Y increments to address the next row. After the very last
address (X = 83 and Y = 5), the address pointers wrap
around to address (X = 0 and Y = 0).
7.7.1
D
ATA STRUCTURE
Fig.4 RAM format, addressing.
handbook, full pagewidth
MGL638
0
0
5
LSB
MSB
Y-address
X-address
83
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
handbook, halfpage
MGL639
0
0
5
503
5
4
3
2
1
0
7
6
Y-address
X-address
83
1999 Apr 12
10
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
handbook, halfpage
MGL640
0
0
5
503
420
336
252
168
421
337
253
169
84
0
85
1
422
338
254
170
86
2
Y-address
X-address
83
7.8
Temperature compensation
Due to the temperature dependency of the liquid crystals'
viscosity, the LCD controlling voltage V
LCD
must be
increased at lower temperatures to maintain optimum
contrast. Figure 7 shows V
LCD
for high multiplex rates.
In the PCD8544, the temperature coefficient of V
LCD
, can
be selected from four values (see Table 2) by setting bits
TC
1
and TC
0
.
Fig.7 V
LCD
as function of liquid crystal temperature (typical values).
handbook, halfpage
MGL641
0
C
(1)
(2)
(3)
(4)
VLCD
temperature
(1) Upper limit.
(2) Typical curve.
(3) Temperature coefficient of IC.
(4) Lower limit.
1999 Apr 12
11
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
8
INSTRUCTIONS
The instruction format is divided into two modes: If D/C
(mode select) is set LOW, the current byte is interpreted as
command byte (see Table 1). Figure 8 shows an example
of a serial data stream for initializing the chip. If D/C is set
HIGH, the following bytes are stored in the display data
RAM. After every data byte, the address counter is
incremented automatically.
The level of the D/C signal is read during the last bit of data
byte.
Each instruction can be sent in any order to the PCD8544.
The MSB of a byte is transmitted first. Figure 9 shows one
possible command stream, used to set up the LCD driver.
The serial interface is initialized when SCE is HIGH. In this
state, SCLK clock pulses have no effect and no power is
consumed by the serial interface. A negative edge on SCE
enables the serial interface and indicates the start of a data
transmission.
Fig.8 General format of data stream.
handbook, halfpage
MGL666
data
data
MSB (DB7)
LSB (DB0)
Fig.9 Serial data stream, example.
handbook, full pagewidth
MGL642
function set (H = 1)
bias system
set VOP
temperature control
function set (H = 0)
display control
X address
Y address
Figures 10 and 11 show the serial bus protocol.
When SCE is HIGH, SCLK clock signals are ignored;
during the HIGH time of SCE, the serial interface is
initialized (see Fig.12)
SDIN is sampled at the positive edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1); it is read with the eighth SCLK
pulse
If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects bit 7 of the next byte at
the next positive edge of SCLK (see Fig.12)
A reset pulse with RES interrupts the transmission.
No data is written into the RAM. The registers are
cleared. If SCE is LOW after the positive edge of RES,
the serial interface is ready to receive bit 7 of a
command/data byte (see Fig.13).
1999 Apr 12
12
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.10 Serial bus protocol - transmission of one byte.
handbook, full pagewidth
DB7
SDIN
SCLK
SCE
D/C
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGL630
Fig.11 Serial bus protocol - transmission of several bytes.
handbook, full pagewidth
DB7
SDIN
SCLK
SCE
D/C
DB6
DB5
DB4
DB3
DB0
DB1
DB2
DB7
DB6
DB5
DB0
DB7 DB6
DB5
MGL631
DB4
DB3
DB2
DB1
1999 Apr 12
13
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.12 Serial bus reset function (SCE).
handbook, full pagewidth
DB7
SDIN
SCLK
RES
SCE
D/C
DB6
DB5
DB4
DB3
DB0
DB1
DB2
DB7
DB6
DB5
DB0
DB7 DB6
DB5
MGL632
DB4
DB3
DB2
DB1
Fig.13 Serial bus reset function (RES).
handbook, full pagewidth
DB7
SDIN
SCLK
RES
SCE
D/C
DB6
DB5
DB4
DB3
DB7
DB6
DB5
DB4
DB7
DB6 DB5
DB4
MGL633
DB3
DB2
DB1
DB0
1999 Apr 12
14
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Table 1
Instruction set
Table 2
Explanations of symbols in Table 1
INSTRUCTION
D/C
COMMAND BYTE
DESCRIPTION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
(H = 0 or 1)
NOP
0
0
0
0
0
0
0
0
0
no operation
Function set
0
0
0
1
0
0
PD
V
H
power down control; entry
mode; extended instruction set
control (H)
Write data
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
writes data to display RAM
(H = 0)
Reserved
0
0
0
0
0
0
1
X
X
do not use
Display control
0
0
0
0
0
1
D
0
E
sets display configuration
Reserved
0
0
0
0
1
X
X
X
X
do not use
Set Y address of
RAM
0
0
1
0
0
0
Y
2
Y
1
Y
0
sets Y-address of RAM;
0
Y
5
Set X address of
RAM
0
1
X
6
X
5
X
4
X
3
X
2
X
1
X
0
sets X-address part of RAM;
0
X
83
(H = 1)
Reserved
0
0
0
0
0
0
0
0
1
do not use
0
0
0
0
0
0
0
1
X
do not use
Temperature
control
0
0
0
0
0
0
1
TC
1
TC
0
set Temperature Coefficient
(TC
x
)
Reserved
0
0
0
0
0
1
X
X
X
do not use
Bias system
0
0
0
0
1
0
BS
2
BS
1
BS
0
set Bias System (BS
x
)
Reserved
0
0
1
X
X
X
X
X
X
do not use
Set V
OP
0
1
V
OP6
V
OP5
V
OP4
V
OP3
V
OP2
V
OP1
V
OP0
write V
OP
to register
BIT
0
1
PD
chip is active
chip is in Power-down mode
V
horizontal addressing
vertical addressing
H
use basic instruction set
use extended instruction set
D and E
00
display blank
10
normal mode
01
all display segments on
11
inverse video mode
TC
1
and TC
0
00
V
LCD
temperature coefficient 0
01
V
LCD
temperature coefficient 1
10
V
LCD
temperature coefficient 2
11
V
LCD
temperature coefficient 3
1999 Apr 12
15
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
8.1
Initialization
Immediately following power-on, the contents of all internal
registers and of the RAM are undefined. A RES pulse
must be applied
. Attention should be paid to the
possibility that the device may be damaged if not properly
reset.
All internal registers are reset by applying an external RES
pulse (active LOW) at pad 31, within the specified time.
However, the RAM contents are still undefined. The state
after reset is described in Section 8.2.
The RES input must be
0.3V
DD
when V
DD
reaches V
DDmin
(or higher) within a maximum time of 100 ms after V
DD
goes HIGH (see Fig.16).
8.2
Reset function
After reset, the LCD driver has the following state:
Power-down mode (bit PD = 1)
Horizontal addressing (bit V = 0) normal instruction set
(bit H = 0)
Display blank (bit E = D = 0)
Address counter X
6
to X
0
= 0; Y
2
to Y
0
= 0
Temperature control mode (TC
1
TC
0
= 0)
Bias system (BS
2
to BS
0
= 0)
V
LCD
is equal to 0, the HV generator is switched off
(V
OP6
to V
OP0
= 0)
After power-on, the RAM contents are undefined.
8.3
Function set
8.3.1
B
IT
PD
All LCD outputs at V
SS
(display off)
Bias generator and V
LCD
generator off, V
LCD
can be
disconnected
Oscillator off (external clock possible)
Serial bus, command, etc. function
Before entering Power-down mode, the RAM needs to
be filled with `0's to ensure the specified current
consumption.
8.3.2
B
IT
V
When V = 0, the horizontal addressing is selected.
The data is written into the DDRAM as shown in Fig.6.
When V = 1, the vertical addressing is selected. The data
is written into the DDRAM, as shown in Fig.5.
8.3.3
B
IT
H
When H = 0 the commands `display control', `set
Y address' and `set X address' can be performed; when
H = 1, the others can be executed. The `write data' and
`function set' commands can be executed in both cases.
8.4
Display control
8.4.1
B
ITS
D
AND
E
Bits D and E select the display mode (see Table 2).
8.5
Set Y address of RAM
Y
n
defines the Y vector addressing of the display RAM.
Table 3
Y vector addressing
8.6
Set X address of RAM
The X address points to the columns. The range of X is
0 to 83 (53H).
8.7
Temperature control
The temperature coefficient of V
LCD
is selected by bits
TC
1
and TC
0
.
8.8
Bias value
The bias voltage levels are set in the ratio of
R - R - nR - R - R, giving a 1/(n + 4) bias system. Different
multiplex rates require different factors n (see Table 4).
This is programmed by BS
2
to BS
0
. For Mux 1 : 48, the
optimum bias value n, resulting in 1/8 bias, is given by:
(1)
Y
2
Y
1
Y
0
BANK
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
n
48
3
3.928
4
=
=
=
1999 Apr 12
16
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Table 4
Programming the required bias system
Table 5
LCD bias voltage
BS
2
BS
1
BS
0
n
RECOMMENDED
MUX RATE
0
0
0
7
1 : 100
0
0
1
6
1 : 80
0
1
0
5
1 : 65/1 : 65
0
1
1
4
1 : 48
1
0
0
3
1 : 40/1 : 34
1
0
1
2
1 : 24
1
1
0
1
1 : 18/1 : 16
1
1
1
0
1 : 10/1 : 9/1 : 8
SYMBOL
BIAS VOLTAGES
BIAS VOLTAGE FOR
1
/
8
BIAS
V1
V
LCD
V
LCD
V2
(n + 3)/(n + 4)
7
/
8
V
LCD
V3
(n + 2)/(n + 4)
6
/
8
V
LCD
V4
2/(n + 4)
2
/
8
V
LCD
V5
1/(n + 4)
1
/
8
V
LCD
V6
V
SS
V
SS
8.9
Set V
OP
value
The operation voltage V
LCD
can be set by software.
The values are dependent on the liquid crystal selected.
V
LCD
= a + (V
OP6
to V
OP0
)
b [V]. In the PCD8544,
a = 3.06 and b = 0.06 giving a program range of
3.00 to 10.68 at room temperature.
Note that the charge pump is turned off if V
OP6
to V
OP0
is
set to zero.
For Mux 1 : 48, the optimum operation voltage of the liquid
can be calculated as:
(2)
where V
th
is the threshold voltage of the liquid crystal
material used.
Caution, as V
OP
increases with lower temperatures,
care must be taken not to set a V
OP
that will exceed the
maximum of 8.5 V when operating at
-
25
C.
V
LCD
1
48
+
2
1
1
48
----------
--------------------------------------- V
th
6.06 V
th
=
=
Fig.14 V
OP
programming.
a = 3.06.
b = 0.06.
V
OP6
to V
OP0
(programmed) [00 to 7FH].
handbook, halfpage
MGL643
00 01 02 03 04 05 06 07 08 09 0A ...
VLCD
b
a
1999 Apr 12
17
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); see notes 1 and 2.
Notes
1. Stresses above those listed under limiting values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
V
SS
unless otherwise noted.
3. With external LCD supply voltage externally supplied (voltage generator disabled). V
DDmax
= 5 V if LCD supply
voltage is internally generated (voltage generator enabled).
4. When setting V
LCD
by software, take care not to set a V
OP
that will exceed the maximum of 8.5 V when operating at
-
25
C, see Caution in Section 8.9.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see
"Handling MOS devices").
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
supply voltage
note 3
-
0.5
+7
V
V
LCD
supply voltage LCD
note 4
-
0.5
+10
V
V
i
all input voltages
-
0.5
V
DD
+ 0.5
V
I
SS
ground supply current
-
50
+50
mA
I
I
, I
O
DC input or output current
-
10
+10
mA
P
tot
total power dissipation
-
300
mW
P
O
power dissipation per output
-
30
mW
T
amb
operating ambient temperature
-
25
+70
C
T
j
operating junction temperature
-
65
+150
C
T
stg
storage temperature
-
65
+150
C
1999 Apr 12
18
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
11 DC CHARACTERISTICS
V
DD
= 2.7 to 3.3 V; V
SS
= 0 V; V
LCD
= 6.0 to 9.0 V; T
amb
=
-
25 to +70
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD1
supply voltage 1
LCD voltage externally
supplied (voltage generator
disabled)
2.7
-
3.3
V
V
DD2
supply voltage 2
LCD voltage internally
generated (voltage
generator enabled)
2.7
-
3.3
V
V
LCD1
LCD supply voltage
LCD voltage externally
supplied (voltage generator
disabled)
6.0
-
9.0
V
V
LCD2
LCD supply voltage
LCD voltage internally
generated (voltage
generator enabled); note 1
6.0
-
8.5
V
I
DD1
supply current 1 (normal mode)
for internal V
LCD
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0; T
amb
= 25
C;
display load = 10
A; note 2
-
240
300
A
I
DD2
supply current 2 (normal mode)
for internal V
LCD
V
DD
= 2.70 V; V
LCD
= 7.0 V;
f
SCLK
= 0; T
amb
= 25
C;
display load = 10
A; note 2
-
-
320
A
I
DD3
supply current 3 (Power-down
mode)
with internal or external LCD
supply voltage; note 3
-
1.5
-
A
I
DD4
supply current external V
LCD
V
DD
= 2.85 V; V
LCD
= 9.0 V;
f
SCLK
= 0; notes 2 and 4
-
25
-
A
I
LCD
supply current external V
LCD
V
DD
= 2.7 V; V
LCD
= 7.0 V;
f
SCLK
= 0; T = 25
C;
display load = 10
A;
notes 2 and 4
-
42
-
A
Logic
V
IL
LOW level input voltage
V
SS
-
0.3V
DD
V
V
IH
HIGH level input voltage
0.7V
DD
-
V
DD
V
I
L
leakage current
V
I
= V
DD
or V
SS
-
1
-
+1
A
Column and row outputs
R
o(C)
column output resistance
C0 to C83
-
12
20
k
R
o(R)
row output resistance R0 to R47
-
12
20
k
V
bias(tol)
bias voltage tolerance on
C0 to C83 and R0 to R47
-
100
0
+100
mV
1999 Apr 12
19
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Notes
1. The maximum possible V
LCD
voltage that may be generated is dependent on voltage, temperature and (display) load.
2. Internal clock.
3. RAM contents equal `0'. During power-down, all static currents are switched off.
4. If external V
LCD
, the display load current is not transmitted to I
DD
.
5. Tolerance depends on the temperature (typically zero at 27
C, maximum tolerance values are measured at the
temperate range limit).
LCD supply voltage generator
V
LCD
V
LCD
tolerance internally
generated
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0;
display load = 10
A; note 5
-
0
300
mV
TC0
V
LCD
temperature coefficient 0
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0;
display load = 10
A
-
1
-
mV/K
TC1
V
LCD
temperature coefficient 1
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0;
display load = 10
A
-
9
-
mV/K
TC2
V
LCD
temperature coefficient 2
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0;
display load = 10
A
-
17
-
mV/K
TC3
V
LCD
temperature coefficient 3
V
DD
= 2.85 V; V
LCD
= 7.0 V;
f
SCLK
= 0;
display load = 10
A
-
24
-
mV/K
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1999 Apr 12
20
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
12 AC CHARACTERISTICS
Notes
1.
2. RES may be LOW before V
DD
goes HIGH.
3. t
h5
is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE
(see Fig.15).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
OSC
oscillator frequency
20
34
65
kHz
f
clk(ext)
external clock frequency
10
32
100
kHz
f
frame
frame frequency
f
OSC
or f
clk(ext)
= 32 kHz; note 1
-
67
-
Hz
t
VHRL
V
DD
to RES LOW
Fig.16
0
(2)
-
30
ms
t
WL(RES)
RES LOW pulse width
Fig.16
100
-
-
ns
Serial bus timing characteristics
f
SCLK
clock frequency
V
DD
= 3.0 V
10%
0
-
4.00
MHz
T
cy
clock cycle SCLK
All signal timing is based on
20% to 80% of V
DD
and
maximum rise and fall times of
10 ns
250
-
-
ns
t
WH1
SCLK pulse width HIGH
100
-
-
ns
t
WL1
SCLK pulse width LOW
100
-
-
ns
t
su2
SCE set-up time
60
-
-
ns
t
h2
SCE hold time
100
-
-
ns
t
WH2
SCE min. HIGH time
100
-
-
ns
t
h5
SCE start hold time; note 3
100
-
-
ns
t
su3
D/C set-up time
100
-
-
ns
t
h3
D/C hold time
100
-
-
ns
t
su4
SDIN set-up time
100
-
-
ns
t
h4
SDIN hold time
100
-
-
ns
T
frame
f
clk ext
(
)
480
--------------------
=
1999 Apr 12
21
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
12.1
Serial interface
12.2
Reset
Fig.15 Serial interface timing.
handbook, full pagewidth
tsu2
tsu3
tsu4
th3
th5
th4
tWL1
SCE
D/C
SCLK
SDIN
MGL644
tWH1
th2
tWH2
tsu2
Tcy
th5
Fig.16 Reset timing.
handbook, full pagewidth
MGL645
tWL(RES)
VDD
RES
tRW
1999 Apr 12
22
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
13 APPLICATION INFORMATION
Table 6
Programming example
STEP
SERIAL BUS BYTE
DISPLAY
OPERATION
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
start
SCE is going LOW
2
0
0
0
1
0
0
0
0
1
function set
PD = 0 and V = 0, select
extended instruction set
(H = 1 mode)
3
0
1
0
0
1
0
0
0
0
set V
OP
; V
OP
is set to a
+16
b [V]
4
0
0
0
1
0
0
0
0
0
function set
PD = 0 and V = 0, select
normal instruction set
(H = 0 mode)
5
0
0
0
0
0
1
1
0
0
display control set
normal mode
(D = 1 and E = 0)
6
1
0
0
0
1
1
1
1
1
data write Y and X are
initialized to 0 by default,
so they are not set here
7
1
0
0
0
0
0
1
0
1
data write
8
1
0
0
0
0
0
1
1
1
data write
9
1
0
0
0
0
0
0
0
0
data write
10
1
0
0
0
1
1
1
1
1
data write
MGL673
MGL674
MGL675
MGL675
MGL676
1999 Apr 12
23
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
The pinning is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48
84 pixels.
11
1
0
0
0
0
0
1
0
0
data write
12
1
0
0
0
1
1
1
1
1
data write
13
0
0
0
0
0
1
1
0
1
display control; set
inverse video mode
(D = 1 and E = 1)
14
0
1
0
0
0
0
0
0
0
set X address of RAM;
set address to `0000000'
15
1
0
0
0
0
0
0
0
0
data write
STEP
SERIAL BUS BYTE
DISPLAY
OPERATION
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGL677
MGL678
MGL679
MGL679
MGL680
Fig.17 Application diagram.
handbook, halfpage
MGL635
DISPLAY 48
84 pixels
PCD8544
I/O
VDD VSS VLCD
Cext
8
84
24
24
The required minimum value for the external capacitors is:
C
ext
= 1.0
F.
Higher capacitor values are recommended for ripple
reduction.
14 BONDING PAD LOCATIONS
14.1
Bonding pad information (see Fig.18)
PARAMETER
SIZE
Pad pitch
min. 100
m
Pad size, aluminium
80
100
m
Bump dimensions
59
89
17.5 (
5)
m
Wafer thickness
max. 380
m
1999
Apr
12
24
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
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14.2
Bonding pad location
handbook, full pagewidth
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
MGR935
12.97 mm
2.5
mm
PCD8544-1
PCD8544-1
x
y
0
0
12.97 mm
2.5 mm
pitch
y
x
Fig.18 Bonding pad locations.
1999 Apr 12
25
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Table 7
Bonding pad locations (dimensions in
m).
All X/Y coordinates are referenced to the centre
of chip (see Fig.18)
PAD
PAD NAME
x
y
1
dummy1
+5932
+1060
2
R36
+5704
+1060
3
R37
+5604
+1060
4
R38
+5504
+1060
5
R39
+5404
+1060
6
R40
+5304
+1060
7
R41
+5204
+1060
8
R42
+5104
+1060
9
R43
+5004
+1060
10
R44
+4904
+1060
11
R45
+4804
+1060
12
R46
+4704
+1060
13
R47
+4604
+1060
14
V
DD1
+4330
+1085
15
V
DD1
+4230
+1085
16
V
DD1
+4130
+1085
17
V
DD1
+4030
+1085
18
V
DD1
+3930
+1085
19
V
DD2
+3750
+1085
20
V
DD2
+3650
+1085
21
V
DD2
+3550
+1085
22
V
DD2
+3450
+1085
23
V
DD2
+3350
+1085
24
V
DD2
+3250
+1085
25
V
DD2
+3150
+1085
26
V
DD2
+3050
+1085
27
SCLK
+2590
+1085
28
SDIN
+2090
+1085
29
D/C
+1090
+1085
30
SCE
+90
+1085
31
RES
-
910
+1085
32
OSC
-
1410
+1085
33
T3
-
1826
+1085
34
V
SS2
-
2068
+1085
35
V
SS2
-
2168
+1085
36
V
SS2
-
2268
+1085
37
V
SS2
-
2368
+1085
38
V
SS2
-
2468
+1085
39
T4
-
2709
+1085
40
V
SS1
-
2876
+1085
41
V
SS1
-
2976
+1085
42
V
SS1
-
3076
+1085
43
V
SS1
-
3176
+1085
44
T1
-
3337
+1085
45
V
LCD2
-
3629
+1085
46
V
LCD2
-
3789
+1085
47
V
LCD1
-
4231
+1085
48
V
LCD1
-
4391
+1085
49
T2
-
4633
+1085
50
R23
-
4894
+1060
51
R22
-
4994
+1060
52
R21
-
5094
+1060
53
R20
-
5194
+1060
54
R19
-
5294
+1060
55
R18
-
5394
+1060
56
R17
-
5494
+1060
57
R16
-
5594
+1060
58
R15
-
5694
+1060
59
R14
-
5794
+1060
60
R13
-
5894
+1060
61
R12
-
5994
+1060
62
dummy2
-
6222
+1060
63
dummy3
-
6238
-
738
64
R0
-
5979
-
738
65
R1
-
5879
-
738
66
R2
-
5779
-
738
67
R3
-
5679
-
738
68
R4
-
5579
-
738
69
R5
-
5479
-
738
70
R6
-
5379
-
738
71
R7
-
5279
-
738
72
R8
-
5179
-
738
73
R9
-
5079
-
738
74
R10
-
4979
-
738
75
R11
-
4879
-
738
76
C0
-
4646
-
746
PAD
PAD NAME
x
y
1999 Apr 12
26
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
77
C1
-
4546
-
746
78
C2
-
4446
-
746
79
C3
-
4346
-
746
80
C4
-
4246
-
746
81
C5
-
4146
-
746
82
C6
-
4046
-
746
83
C7
-
3946
-
746
84
C8
-
3846
-
746
85
C9
-
3746
-
746
86
C10
-
3646
-
746
87
C11
-
3546
-
746
88
C12
-
3446
-
746
89
C13
-
3346
-
746
90
C14
-
3246
-
746
91
C15
-
3146
-
746
92
C16
-
3046
-
746
93
C17
-
2946
-
746
94
C18
-
2846
-
746
95
C19
-
2746
-
746
96
C20
-
2646
-
746
97
C21
-
2546
-
746
98
C22
-
2446
-
746
99
C23
-
2346
-
746
100
C24
-
2246
-
746
101
C25
-
2146
-
746
102
C26
-
2046
-
746
103
C27
-
1946
-
746
104
C28
-
1696
-
746
105
C29
-
1596
-
746
106
C30
-
1496
-
746
107
C31
-
1396
-
746
108
C32
-
1296
-
746
109
C33
-
1196
-
746
110
C34
-
1096
-
746
111
C35
-
996
-
746
112
C36
-
896
-
746
113
C37
-
796
-
746
114
C38
-
696
-
746
115
C39
-
596
-
746
116
C40
-
496
-
746
117
C41
-
396
-
746
PAD
PAD NAME
x
y
118
C42
-
296
-
746
119
C43
-
196
-
746
120
C44
-
96
-
746
121
C45
+4
-
746
122
C46
+104
-
746
123
C47
+204
-
746
124
C48
+304
-
746
125
C49
+404
-
746
126
C50
+504
-
746
127
C51
+604
-
746
128
C52
+704
-
746
139
C53
+804
-
746
130
C54
+904
-
746
131
C55
+1004
-
746
132
C56
+1254
-
746
133
C57
+1354
-
746
134
C58
+1454
-
746
135
C59
+1554
-
746
136
C60
+1654
-
746
137
C61
+1754
-
746
138
C62
+1854
-
746
139
C63
+1954
-
746
140
C64
+2054
-
746
141
C65
+2154
-
746
142
C66
+2254
-
746
143
C67
+2354
-
746
144
C68
+2454
-
746
145
C69
+2554
-
746
146
C70
+2654
-
746
147
C71
+2754
-
746
148
C72
+2854
-
746
149
C73
+2954
-
746
150
C74
+3054
-
746
151
C75
+3154
-
746
152
C76
+3254
-
746
153
C77
+3354
-
746
154
C78
+3454
-
746
155
C79
+3554
-
746
156
C80
+3654
-
746
157
C81
+3754
-
746
158
C82
+3854
-
746
PAD
PAD NAME
x
y
1999 Apr 12
27
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
159
C83
+3954
-
746
160
R35
+4328
-
738
161
R34
+4428
-
738
162
R33
+4528
-
738
163
R32
+4628
-
738
164
R31
+4728
-
738
165
R30
+4828
-
738
166
R29
+4928
-
738
167
R28
+5028
-
738
168
R27
+5128
-
738
169
R26
+5228
-
738
170
R25
+5328
-
738
171
R24
+5428
-
738
172
dummy4
+5694
-
738
PAD
PAD NAME
x
y
1999 Apr 12
28
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
Fig.19 Device protection diagram.
handbook, full pagewidth
MGL634
VLCD2
VSS1
LCD O/Ps
VDD2
VSS1
T2, T3
VDD1, VDD2
VSS1
VDD SUPPLY
VLCD1, VLCD2
VSS1
VLCD SUPPLY
VLCD2
VDD1
VSS1
VSS1
VSS2
VSS1
VDD1
INPUT PINS
SCLK, SDIN, OSC,
RES, D/C, SCE,
T1, T4
VLCD1
VSS2
VSS1
1999 Apr 12
29
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
15 TRAY INFORMATION
Fig.20 Tray details.
handbook, full pagewidth
MGL646
D
C
A
x
y
F
E
B
For the dimensions of x, y and A to F, see Table 8.
Fig.21 Tray alignment.
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with
respect to the chamfer on the upper left corner of the tray.
Refer to the bonding pad location diagram for the
orientation and position of the type name on the die
surface.
handbook, halfpage
MGL647
PCD8544-1
Table 8
Dimensions
DIM.
DESCRIPTION
VALUE
A
pocket pitch, in the x direction
14.82 mm
B
pocket pitch, in the y direction
4.39 mm
C
pocket width, in the x direction
13.27 mm
D
pocket width, in the y direction
2.8 mm
E
tray width, in the x direction
50.67 mm
F
tray width, in the y direction
50.67 mm
x
no. of pockets in the x direction
3
y
no. of pockets in the y direction
11
1999 Apr 12
30
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Apr 12
31
Philips Semiconductors
Product specification
48
84 pixels matrix LCD controller/driver
PCD8544
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Printed in The Netherlands
465008/750/01/pp32
Date of release: 1999 Apr 12
Document order number:
9397 750 05024