Document Outline

CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 PIN FUNCTIONS
- 7.1 RS: register select (parallel control)
- 7.2 R/W: read/write (parallel control)
- 7.3 E: data bus clock
- 7.4 DB0 to DB7: data bus
- 7.5 C1 to C60: column driver outputs
- 7.6 R1 to R32: row driver outputs
- 7.7 VLCD : LCD power supply
- 7.8 V0 : VLCD control input
- 7.9 OSC: oscillator
- 7.10 SCL: serial clock line
- 7.11 SDA: serial data line
- 7.12 SA0: address pin
- 7.13 T1: test pad
8 FUNCTIONAL DESCRIPTION
- 8.1 LCD supply voltage generator, PCF2114x and PCF2116x
- 8.2 LCD supply voltage generator, PCF2116K
- 8.3 Character generator ROM (CGROM)
- 8.4 LCD bias voltage generator
- 8.5 Oscillator
- 8.6 External clock
- 8.7 Power-on reset
- 8.8 Registers
- 8.9 Busy Flag
- 8.10 Address Counter (AC)
- 8.11 Display data RAM (DDRAM)
- 8.12 Character generator ROM (CGROM)
- 8.13 Character generator RAM (CGRAM)
- 8.14 Cursor control circuit
- 8.15 Timing generator
- 8.16 LCD row and column drivers
- 8.17 Programming MUX 1 : 16 displays with the PCF2114x
- 8.18 Programming MUX 1 : 32 displays with the PCF2114x
- 8.19 Reset function
9 INSTRUCTIONS
- 9.1 Clear display
- 9.2 Return home
- 9.3 Entry mode set
- 9.4 Display on/off control
- 9.5 Cursor/display shift
- 9.6 Function set
- 9.7 Set CGRAM address
- 9.8 Set DDRAM address
- 9.9 Read busy flag and address
- 9.10 Write data to CGRAM or DDRAM
- 9.11 Read data from CGRAM or DDRAM
10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE)
11 INTERFACE TO MICROCONTROLLER (I 2 C-BUS INTERFACE)
- 11.1 Characteristics of the I 2 C-bus
- 11.2 Bit transfer
- 11.3 START and STOP conditions
- 11.4 System configuration
- 11.5 Acknowledge
- 11.6 I 2 C-bus protocol
12 LIMITING VALUES
13 HANDLING
14 DC CHARACTERISTICS
15 DC CHARACTERISTICS (PCF2116K)
16 AC CHARACTERISTICS
17 TIMING CHARACTERISTICS
18 APPLICATION INFORMATION
- 18.1 8-bit operation, 1-line display using internal reset
- 18.2 4-bit operation, 1-line display using internal reset
- 18.3 8-bit operation, 2-line display
- 18.4 I 2 C operation, 1-line display
- 18.5 Initializing by instruction
19 BONDING PAD LOCATIONS
20 PACKAGE OUTLINE
- SOT425-1
21 SOLDERING
- 21.1 Introduction
- 21.2 Reflow soldering
- 21.3 Wave soldering
- 21.4 Repairing soldered joints
22 DEFINITIONS
23 LIFE SUPPORT APPLICATIONS
24 PURCHASE OF PHILIPS I 2 C COMPONENTS

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

CONTENTS

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

3.1

Packages

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

PIN FUNCTIONS

7.1

RS: register select (parallel control)

7.2

R/W: read/write (parallel control)

7.3

E: data bus clock

7.4

DB0 to DB7: data bus

7.5

C1 to C60: column driver outputs

7.6

R1 to R32: row driver outputs

7.7

VLCD: LCD power supply

7.8

V0: VLCD control input

7.9

OSC: oscillator

7.10

SCL: serial clock line

7.11

SDA: serial data line

7.12

SA0: address pin

7.13

T1: test pad

FUNCTIONAL DESCRIPTION

8.1

LCD supply voltage generator, PCF2114x and
PCF2116x

8.2

LCD supply voltage generator, PCF2116K

8.3

Character generator ROM (CGROM)

8.4

LCD bias voltage generator

8.5

Oscillator

8.6

External clock

8.7

Power-on reset

8.8

Registers

8.9

Busy Flag

8.10

Address Counter (AC)

8.11

Display data RAM (DDRAM)

8.12

Character generator ROM (CGROM)

8.13

Character generator RAM (CGRAM)

8.14

Cursor control circuit

8.15

Timing generator

8.16

LCD row and column drivers

8.17

Programming MUX 1 : 16 displays with the
PCF2114x

8.18

Programming MUX 1 : 32 displays with the
PCF2114x

8.19

Reset function

INSTRUCTIONS

9.1

Clear display

9.2

Return home

9.3

Entry mode set

9.4

Display on/off control

9.5

Cursor/display shift

9.6

Function set

9.7

Set CGRAM address

9.8

Set DDRAM address

9.9

Read busy flag and address

9.10

Write data to CGRAM or DDRAM

9.11

Read data from CGRAM or DDRAM

INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)

INTERFACE TO MICROCONTROLLER
(I

C-BUS INTERFACE)

11.1

Characteristics of the I

C-bus

11.2

Bit transfer

11.3

START and STOP conditions

11.4

System configuration

11.5

Acknowledge

11.6

C-bus protocol

LIMITING VALUES

HANDLING

DC CHARACTERISTICS

DC CHARACTERISTICS (PCF2116K)

AC CHARACTERISTICS

TIMING CHARACTERISTICS

APPLICATION INFORMATION

18.1

8-bit operation, 1-line display using internal
reset

18.2

4-bit operation, 1-line display using internal
reset

18.3

8-bit operation, 2-line display

18.4

C operation, 1-line display

18.5

Initializing by instruction

BONDING PAD LOCATIONS

PACKAGE OUTLINE

SOLDERING

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

FEATURES

�

Single chip LCD controller/driver

�

1 or 2-line display of up to 24 characters per line, or
2 or 4 lines of up to 12 characters per line

�

7 character format plus cursor; 5

�

8 for kana

(Japanese syllabary) and user defined symbols

�

On-chip:

� generation of LCD supply voltage (external supply

also possible)

� generation of intermediate LCD bias voltages

� oscillator requires no external components (external

clock also possible)

�

Display data RAM: 80 characters

�

Character generator ROM: 240 characters

�

Character generator RAM: 16 characters

�

4 or 8-bit parallel bus or 2-wire I

C-bus interface

�

CMOS/TTL compatible

�

32 row, 60 column outputs

�

MUX rates 1 : 32 and 1 : 16

�

Uses common 11 code instruction set

�

Logic supply voltage range, V

: 2.5 to 6 V

�

Display supply voltage range, V

LCD

: 3.5 to 9 V

�

Low power consumption

�

C-bus address: 011101 SA0.

APPLICATIONS

�

Telecom equipment

�

Portable instruments

�

Point-of-sale terminals.

GENERAL DESCRIPTION

The PCF2116 family of LCD controller/drivers consists of
the PCF2116x, the PCF2114x and the PCF2116K.
The term `PCF2116' is used to refer to all devices for
common information. Specific information is given in
separate paragraphs.

The `x' in `PCF2116x' and `PCF2114x' represents a
specific letter code for a character set in the character
generator ROM (CGROM). The different character sets
currently available are specified by the letters A, C, and G
(see Figs 8 to 10). Other character sets are available on
request.

The PCF2116 is a low-power CMOS LCD controller and
driver, designed to drive a split screen dot matrix LCD
display of 1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with 5

�

8 dot format. All necessary

functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages,
resulting in a minimum of external components and lower
system power consumption. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. The PCF2116 interfaces to most
microcontrollers via a 4 or 8-bit bus or via the 2-wire
I

C-bus. To allow partial V

shutdown the ESD protection

system of the SCL and SDA pins does not use a diode
connected to V

The PCF2116K differs from the other members of the
family in that:

�

LCD

generation is different (see Section 8.1)

�

It is available with character set C only (see Fig.9).

ORDERING INFORMATION

Note

1. The letter `x' in the type number represents the letter of the required built-in character set: A, C or G.

TYPE

NUMBER

(1)

PACKAGE

NAME

DESCRIPTION

VERSION

PCF2116xU/10

chip on flexible film carrier

PCF2114xU/10

chip on flexible film carrier

PCF2116xU/12

chip with bumps on flexible film carrier

PCF2114xU/12

chip with bumps on flexible film carrier

PCF2116xHZ

LQFP128 plastic low profile quad flat package; 128 leads; body 14

�

1.4 mm

SOT425-1

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

PINNING

SYMBOL

LQFP128

FFC PAD

TYPE

DESCRIPTION

R31

LCD row driver output

n.c.

2 and 3

not connected

R32

LCD row driver output

C60 to C30

5 to 35

29 to 59

LCD column driver outputs 60 to 30

n.c.

36 and 37

not connected

C29 to C2

38 to 65

60 to 87

LCD column driver outputs 29 to 2

n.c.

66 and 67

not connected

LCD column driver output 1

R24 to R17

69 to 76

89 to 96

LCD row driver outputs

R8 to R1

77 to 84

97 to 104

LCD row driver outputs

n.c.

85 and 86

not connected

DB7

105

I/O

1 bit of 8-bit bidirectional data bus

SCL

106

C-bus serial clock input

DB6

107

I/O

1 bit of 8-bit bidirectional data bus

SDA

108

I/O

C-bus serial data input/output

DB5

109

I/O

1 bit of 8-bit bidirectional data bus

110

control input for V

LCD

LCD1

111

I/O

LCD supply voltage input/output 1

DB4

112

I/O

1 bit of 8-bit bidirectional data bus

LCD2

113

I/O

LCD supply voltage input/output 2

DB3

114

I/O

1 bit of 8-bit bidirectional data bus

LCD3

115

I/O

LCD supply voltage input/output 3

DB2

116

I/O

1 bit of 8-bit bidirectional data bus

n.c.

99 to 101

not connected

OSC

102

oscillator/external clock input

DB1

103

I/O

1 bit of 8-bit bidirectional data bus

DD2

104

supply voltage 2

DB0

105

I/O

1 bit of 8-bit bidirectional data bus

DD1

106

supply voltage 1

SA0

107

C-bus address pin

108

data bus clock input (parallel control)

SS1

109

ground (logic) 1

R/W

110

read/write input (parallel control)

111

test pad (connect to V

)

SS2

112

ground (logic) 2

113

n.c.

114

not connected

R9 to R16

115 to 122

13 to 20

LCD row driver outputs

R25 to R30

123 to 128

21 to 26

LCD row driver outputs

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Fig.2 Pin configuration (LQFP128).

handbook, full pagewidth

MBD451 - 1

102

101

100

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

PCF2116

R31

n.c.

R32

C60

C59

C58

C57

C56

C55

C54

C53

C52

C51

C50

C49

C48

C47

C46

C45

C44

C43

C42

C41

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

n.c.

C29

OSC

n.c.

DB2

DB3

DB4

DB5

SDA

DB6

SCL

DB7

n.c.

R17

R18

R19

R20

R21

R22

R23

R24

n.c.

LCD3

VLCD2

VLCD1

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

R30

R29

R28

R27

R26

R25

R16

R15

R14

R13

R12

R11

R10

n.c.

R/W

SA0

DB0

DB1

DD2

DD1

SS1

SS2

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

PIN FUNCTIONS

7.1

RS: register select (parallel control)

RS selects the register to be accessed for read and write
when the device is controlled by the parallel interface.
RS = logic 0 selects the instruction register for write and
the Busy Flag and Address Counter for read. RS = logic 1
selects the data register for both read and write. There is
an internal pull-up on pin RS.

7.2

R/W: read/write (parallel control)

R/W selects either the read (R/W = logic 1) or write
(R/W = logic 0) operation when control is by the parallel
interface. There is an internal pull-up on this pin.

7.3

E: data bus clock

The E pin is set HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied
to logic 0 (V

) when I

C-bus control is used.

7.4

DB0 to DB7: data bus

The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2116. DB7 may be used
as the Busy Flag, signalling that internal operations are not
yet completed. In 4-bit operations the 4 higher order lines
DB4 to DB7 are used; DB0 to DB3 must be left open
circuit. There is an internal pull-up on each of the data
lines. Note that these pins must be left open circuit when
I

C-bus control is used.

7.5

C1 to C60: column driver outputs

These pins output the data for pairs of columns.
This arrangement permits optimized chip-on-glass (COG)
layout for 4-line by 12 characters.

7.6

R1 to R32: row driver outputs

These pins output the row select waveforms to the left and
right halves of the display.

7.7

LCD

: LCD power supply

Negative power supply for the liquid crystal display.
This may be generated on-chip or supplied externally.

7.8

: V

LCD

control input

The input level at this pin determines the generated V

LCD

output voltage.

7.9

OSC: oscillator

When the on-chip oscillator is used this pin must be
connected to V

. An external clock signal, if used, is input

at this pin.

7.10

SCL: serial clock line

Input for the I

C-bus clock signal.

7.11

SDA: serial data line

Input/output for the I

C-bus data line.

7.12

SA0: address pin

The hardware sub-address line is used to program the
device sub-address for 2 different PCF2116s on the same
I

C-bus.

7.13

T1: test pad

Must be connected to V

. Not user accessible.

FUNCTIONAL DESCRIPTION (see Fig.1)

8.1

LCD supply voltage generator, PCF2114x and
PCF2116x

The on-chip voltage generator is controlled by bit G of the
`Function set' instruction and V

is a high-impedance input and draws no current from

the system power supply. Its range is between V

and

1 V. When V

is connected to V

the generator is

switched off and an external voltage must be supplied to
pin V

LCD

. This may be more negative than V

When G = logic 1 the generator produces a negative
voltage at pin V

LCD

, controlled by the input voltage at

pin V

. The LCD operating voltage is given by the

relationship:

= 1.8V

Where:

= V

LCD

= V

(0.8V

)

When G = logic 0, the generated output voltage V

LCD

equal to V

(between V

and V

). In this instance:

= V

When V

LCD

is generated on-chip the V

LCD

pin should be

decoupled to V

with a suitable capacitor. V

and V

must be selected to limit the maximum value of V

to 9 V.

Figure 3 shows the two generator control characteristics.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

8.2

LCD supply voltage generator, PCF2116K

In the PCF2116K version, V

is connected through an

on-chip resistor (R

) to V

LCD

. Resistor R

has a nominal

value of 1 M

and draws a typical current of 4

�

A from the

pin V

. A constant voltage (equal to 1.34V

) is always

present across R

The voltage range of the PCF2116K is between V

and

0.5 V (see Fig.4). When V

is connected to V

the

generator is switched off and an external voltage must be
supplied to pin V

LCD

. This may be more negative than V

When G = logic 1 the generator produces a negative
voltage at pin V

LCD

, controlled by the input voltage at

pin V

. The LCD operating voltage is given by the

relationship:

= 2.34V

Where:

= V

LCD

= V

(1.34V

)

When G = logic 0, the generated output voltage V

LCD

equal to V

(between V

and V

). In this instance:

= V

8.3

Character generator ROM (CGROM)

The standard character sets A, C and G are available for
the PCF2114x and PCF2116x. Standard character set C is
available for the PCF2116K.

8.4

LCD bias voltage generator

The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.

The optimum value of V

depends on the multiplex rate,

the LCD threshold voltage (V

) and the number of bias

levels and is given by the relationships in Table 1.Using a
5-level bias scheme for 1 : 16 MUX rate allows V

< 5 V

for most LCD liquids. The effect on the display contrast is
negligible.

8.5

Oscillator

The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to V

8.6

External clock

If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
f

frame

2304

osc

. A clock signal must always be present,

otherwise the LCD may be frozen in a DC state.

8.7

Power-on reset

The power-on reset block initializes the chip after
power-on or power failure.

8.8

Registers

The PCF2116 has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed.

The instruction register stores instruction codes such as
`Display clear' and `Cursor shift', and address information
for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be
written to, but not read, by the system controller.

The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM corresponding to the address in the
Address Counter is written to the data register prior to
being read by the `Read data' instruction.

8.9

Busy Flag

The Busy Flag indicates the free/busy status of the
PCF2116. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output to pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is logic 0 or waiting for the required number of
clock cycles.

Table 1

Optimum values for V

MUX RATE

NUMBER OF BIAS

LEVELS

DISCRIMINATION

off

1 : 16

3.67

1.277

1 : 32

5.19

1.196

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

8.10

Address Counter (AC)

The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions `Set CGRAM address' and
`Set DDRAM address'. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1.The Address Counter contents are
output to the bus (DB0 to DB6) when RS = logic 0 and
R/W = logic 1.

8.11

Display data RAM (DDRAM)

The display data RAM stores up to 80 characters of
display data represented by 8-bit character codes.
RAM locations not used for storing display data can be
used as general purpose RAM. The basic
DDRAM-to-display mapping scheme is shown in Fig.5.
With no display shift the characters represented by the
codes in the first 12 or 24 RAM locations starting at
address 00 in line 1 are displayed. Subsequent lines
display data starting at addresses 20, 40, or 60 Hex.
Figs 6 and 7 show the DDRAM-to-display mapping
principle when the display is shifted.

The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively.
For 2 and 4-line displays the end address of one line and
the start address of the next line are not consecutive.
When the display is shifted each line wraps around
independently of the others (Figs 6 and 7).

When data is written into the DDRAM wrap-around occurs
from 4F to 00 in 1-line mode and from 27 to 40 and
67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line mode.

8.12

Character generator ROM (CGROM)

The character generator ROM generates 240 character
patterns in 5

�

8 dot format from 8-bit character codes.

Figures 8 to 10 show the character sets currently
available.

8.13

Character generator RAM (CGRAM)

Up to 16 user-defined characters may be stored in the
character generator RAM. The CGROM and CGRAM use
a common address space, of which the first column is
reserved for the CGRAM (see Fig.8). Figure 11 shows the
addressing principle for the CGRAM.

8.14

Cursor control circuit

The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.12) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.

8.15

Timing generator

The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.

8.16

LCD row and column drivers

The PCF2116 contains 32 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 13 and 14 show typical waveforms.

In 1-line mode (1 : 16) the row outputs are driven in pairs:
R1/R17, R2/R18 for example. This allows the output pairs
to be connected in parallel, providing greater drive
capability.

Unused outputs should be left unconnected.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Fig.6 DDRAM-to-display mappi7ng; right shift.

27 00 01 02 03

67 40 41 42 43

14 15 16

54 55 56

DDRAM
Address
(hex)

line 1

line 2

2-line display

22 23 24

4F 00 01 02 03

14 15 16

Display
Position
(decimal)

DDRAM
Address
(hex)

1-line display

MLA802

01 02 03 04 05 06 07 08 09 0A

20 21 22 23 24 25 26 27 28 29 2A

40 41 42 43 44 45 46 47 48 49 4A

60 61 62 63 64 65 66 67 68 69 6A

8 9 10 11 12

DDRAM

Address
(hex)

line 1

line 2

line 3

line 4

4-line display

MLA803

Fig.7 DDRAM-to-display mapping; left shift.

22 23 24

01 02 03 04

16 17 18

41 42 43 44 45

56 57 58

01 02 03 04

16 17 18

Display
Position
(decimal)

DDRAM
Address
(hex)

line 1

line 2

1-line display

2-line display

MLA815

01 02 03 04 05 06 07 08 09 0A 0B 0C

21 22 23 24 25 26 27 28 29 2A 2B 2C

41 42 43 44 45 46 47 48 49 4A 4B 4C

61 62 63 64 65 66 67 68 69 6A 6B 6C

9 10 11 12

DDRAM
Address
(hex)

line 1

line 2

line 3

line 4

4-line display

MLA816

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Fig.11 Relationship between CGRAM addresses and data and display patterns.

handbook, full pagewidth

MGA800 - 1

higher

order

bits

lower
order

bits

lower
order

bits

higher

order

bits

lower
order

bits

higher

order

bits

1
1
1
1

character codes

(DDRAM data)

CGRAM

address

character patterns

(CGRAM data)

character

pattern

example 1

cursor

position

character

pattern

example 2

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th line will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.11 (bit 4 being at the left end).

As shown in Figs 8 and 11, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1
corresponds to selection for display.

Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction
or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

8.17

Programming MUX 1 : 16 displays with the
PCF2114x

The PCF2114x can be used in:

�

1-line mode to drive a 2-line display

�

12 characters with MUX rate 1 : 16, resulting in

better contrast. The internal data flow of the chip is
optimized for this purpose.

With the `Function set' instruction M and N are set to 0, 0.
Figures 15 to 17 show DDRAM addresses of the display
characters. The second row of each table corresponds to
either the right half of a 1-line display or to the second line
of a 2-line display. Wrap around of data during display shift
or when writing data is non-standard.

Fig.15 DDRAM-to-display mapping; no shift (PCF2114x).

handbook, full pagewidth

MLB899

display position

DDRAM address

display position

DDRAM address

Fig.16 DDRAM-to-display mapping; right shift (PCF2114x).

handbook, full pagewidth

MLB900

display position

DDRAM address

display position

DDRAM address

Fig.17 DDRAM-to-display mapping; left shift (PCF2114x).

handbook, full pagewidth

MLB901

display position

DDRAM address

display position

DDRAM address

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

8.18

Programming MUX 1 : 32 displays with the
PCF2114x

To drive a 2-line by 24 characters MUX 1 : 32 display, use
instruction `Function set' M, N to 0, 1. Note that the right
half of the display needs mirrored column connection
compared to a display driven by a PCF2116x.

To drive a 4-line by 12 characters MUX 1 : 32 display the
PCF2116x operating instructions apply. There is no
functional difference between the PCF2114x and the
PCF2116x in this mode. For such an application
set M, N to 1, 1 with the `Function set' instruction.

8.19

Reset function

The PCF2116 automatically initializes (resets) when
power is turned on. After reset the chip has the following
state.

Table 2

State after reset

STEP

DESCRIPTION

display clear

function set

DL = 1

8-bit interface

M, N = 0

1-line display

G = 0

voltage
generator;
V

LCD

= V

display on/off
control

D = 0

display off

C = 0

cursor off

B = 0

blink off

entry mode set

I/D = 1

+1 (increment)

S = 0

no shift

Default address pointer to DDRAM. The Busy
Flag (BF) indicates the busy state (BF = logic 1)
until initialization ends. The busy state lasts
2 ms. The chip may also be initialized by
software. See Figs 28 and 29.

C-bus interface reset

INSTRUCTIONS

Only two PCF2116 registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow
interface to various types of microcontrollers which
operate at different speeds or to allow interface to
peripheral control ICs.
The PCF2116 operation is controlled by the instructions
shown in Table 3 together with their execution time.
Details are explained in subsequent sections.

Instructions are of 4 categories, those that:

1. Designate PCF2116 functions such as display format,

data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1 (or
decrementing by 1) of internal RAM addresses after each
data write lessens the microcontroller program load. The
display shift in particular can be performed concurrently
with display data write, enabling the designer to develop
systems in minimum time with maximum programming
efficiency.

During internal operation, no instruction other than
`Read busy flag and address' will be executed.

Because the Busy Flag is set to logic 1 while an instruction
is being executed, check to make sure it is on logic 0
before sending the next instruction or wait for the
maximum instruction execution time, as given in Table 3.
An instruction sent while the Busy Flag is HIGH will not be
executed.

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 3

Instructions (note 1)

Notes

1. In the I

C-bus mode the DL bit is don't care. 8-bit mode is assumed.

In the I

C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.

2. Example: f

osc

= 150 kHz,

= 6.67

�

s; 3 cycles = 20

�

s, 165 cycles = 1.1 ms.

INSTRUCTION

R/W

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DESCRIPTION

REQUIRED

CLOCK

CYCLES

(2)

NOP

No operation.

Clear display

Clears entire display and sets DDRAM
address 0 in Address Counter.

165

Return Home

Sets DDRAM address 0 in Address Counter.
Also returns shifted display to original position.
DDRAM contents remain unchanged.

Entry mode set

I/D

Sets cursor move direction and specifies shift
of display. These operations are performed
during data write and read.

Display control

Sets entire display on/off (D), cursor on/off (C)
and blink of cursor position character (B).

Cursor/display
shift

S/C

R/L

Moves cursor and shifts display without
changing DDRAM contents.

Function set

Sets interface data length (DL), number of
display lines (N, M) and voltage generator
control (G).

Set CGRAM
address

Sets CGRAM address.

Set DDRAM
address

Sets DDRAM address.

Read busy flag
and address

Reads Busy Flag (BF) indicating internal
operation is being performed and reads
Address Counter contents.

Read data

read data

Reads data from CGRAM or DDRAM.

Write data

write data

Writes data to CGRAM or DDRAM.

osc

---------

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Table 4

Command bit identities

BIT

I/D

decrement

increment

display freeze

display shift

display off

display on

cursor off

cursor on

character at cursor position does not blink

character at cursor position blinks

S/C

cursor move

display shift

R/L

left shift

right shift

4 bits

8 bits

voltage generator: V

LCD

= V

voltage generator; V

LCD

= V

0.8V

N, (M = 0)

PCF2116x

1 line

�

24 characters; MUX 1 : 16

2 lines

�

24 characters; MUX 1 : 32

PCF2114x

2 line

�

12 characters; MUX 1 : 16

2 lines

�

24 characters; MUX 1 : 32

N, (M = 1)

reserved

4 lines

�

12 characters; MUX 1 : 32

end of internal operation

internal operation in progress

last control byte, only data bytes to follow

next two bytes are a data byte and another
control byte

Fig.18 4-bit transfer example.

MGA804

DB7

R/W

DB6

DB5

DB4

instruction

write

busy flag and

address counter read

data register

read

IR7

IR3

AC3

DR7

DR3

IR6

IR2

AC6

AC2

DR6

DR2

IR5

IR1

AC5

AC1

DR5

DR1

IR4

IR0

AC4

AC0

DR4

DR0

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

9.1

Clear display

`Clear display' writes space code 20 (hexadecimal) into all
DDRAM addresses (The character pattern for character
code 20 must be blank pattern). Sets the DDRAM Address
Counter to logic 0. Returns display to its original position if
it was shifted. Thus, the display disappears and the cursor
or blink position goes to the left edge of the display
(the first line if 2 or 4 lines are displayed). Sets entry mode
I/D = logic 1 (increment mode). S of entry mode does not
change.

The instruction `Clear display' requires extra execution
time. This may be allowed for by checking the busy-flag
(BF) or by waiting until 2 ms has elapsed. The latter must
be applied where no read-back options are foreseen, as in
some chip-on-glass (COG) applications.

9.2

Return home

`Return home' sets the DDRAM Address Counter to
logic 0. Returns display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the display (the first line if 2
or 4 lines are displayed). I/D and S of entry mode do not
change.

9.3

Entry mode set

9.3.1

I/D

When I/D = logic 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor and blink are inhibited
when the CGRAM is accessed.

9.3.2

When S = logic 1, the entire display shifts either to the right
(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM
write. Thus it looks as if the cursor stands still and the
display moves. The display does not shift when reading
from the DDRAM, or when writing into or reading out of the
CGRAM. When S = logic 0 the display does not shift.

9.4

Display on/off control

9.4.1

The display is on when D = logic 1 and off when
D = logic 0. Display data in the DDRAM are not affected
and can be displayed immediately by setting D to logic 1.

9.4.2

The cursor is displayed when C = logic 1 and inhibited
when C = logic 0. Even if the cursor disappears, the
display functions I/D, etc. remain in operation during
display data write. The cursor is displayed using 5 dots in
the 8

line (see Fig.12).

9.4.3

The character indicated by the cursor blinks when
B = logic 1. The blink is displayed by switching between
display characters and all dots on with a period of
1 second when f

osc

= 150 kHz (see Fig.12). At other clock

frequencies the blink period is equal to 150 kHz/f

osc

The cursor and the blink can be set to display
simultaneously.

9.5

Cursor/display shift

`Cursor/display shift' moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2 or 4-line displays, the
cursor moves to the next line when it passes the last
position (40 or 20 decimal) of the line. When the displayed
data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the cursor shift.

9.6

Function set

9.6.1

DL (

PARALLEL MODE ONLY

)

Defines interface data width when the parallel data
interface is used.

Data is sent or received in bytes (bits DB7 to DB0) when
DL = logic 1, or in two 4-bit nibbles (DB7 to DB4) when
DL = logic 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus

(1)

When using the I

C-bus interface the DL should not

previously have been set to 0 using the parallel interface.

9.6.2

N, M

Sets number of display lines.

(1) In a 4-bit application DB3 to DB0 are left open (internal

pull-ups). Hence in the first `Function set' instruction after
power-on, G and H are set to 1. A second `Function set' must
then be sent (2 nibbles) to set G and H to their required
values.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

9.6.3

Controls the V

LCD

voltage generator characteristic.

9.7

Set CGRAM address

`Set CGRAM address' sets bit 0 to 5 of the CGRAM
address (A

in Table 3) into the Address Counter

(binary A[5] to A[0]). Data can then be written to or read
from the CGRAM.

Only bits 0 to 5 of the CGRAM address are set by the
`Set CGRAM address' instruction. Bit 6 can be set using
the `Set DDRAM address' instruction or by using the
auto-increment feature during CGRAM write. All bits 0 to 6
can be read using the `Read busy flag and address'
instruction.

9.8

Set DDRAM address

`Set DDRAM address' sets the DDRAM address (A

Table 3) into the Address Counter (binary A[6] to A[0]).
Data can then be written to or read from the DDRAM.

Hexadecimal address ranges.

9.9

Read busy flag and address

`Read busy flag and address' reads the Busy Flag (BF).
BF = logic 1 indicates that an internal operation is in
progress. The next instruction will not be executed until
BF = logic 0, so BF should be checked before sending
another instruction.

At the same time, the value of the Address Counter (A

Table 3) expressed in binary A[6] to A[0] is read out. The
Address Counter is used by both CGRAM and DDRAM,
and its value is determined by the previous instruction.

9.10

Write data to CGRAM or DDRAM

Writes binary 8-bit data D[7] to D[0] to the CGRAM or the
DDRAM.

Whether the CGRAM or DDRAM is to be written into is
determined by the previous specification of CGRAM or
DDRAM address setting.

ADDRESS

FUNCTION

00 to 4F

1-line by 24; 2114x/2116x

00 to 0B and 0C to 4F

2-line by 12; 2114x

00 to 27 and 40 to 67

2-line by 24; 2114x/2116x

00 to 13, 20 to 33, 40 to 53
and 60 to 73

4-line by 12; 2114x/2116x

After writing, the address automatically increments or
decrements by 1, in accordance with the entry mode.
Only bits D[4] to D[0] of CGRAM data are valid, bits
D[7] to D[5] are `don't care'.

9.11

Read data from CGRAM or DDRAM

Reads binary 8-bit data D[7] to D[0] from the CGRAM or
DDRAM.

The most recent `Set address' instruction determines
whether the CGRAM or DDRAM is to be read.

The `Read data' instruction gates the content of the data
register (DR) to the bus while E = HIGH. After E goes LOW
again, internal operation increments (or decrements) the
AC and stores RAM data corresponding to the new AC into
the DR.

Remark: the only three instructions that update the data
register (DR) are:

�

`Set CGRAM address'

�

`Set DDRAM address'

�

`Read data' from CGRAM or DDRAM.

Other instructions (e.g. `Write data', `Cursor/Display shift',
`Clear display', `Return home') will not modify the data
register content.

10 INTERFACE TO MICROCONTROLLER

(PARALLEL INTERFACE)

The PCF2116 can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB0 to DB7. Three further control lines E, RS,
and R/W are required.

In 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB4 to DB7
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB0 to DB3 in 8-bit mode) in the second.
Data transfer is complete after two 4-bit data transfers.
It should be noted that two cycles are also required for the
Busy Flag check. 4-bit operation is selected by instruction.
See Figs 18, 19 and 20 for examples of bus protocol.

In 4-bit mode pins DB3 to DB0 must be left open-circuit.
They are pulled up to V

internally.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

11 INTERFACE TO MICROCONTROLLER

C-BUS INTERFACE)

11.1

Characteristics of the I

C-bus

The I

C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.

11.2

Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.

11.3

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).

11.4

System configuration

A device generating a message is a `transmitter', a device
receiving a message is the `receiver'. The device that
controls the message is the `master' and the devices which
are controlled by the master are the `slaves'.

11.5

Acknowledge

The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.

11.6

C-bus protocol

Before any data is transmitted on the I

C-bus, the device

which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I

C-bus configuration for the different

PCF2116 READ and WRITE cycles is shown in
Figs 25 to 27.

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

14 DC CHARACTERISTICS

= 2.5 to 6 V; V

= 0 V; V

LCD

= V

3.5 to V

9 V; T

amb

�

C to +85

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage

2.5

6.0

LCD

LCD supply voltage

3.5

supply current external V

LCD

note 1

DD1

supply current 1

200

500

�

DD2

supply current 2

= 5 V; V

= 9 V;

osc

= 150 kHz;

amb

= 25

�

200

300

�

DD3

supply current 3

= 3 V; V

= 5 V;

osc

= 150 kHz;

amb

= 25

�

150

200

�

supply current internal V

LCD

notes 1, 2 and 8

DD4

supply current 4

700

1100

�

DD5

supply current 5

= 5 V; V

= 9 V;

osc

= 150 kHz;

amb

= 25

�

600

900

�

DD6

supply current 6

= 3 V; V

= 5 V;

osc

= 150 kHz;

amb

= 25

�

500

800

�

LCD

input current

notes 1 and 7

100

�

POR

power-on reset voltage level

note 3

1.3

1.8

Logic

IL1

LOW level input voltage E, RS,
R/W, DB0 to DB7 and SA0

0.3V

IH1

HIGH level input voltage E, RS,
R/W, DB0 to DB7 and SA0

0.7V

IL(osc)

LOW level input voltage OSC

1.5

IH(osc)

HIGH level input voltage OSC

0.1

IL(V0)

LOW level input voltage V

0.5

IH(V0)

HIGH level input voltage V

0.05

pull-up current at DB0 to DB7

= V

0.04

0.15

1.00

�

OL(DB)

LOW level output current
DB0 to DB7

= 0.4 V; V

= 5 V 1.6

OH(DB)

HIGH level output current
DB0 to DB7

= 4 V; V

= 5 V

1.0

leakage current OSC, V

, E, RS,

R/W, DB0 to DB7 and SA0

= V

or V

�

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Notes

1. LCD outputs are open-circuit; inputs at V

or V

; V

= V

; bus inactive; internal or external clock with duty cycle

50% (I

DD1

only).

2. LCD outputs are open-circuit; LCD supply voltage generator is on; load current at V

LCD

= 20

�

3. Resets all logic when V

< V

POR

4. When the voltages are above or below the supply voltages V

or V

, an input current may flow; this current must

not exceed

�

0.5 mA.

5. Tested on sample basis.

6. Resistance of output terminals (R1 to R32 and C1 to C60) with load current = 150

�

A; V

= V

LCD

= 9 V;

outputs measured one at a time; (external V

LCD

7. LCD outputs open-circuit; external V

LCD

8. Maximum value occurs at 85

�

15 DC CHARACTERISTICS (PCF2116K)

= 2.5 to 6 V; V

= 0 V; V

LCD

= V

3.5 to V

9 V; T

amb

�

C to +85

�

C; unless otherwise specified.

Note

1. R

has a temperature coefficient of resistance of +0.6%/K.

C-bus

SDA, SCL

IL2

LOW level input voltage

note 4

0.3V

IH2

HIGH level input voltage

note 4

0.7V

leakage current

= V

or V

�

input capacitance

note 5

OL(SDA)

LOW level output current (SDA)

= 0.4 V; V

= 5 V 3

LCD outputs

ROW

row output resistance R1 to R32

note 6

1.5

COL

column output resistance C1 to C60 note 6

tol1

bias voltage tolerance R1 to R32
and C1 to C60

note 7

�

130

tol2

LCD supply voltage (V

LCD

)

tolerance

note 2

�

300

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

2.5

6.0

LCD

LCD supply voltage

3.5

voltage generator control input
voltage

0.5

voltage generator control input
resistance

amb

= 25

�

C; note 1

700

1000

1300

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

16 AC CHARACTERISTICS

= 2.5 to 6.0 V; V

= 0 V; V

LCD

= V

3.5 V to V

9 V; T

amb

�

C to +85

�

C; unless otherwise specified.

Notes

1. V

= 5 V.

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to

and V

with an input voltage swing of V

to V

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

LCD frame frequency (internal clock); note 1

100

osc

external clock frequency

150

225

kHz

Bus timing characteristics: Parallel Interface; notes 1 and 2

RITE OPERATION

(

WRITING DATA FROM MICROCONTROLLER TO

PCF2116)

enable cycle time

500

enable pulse width

220

ASU

address set-up time

address hold time

DSW

data set-up time

data hold time

EAD OPERATION

(

READING DATA FROM

PCF2116

TO MICROCONTROLLER

)

enable cycle time

500

enable pulse width

220

ASU

address set-up time

address hold time

DHD

data delay time

150

data hold time

100

Timing characteristics: I

C-bus interface; note 2

SCL

SCL clock frequency

100

kHz

tolerable spike width on bus

100

BUF

bus free time

4.7

�

SU;STA

set-up time for a repeated START condition

4.7

�

HD;STA

START condition hold time

�

LOW

SCL LOW time

4.7

�

HIGH

SCL HIGH time

�

SCL and SDA rise time

�

SCL and SDA fall time

0.3

�

SU;DAT

data set-up time

250

HD;DAT

data hold time

SU;STO

set-up time for STOP condition

�

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

18.1

8-bit operation, 1-line display using internal
reset

Table 6 shows an example of a 1-line display in 8-bit
operation. The PCF2116 functions must be set by the
`Function set' instruction prior to display. Since the display
data RAM can store data for 80 characters, the RAM can
be used for advertising displays when combined with
display shift operation. Since the display shift operation
changes display position only and DDRAM contents
remain unchanged, display data entered first can be
displayed when the Return Home operation is performed.

18.2

4-bit operation, 1-line display using internal
reset

The program must set functions prior to 4-bit operation.
Table 5 shows an example. When power is turned on, 8-bit
operation is automatically selected and the PCF2116
attempts to perform the first write as an 8-bit operation.
Since nothing is connected to DB0 to DB3, a rewrite is
then required. However, since one operation is completed
in two accesses of 4-bit operation, a rewrite is required to
set the functions (see Table 5 step 3).

Thus, DB4 to DB7 of the function set are written twice.

18.3

8-bit operation, 2-line display

For a 2-line display, the cursor automatically moves from
the first to the second line after the 40

digit of the first line

has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the eighth
character is completed (see Table 7). Note that both lines
of the display are always shifted together; data does not
shift from one line to the other.

18.4

C operation, 1-line display

A control byte is required with most instructions
(see Table 8).

18.5

Initializing by instruction

If the power supply conditions for correctly operating the
internal reset circuit are not met, the PCF2116 must be
initialized by instruction. Tables 9 and 10 show how this
may be performed for 8-bit and 4-bit operation.

Table 5

4-bit operation, 1-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2116 is initialized by
the internal reset circuit)

Initialized. No display appears.

function set

R/W

DB7

DB6

DB5

DB4

Sets to 4-bit operation. In this instance operation
is handled as 8-bits by initialization and only this
instruction completes with one write.

function set

Sets to 4-bit operation, selects 1-line display and
V

LCD

= V

. 4-bit operation starts from this point

and resetting is needed.

display on/off control

Turns on display and cursor. Entire display is
blank after initialization.

entry mode set

Sets mode to increment the address by 1 and to
shift the cursor to the right at the time of write to
the DD/CGRAM. Display is not shifted.

write data to CGRAM/DDRAM

Writes `P'. The DDRAM has already been
selected by initialization at power-on. The cursor
is incremented by 1 and shifted to the right.

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 6

8-bit operation, 1-line display example; using internal reset (character set `A')

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2116 is initialized by the internal reset
function)

Initialized. No display appears.

function set

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Sets to 8-bit operation, selects 1-line display and
V

LCD

= V

display mode on/off control

Turns on display and cursor. Entire display is blank after
initialization.

entry mode set

Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM. Display is not shifted.

write data to CGRAM/DDRAM

Writes `P'. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.

write data to CGRAM/DDRAM

PH_

Writes `H'.

|
|
|

write data to CGRAM/DDRAM

PHILIPS_

Writes `S'.

entry mode set

PHILIPS_

Sets mode for display shift at the time of write.

write data to CGRAM/DDRAM

PHILIPS_

Writes space.

write data to CGRAM/DDRAM

PHILIPS M_

Writes `M'.

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 7

8-bit operation, 2-line display example; using internal reset

STEP

INSTRUCTION

DISPLAY

OPERATION

power supply on (PCF2116 is initialized by the internal reset
function)

Initialized. No display appears.

function set

Sets to 8-bit operation, selects 2-line display and voltage
generator off.

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

display on/off control

Turns on display and cursor. Entire display is blank after
initialization.

entry mode set

Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM.
Display is not shifted.

Write data to CGRAM/DDRAM

Writes `P'. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.

|
|
|

write data to CGRAM/DDRAM

PHILIPS_

Writes `S'.

set DDRAM address

PHILIPS

Sets DDRAM address to position the cursor at the head of
the 2nd line.

write data to CGRAM/ DDRAM

PHILIPS

Writes `M'.

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 8

Example of I

C operation; 1-line display (using internal reset, assuming SA0 = V

; note 1)

STEP

C BYTE

DISPLAY

OPERATION

C START

Initialized. No display appears.

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

During the acknowledge cycle SDA will be pulled-down by the
PCF2116.

send a control byte for function set

R/W

Ack

Control byte sets RS and R/W for following data bytes.

function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Selects 1-line display and V

LCD

= V

; SCL pulse during

acknowledge cycle starts execution of instruction.

display on/off control

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Turns on display and cursor. Entire display shows character
Hex 20 (blank in ASCII-like character sets).

entry mode set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM.
Display is not shifted.

C START

For writing data to DDRAM, RS must be set to 1. Therefore a
control byte is needed.

slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W

Ack

send a control byte for write data

R/W

Ack

write data to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Writes `P'. The DDRAM has been selected at power-up.
The cursor is incremented by 1 and shifted to the right.

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

write data to DDRAM

PH_

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Writes `H'.

12 to 15

|
|
|
|

write data to DDRAM

PHILIPS_

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Writes `S'.

(optional I

C stop) I

C start + slave address for write

(as step 8)

PHILIPS_

control byte

PHILIPS_

R/W

Ack

Return Home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

Sets DDRAM address 0 in Address Counter. (also returns
shifted display to original position. DDRAM contents
unchanged). This instruction does not update the Data Register

PHILIPS

control byte for read

R/W

Ack

DDRAM content will be read from following instructions.
The R/W has to be set to 1 while still in I

C-write mode.

PHILIPS

C START

PHILIPS

slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W

Ack

During the acknowledge cycle the content of the DR is loaded
into the internal I

C interface to be shifted out. In the previous

instruction neither a `Set address' nor a `Read data' has been
performed. Therefore the content of the DR was unknown.

PHILIPS

read data: 8

�

SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Ack

�

SCL; content loaded into interface during previous

acknowledge cycle is shifted out over SDA. MSB is DB7. During
master acknowledge content of DDRAM address 01 is loaded
into the I

C interface.

PHILIPS

STEP

C BYTE

DISPLAY

OPERATION

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 9

Initialization by instruction, 8-bit interface (note 1)

Note

1. X = don't care.

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after V

rises above V

POR

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 2 ms

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait more than 40

�

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

|
|

BF can be checked after the following instructions. When BF is not checked,
the waiting time between instructions is the specified instruction time (see
Table 3).

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Function set (interface is 8-bits long). Specify the number of display lines and
voltage generator characteristic.

Display off.

Clear display.

I/D

Entry mode set.

Initialization ends

1997

Apr

Philips Semiconductors

Product specification

LCD controller/drivers

PCF21

16 family

Table 10 Initialization by instruction, 4-bit interface. Not applicable for I

C-bus operation

STEP

DESCRIPTION

power-on or unknown state

wait 2 ms after V

rises above V

POR

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 2 ms

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

wait 40

�

R/W

DB7

DB6

DB5

DB4

BF cannot be checked before this instruction.

Function set (interface is 8-bits long).

BF can be checked after the following instructions. When BF is not checked, the waiting time
between instructions is the specified instruction time. (See Table 3).

R/W

DB7

DB6

DB5

DB4

Function set (set interface to 4-bits long).

Interface is 8-bits long.

Function set (interface is 4-bits long).

Specify number of display lines and voltage generator characteristic.

Display off.

Clear display.

Entry mode set.

I/D

Initialization ends

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

Table 11 Bonding pad locations (dimensions in

�

All x/y coordinates are referenced to centre of chip,
see Fig.40.

SYMBOL

PAD

OSC

2445

3300

DB1

2211

3300

DD2

2034

3300

DB0

1806

3300

DD1

1627

3300

SA0

1437

3300

1245

3300

SS1

1056

3300

R/W

867

3300

672

3300

SS2

486

3300

297

3300

R10

247

3300

R11

417

3300

R12

587

3300

R13

757

3300

R14

927

3300

R15

1097

3300

R16

1267

3300

R25

1436

3300

R26

1606

3300

R27

1776

3300

R28

1946

3300

R29

2116

3300

R30

2286

3300

R31

2456

3300

R32

2626

3013

C60

2626

2760

C59

2626

2590

C58

2626

2420

C57

2626

2250

C56

2626

2080

C55

2626

1910

C54

2626

1740

C53

2626

1570

C52

2626

1400

C51

2626

1230

C50

2626

1060

C49

2626

890

C48

2626

720

C47

2626

550

C46

2626

380

C45

2626

582

C44

2626

752

C43

2626

922

C42

2626

1092

C41

2626

1262

C40

2626

1432

C39

2626

1602

C38

2626

1772

C37

2626

1942

C36

2626

2112

C35

2626

2282

C34

2626

2452

C33

2626

2622

C32

2626

2792

C31

2626

2962

C30

2626

3132

C29

2339

3302

C28

2169

3302

C27

1999

3302

C26

1829

3302

C25

1659

3302

C24

1489

3302

C23

1319

3302

C22

1149

3302

C21

979

3302

C20

809

3302

C19

639

3302

C18

469

3302

C17

299

3302

C16

129

3302

C15

245

3302

C14

415

3302

C13

585

3302

SYMBOL

PAD

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

21 SOLDERING

21.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

21.2

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

�

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

�

21.3

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

�

The footprint must be at an angle of 45

�

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

21.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

1997 Apr 07

Philips Semiconductors

Product specification

LCD controller/drivers

PCF2116 family

22 DEFINITIONS

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

24 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1997

SCA54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands

417067/1200/04/pp64

Date of release: 1997 Apr 07

Document order number:

9397 750 01754

Электронный компонент: PCF2116CU

Document Outline