1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

CONTENTS

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

6.1

Power-on reset

6.2

LCD bias generator

6.3

LCD voltage selector

6.4

LCD drive mode waveforms

6.5

Oscillator

6.6

Internal clock

6.7

External clock

6.8

Timing

6.9

Display latch

6.10

Shift register

6.11

Segment outputs

6.12

Backplane outputs

6.13

Display RAM

6.14

Data pointer

6.15

Subaddress counter

6.16

Output bank selector

6.17

Input bank selector

6.18

Blinker

C-BUS DESCRIPTION

7.1

Bit transfer

7.2

Start and stop conditions

7.3

System configuration

7.4

Acknowledge

7.5

PCF8566 I

C-bus controller

7.6

Input filters

7.7

C-bus protocol

7.8

Command decoder

7.9

Display controller

7.10

Cascaded operation

LIMITING VALUES

HANDLING

DC CHARACTERISTICS

AC CHARACTERISTICS

APPLICATION INFORMATION

CHIP DIMENSIONS AND BONDING PAD
LOCATIONS

PACKAGE OUTLINES

SOLDERING

15.1

Introduction

15.2

DIP

15.2.1

Soldering by dipping or by wave

15.2.2

Repairing soldered joints

15.3

SO and VSO

15.3.1

Reflow soldering

15.3.2

Wave soldering

15.3.3

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

FEATURES

�

Single-chip LCD controller/driver

�

Selectable backplane drive configuration: static
or 2, 3 or 4 backplane multiplexing

�

Selectable display bias configuration: static,

�

Internal LCD bias generation with voltage-follower
buffers

�

24 segment drives: up to twelve 8-segment numeric
characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements

�

4-bit RAM for display data storage

�

Auto-incremented display data loading across device
subaddress boundaries

�

Display memory bank switching in static and duplex
drive modes

�

Versatile blinking modes

�

LCD and logic supplies may be separated

�

2.5 to 6 V power supply range

�

Low power consumption

�

Power saving mode for extremely low power
consumption in battery-operated and telephone
applications

�

C-bus interface

�

TTL/CMOS compatible

�

Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers

�

May be cascaded for large LCD applications
(up to 1536 segments possible)

�

Cascadable with the 40 segment LCD driver PCF8576C

�

Optimized pinning for single plane wiring in both single
and multiple PCF8566 applications

�

Space-saving 40 lead plastic very small outline package
(VSO40; SOT158-1)

�

No external components required (even in multiple
device applications)

�

Manufactured in silicon gate CMOS process.

GENERAL DESCRIPTION

The PCF8566 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) having low
multiplex rates. It generates the drive signals for any static
or multiplexed LCD containing up to four backplanes and
up to 24 segments and can easily be cascaded for larger
LCD applications. The PCF8566 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I

C-bus. Communication overheads

are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

PCF8566P

DIP40

plastic dual in-line package; 40 leads (600 mil)

SOT129-1

PCF8566T

VSO40

plastic very small outline package; 40 leads

SOT158-1

1998

May

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex

rates

PCF8566

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BLOCK DIAGRAM

ndbook, full pagewidth

MGG383

LCD

VOLTAGE

SELECTOR

TIMING

BLINKER

OSCILLATOR

INPUT

FILTERS

I C-BUS

CONTROLLER

POWER-

RESET

CLK

SYNC

OSC

SCL

SDA

SA0

DISPLAY

CONTROLLER

COMMAND

DECODER

BACKPLANE

OUTPUTS

BP0

BP2

BP1

BP3

INPUT

BANK

SELECTOR

DISPLAY

RAM

�

4 BITS

OUTPUT

BANK

SELECTOR

DATA

POINTER

SUB-

ADDRESS

COUNTER

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

17 to 40

S0 to S23

PCF8566

LCD BIAS

GENERATOR

VSS

VLCD

VDD

Fig.1 Block diagram.

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

FUNCTIONAL DESCRIPTION

The PCF8566 is a versatile peripheral device designed to
interface any microprocessor to a wide variety of LCDs.
It can directly drive any static or multiplexed LCD
containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.

All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
two-line I

C-bus communication channel with the

PCF8566. The internal oscillator is selected by tying OSC
(pin 6) to V

. The appropriate biasing voltages for the

multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (V

, V

and V

LCD

) and

to the LCD panel chosen for the application.

Table 1

Selection of display configurations

ACTIVE

BACKPLANE

OUTPUTS

NUMBER OF

SEGMENTS

7-SEGMENT NUMERIC

14-SEGMENT

ALPHANUMERIC

DOT MATRIX

12 digits + 12 indicator
symbols

6 characters + 12 indicator
symbols

96 dots (4

�

24)

9 digits + 9 indicator
symbols

4 characters + 16 indicator
symbols

72 dots (3

�

24)

6 digits + 6 indicator
symbols

3 characters + 6 indicator
symbols

48 dots (2

�

24)

3 digits + 3 indicator
symbols

1 character + 10 indicator
symbols

24 dots

Fig.3 Typical system configuration.

handbook, full pagewidth

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

OSC

17 to 40

13 to 16

24 segment drives

4 backplanes

LCD PANEL

(up to 96

elements)

PCF8566

SA0

VDD

VLCD

VSS

MGG385

trise

2 Cbus

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

6.1

Power-on reset

At power-on the PCF8566 resets to a defined starting
condition as follows:

1. All backplane outputs are set to V

2. All segment outputs are set to V

3. The drive mode `1 : 4 multiplex with

bias' is selected

4. Blinking is switched off

5. Input and output bank selectors are reset (as defined

in Table 5)

6. The I

C-bus interface is initialized

7. The data pointer and the subaddress counter are

cleared.

Data transfers on the I

C-bus should be avoided for 1 ms

following power-on to allow completion of the reset action.

6.2

LCD bias generator

The full-scale LCD voltage (V

) is obtained from

LCD

. The LCD voltage may be temperature

compensated externally through the V

LCD

supply to pin 12.

Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors connected
between V

and V

LCD

. The centre resistor can be

switched out of circuit to provide a

bias voltage level for

the 1 : 2 multiplex configuration.

6.3

LCD voltage selector

The LCD voltage selector coordinates the multiplexing of
the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of V

= V

LCD

and the

resulting discrimination ratios (D), are given in Table 2.

A practical value of V

is determined by equating V

off(rms)

with a defined LCD threshold voltage (V

), typically when

the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is V

3 V

. Multiplex drive

ratios of 1 : 3 and 1 : 4 with

bias are possible but the

discrimination and hence the contrast ratios are smaller

(

for 1 : 3 multiplex or

for

1 : 4 multiplex). The advantage of these modes is a
reduction of the LCD full scale voltage V

as follows:

1 : 3 multiplex (

bias):

1 : 4 multiplex (

bias):

These compare with V

= 3 V

off(rms)

when

bias is used.

1.732

21 3

1.528

op(mrs)

2.449V

off rms

(

)

off rms

(

)

2.309V

off rms

(

)

Table 2

Preferred LCD drive modes: summary of characteristics

LCD DRIVE MODE

LCD BIAS

CONFIGURATION

Static (1 BP)

static (2 levels)

1 : 2 MUX (2 BP)

(3 levels)

1 : 2 MUX (2 BP)

(4 levels)

= 0.333

1 : 3 MUX (3 BP)

(4 levels)

= 0.333

1 : 4 MUX (4 BP)

(4 levels)

= 0.333

off rms

(

)

-----------------------

on rms

(

)

-----------------------

on rms

(

)

off rms

(

)

-----------------------

2 4

0.354

10 4

0.791

2.236

5 3

0.745

2.236

33 9

0.638

33 3

1.915

3 3

0.577

1.732

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

6.5

Oscillator

The internal logic and the LCD drive signals of the
PCF8566 or PCF8576 are timed either by the built-in
oscillator or from an external clock.

The clock frequency (f

CLK

) determines the LCD frame

frequency and the maximum rate for data reception from
the I

C-bus. To allow I

C-bus transmissions at their

maximum data rate of 100 kHz, f

CLK

should be chosen to

be above 125 kHz.

A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.

6.6

Internal clock

When the internal oscillator is used, OSC (pin 6) should be
tied to V

. In this case, the output from CLK (pin 4)

provides the clock signal for cascaded PCF8566s and
PCF8576s in the system.

6.7

External clock

The condition for external clock is made by tying OSC
(pin 6) to V

; CLK (pin 4) then becomes the external

clock input.

6.8

Timing

The timing of the PCF8566 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the PCF8566s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
multiple of the clock frequency (Table 3). The frame
frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when
external clock is used.

Table 3

LCD frame frequencies

The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.

PCF8566 MODE

frame

NOMINAL

frame

(Hz)

Normal mode

CLK

/2880

Power saving mode

CLK

/480

The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I

C-bus. When a

device is unable to `digest' a display data byte before the
next one arrives, it holds the SCL line LOW until the first
display data byte is stored. This slows down the
transmission rate of the I

C-bus but no data loss occurs.

6.9

Display latch

The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.

6.10

Shift register

The shift register serves to transfer display information
from the display RAM to the display latch while previous
data are displayed.

6.11

Segment outputs

The LCD drive section includes 24 segment outputs
S0 to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with the data resident in the display latch.
When less than 24 segment outputs are required the
unused segment outputs should be left open-circuit.

6.12

Backplane outputs

The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open. In the 1 : 3 multiplex drive mode BP3
carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.

6.13

Display RAM

The display RAM is a static 24

�

4-bit RAM which stores

LCD data. A logic 1 in the RAM bit-map indicates the `on'
state of the corresponding LCD segment; similarly, a
logic 0 indicates the `off' state.

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs.
The first RAM column corresponds to the 24 segments
operated with respect to backplane BP0 (see Fig.9).
In multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.

When display data are transmitted to the PCF8566 the
display bytes received are stored in the display RAM
according to the selected LCD drive mode. To illustrate the
filling order, an example of a 7-segment numeric display
showing all drive modes is given in Fig.10; the RAM filling
organization depicted applies equally to other LCD types.

With reference to Fig.10, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.

6.14

Data pointer

The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM.

The sequence commences with the initialization of the
data pointer by the LOAD DATA POINTER command.
Following this, an arriving data byte is stored starting at the
display RAM address indicated by the data pointer thereby
observing the filling order shown in Fig.10. The data
pointer is automatically incremented according to the LCD
configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode), by
three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex
drive mode).

6.15

Subaddress counter

The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should
be tied to V

or V

. The subaddress counter value is

defined by the DEVICE SELECT command. If the contents
of the subaddress counter and the hardware subaddress
do not agree then data storage is inhibited but the data
pointer is incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.

The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are being sent to the display RAM,
automatic wrap-over to the next PCF8566 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character.

Fig.9

Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.

handbook, full pagewidth

display RAM addresses (rows)/segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MGG389

1998

May

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex

rates

PCF8566

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handbook, full pagewidth

MBE534

BP0

BP1

BP2

BP1

BP2

BP3

BP0

x
x
x

1
2
3

x
x
x

n 1

n 2

n 3

n 4

n 5

n 6

n 7

bit/
BP

b
x
x

1
2
3

g
x
x

c
x
x

x
x

n 1

n 2

n 3

bit/
BP

c
x

1
2
3

d
g
x

e
x
x

n 1

n 2

bit/
BP

c
b

1
2
3

e
g
d

n 1

bit/
BP

c b a f

g e d DP

a b f

g e c d DP

b DP c a d g f

a c

b DP f

e g d

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

drive mode

static

1 : 2

multiplex

1 : 3

multiplex

1 : 4

multiplex

LCD segments

LCD backplanes

display RAM filling order

transmitted display byte

Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I

C-bus (X = data bit

unchanged).

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

6.16

Output bank selector

This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 then 1
are selected and, in the static mode, bit 0 is selected.

The PCF8566 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.

6.17

Input bank selector

The input bank selector loads display data into the display
RAM according to the selected LCD drive configuration.
Display data can be loaded in bit 2 in static drive mode or
in bits 2 and 3 in 1 : 2 drive mode by using the BANK
SELECT command. The input bank selector functions
independently of the output bank selector.

6.18

Blinker

The display blinking capabilities of the PCF8566 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.

An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and 1 : 2
LCD drive modes and can be implemented without any
communication overheads. By means of the output bank
selector, the displayed RAM banks are exchanged with
alternate RAM banks at the blinking frequency. This mode
can also be specified by the BLINK command.

In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.

If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.

Table 4

Blinking frequencies

BLINKING MODE

NORMAL OPERATING

MODE RATIO

POWER-SAVING

MODE RATIO

NOMINAL BLINKING FREQUENCY

blink

(Hz)

Off

blinking off

2 Hz

CLK

/92160

CLK

/15360

1 Hz

CLK

/184320

CLK

/30720

0.5 Hz

CLK

/368640

CLK

/61440

0.5

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

C-BUS DESCRIPTION

The I

C-bus is for 2-way, 2-line communication between

different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.

7.1

Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.

7.2

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).

7.3

System configuration

A device generating a message is a `transmitter', a device
receiving a message is a `receiver'. The device that
controls the message is the `master' and the devices which
are controlled by the master are the `slaves'.

7.4

Acknowledge

The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.

Fig.11 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

7.5

PCF8566 I

C-bus controller

The PCF8566 acts as an I

C-bus slave receiver. It does

not initiate I

C-bus transfers or transmit data to an I

C-bus

master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I

C-bus slave address,

on the transferred command data and on the hardware
subaddress.

In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to V

which defines the hardware subaddress 0.

In multiple device applications A0, A1 and A2 are left
open-circuit or tied to V

or V

according to a binary

coding scheme such that no two devices with a common
I

C-bus slave address have the same hardware

subaddress.

In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the `clock synchronization feature' of the I

C-bus and

serves to slow down fast transmitters. Data loss does not
occur.

7.6

Input filters

To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.

7.7

C-bus protocol

Two I

C-bus slave addresses (0111110 and 0111111) are

reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I

C-bus which

allows:

1. Up to 16 PCF8566s on the same I

C-bus for very large

LCD applications

2. The use of two types of LCD multiplex on the same

C-bus.

The I

C-bus protocol is shown in Fig.15. The sequence is

initiated with a START condition (S) from the I

C-bus

master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I

C-bus transfer. After acknowledgement, one or more

command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.

After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I

C-bus master issues a STOP condition (P).

7.8

Command decoder

The command decoder identifies command bytes that
arrive on the I

C-bus. All available commands carry a

continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.

The five commands available to the PCF8566 are defined
in Table 5.

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

Table 5

Definition of PCF8566 commands

Table 6

LCD drive mode

COMMAND/OPCODE

OPTIONS

DESCRIPTION

Mode set

see Table 6

defines LCD drive mode

see Table 7

defines LCD bias configuration

see Table 8

defines display status; the possibility to disable
the display allows implementation of blinking
under external control

see Table 9

defines power dissipation mode

Load data pointer

see Table 10

five bits of immediate data, bits P4 to P0, are
transferred to the data pointer to define one of
twenty-four display RAM addresses

Device select

see Table 11

three bits of immediate data, bits A0 to A2, are
transferred to the subaddress counter to define
one of eight hardware subaddresses

Bank select

see Table 12

defines input bank selection (storage of arriving
display data)

see Table 13

defines output bank selection (retrieval of LCD
display data)

the BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes

Blink

BF1 BF0

see Table 14

defines the blinking frequency

see Table 15

selects the blinking mode; normal operation
with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes

LCD DRIVE MODE

BIT M1

BIT M0

Static (1 BP)

1 : 2 MUX (2 BP)

1 : 3 MUX (3 BP)

1 : 4 MUX (4 BP)

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

Table 7

LCD bias configuration

Table 8

Display status

Table 9

Power dissipation mode

Table 10 Load data pointer

Table 11 Device select

Table 12 Input bank selection

Table 13 Output bank selection

Table 14 Blinking frequency

LCD BIAS

BIT B

bias

DISPLAY STATUS

BIT E

Disabled (blank)

Enabled

MODE

BIT LP

Normal mode

Power-saving mode

BITS

5-bit binary value of 0 to 23

BITS

3-bit binary value of 0 to 7

STATIC

1 : 2 MUX

BIT 1

RAM bit 0

RAM bits 0, 1

RAM bit 2

RAM bits 2, 3

STATIC

1 : 2 MUX

BIT 0

RAM bit 0

RAM bits 0, 1

RAM bit 2

RAM bits 2, 3

BLINK

FREQUENCY

BIT BF1

BIT BF0

Off

2 Hz

1 Hz

0.5 Hz

Table 15 Blink mode selection

7.9

Display controller

The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8566 and coordinates their effects.

The controller is also responsible for loading display data
into the display RAM as required by the filling order.

7.10

Cascaded operation

In large display configurations, up to 16 PCF8566s can be
distinguished on the same I

C-bus by using the 3-bit

hardware subaddress (A0, A1 and A2) and the
programmable I

C-bus slave address (SA0). It is also

possible to cascade up to 16 PCF8566s. When cascaded,
several PCF8566s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other PCF8566s of the cascade
contribute additional segment outputs but their backplane
outputs are left open-circuit (Fig.17).

The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8566s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8566s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A PCF8566 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be
restored by the first PCF8566 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
PCF8566s and PCF8576s is possible, giving cost effective
LCD applications.

BLINK MODE

BIT A

Normal blinking

Alternation blinking

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

10 DC CHARACTERISTICS

= 0 V; V

= 2.5 to 6 V; V

LCD

= V

2.5 to V

6 V; T

amb

40 to +85

�

C; unless otherwise specified.

Notes

1. Outputs open; inputs at V

or V

; external clock with 50% duty factor; I

C-bus inactive.

2. Resets all logic when V

< V

ref

3. Periodically sampled, not 100% tested.

4. Outputs measured one at a time.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

operating supply voltage

2.5

LCD

LCD supply voltage

2.5 V

operating supply current
(normal mode)

CLK

= 200 kHz; note 1

�

power saving mode supply current

= 3.5 V; V

LCD

= 0 V;

CLK

= 35 kHz; A0,

A1 and A2 tied to V

;

note 1

�

Logic

LOW level input voltage

0.3V

HIGH level input voltage

0.7V

LOW level output voltage

= 0 mA

0.05

HIGH level output voltage

= 0 mA

0.05

OL1

LOW level output current
(CLK and SYNC)

= 1 V; V

= 5 V

HIGH level output current (CLK)

= 4 V; V

= 5 V

OL2

LOW level output current
(SDA and SCL)

= 0.4 V; V

= 5 V

leakage current
(SA0, CLK, OSC, A0, A1, A2, SCL
and SDA)

= V

or V

�

pull-down current
(A0, A1, A2 and OSC)

= 1 V; V

= 5 V

150

�

puSYNC

pull-up resistor (SYNC)

ref

power-on reset level

note 2

1.3

tolerable spike width on bus

100

input capacitance

note 3

LCD outputs

DC voltage component
(BP0 to BP3)

= 35 nF

�

DC voltage component (S0 to S23)

= 5 nF

�

output impedance (BP0 to BP3)

LCD

= V

5 V; note 4

output impedance (S0 to S23)

LCD

= V

5 V; note 4

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

11 AC CHARACTERISTICS

= 0 V; V

= 2.5 to 6 V; V

LCD

= V

2.5 to V

6 V; T

amb

40 to +85

�

C; unless otherwise specified; note 1.

Notes

1. All timing values referred to V

and V

levels with an input voltage swing of V

to V

2. At f

CLK

< 125 kHz, I

C-bus maximum transmission speed is derated.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CLK

oscillator frequency (normal mode)

= 5 V; note 2

125

200

315

kHz

CLKLP

oscillator frequency (power saving
mode)

= 3.5 V

kHz

CLKH

CLK HIGH time

�

CLKL

CLK LOW time

�

PSYNC

SYNC propagation delay

400

SYNCL

SYNC LOW time

�

PLCD

driver delays with test loads

LCD

= V

5 V

�

C-bus

BUF

bus free time

4.7

�

HD; STA

START condition hold time

�

LOW

SCL LOW time

4.7

�

HIGH

SCL HIGH time

�

SU; STA

START condition set-up time
(repeated start code only)

4.7

�

HD; DAT

data hold time

�

SU; DAT

data set-up time

250

rise time

�

fall time

300

SU; STO

STOP condition set-up time

4.7

�

Fig.19 Test loads.

handbook, full pagewidth

MGG387

3.3 k

1.5 k

6.8 k

(2%)

CLK

(pin 4)

SDA, SCL

(pins 1, 2)

SYNC
(pin 3)

0.5VDD

VDD

S0 to S23

(pins 17 to 40)

Iload

�

Iload

�

BP0 to BP3

(pins 13 to 16)

1998

May

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex

rates

PCF8566

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APPLICA

TION INFORMA

TION

Fig.24 Single plane wiring of package PCF8566s.

handbook, full pagewidth

MGG386

PCF8566

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

SDA

SCL

SYNC

CLK

VDD

OSC

SA0

VSS

VLCD

VSS

VLCD

BP0

BP2

BP1

BP3

SDA
SCL
SYNC
CLK
VDD

PCF8566

S47

S46

S45

S44

S43

S42

S41

S40

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

BP0

BP2

BP1

BP3

S24

S25

S26

S27

open-circuit

BACKPLANES

SEGMENTS

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

Table 16 Bonding pad locations (dimensions in mm)

All x/y coordinates are referenced to centre of chip, (see Fig.25).

PAD NUMBER

SYMBOL

PIN

SDA

200

1235

SCL

400

1235

SYNC

605

1235

CLK

856

1235

1062

1235

OSC

1080

1025

1080

825

1080

625

1080

425

SA0

1080

225

1080

LCD

1080

347

BP0

1080

547

BP2

1080

747

BP1

1080

947

BP3

1074

1235

874

1235

674

1235

474

1235

274

1235

274

1235

474

1235

674

1235

874

1235

1074

1235

1080

765

S10

1080

565

S11

1080

365

S12

1080

165

S13

1080

S14

1080

235

S15

1080

435

S16

1080

635

S17

1080

835

S18

1080

1035

S19

1056

1235

S20

830

1235

S21

630

1235

S22

430

1235

S23

230

1235

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

0.3
0.1

2.45
2.25

0.25

0.42
0.30

0.22
0.14

15.6
15.2

7.6
7.5

0.762

2.25

12.3
11.8

1.15
1.05

0.6
0.3

7
0

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1.7
1.5

SOT158-1

92-11-17
95-01-24

detail X

(A )

pin 1 index

0.012
0.004

0.096
0.089

0.017
0.012

0.0087
0.0055

0.61
0.60

0.30
0.29

0.03

0.089

0.48
0.46

0.045
0.041

0.024
0.012

0.004

0.2

0.008

0.004

0.067
0.059

0.010

10 mm

scale

VSO40: plastic very small outline package; 40 leads

SOT158-1

max.

2.70

0.11

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

15 SOLDERING

15.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(order code 9398 652 90011).

15.2

DIP

15.2.1

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

�

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

15.2.2

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

�

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

�

C, contact may be up to 5 seconds.

15.3

SO and VSO

15.3.1

EFLOW SOLDERING

Reflow soldering techniques are suitable for all SO and
VSO packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

�

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

�

15.3.2

AVE SOLDERING

Wave soldering techniques can be used for all SO and
VSO packages if the following conditions are observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

�

The longitudinal axis of the package footprint must be
parallel to the solder flow.

�

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.3.3

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

1998 May 04

Philips Semiconductors

Product specification

Universal LCD driver for low multiplex
rates

PCF8566

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1998

SCA59

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands

415106/1200/06/pp40

Date of release: 1998 May 04

Document order number:

9397 750 03725

Электронный компонент: PCF8570P/F5

Document Outline