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Электронный компонент: SCN2652AC2A44

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Philips
Semiconductors
SCN2652/SCN68652
Multi-protocol communications controller
(MPCC)
Product specification
IC19 Data Handbook
1995 May 01
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
2
1995 May 01
853-1068 15179
DESCRIPTION
The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.
APPLICATIONS
Intelligent terminals
Line controllers
Network processors
Front end communications
Remote data concentrators
Communication test equipment
Computer to computer links
FEATURES
DC to 2Mbps data rate
Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
Programmable operation
8 or 16-bit tri-state data bus
Error control CRC or VRC or none
Character length 1 to 8 bits for BOP or 5 to 8 bits for BCP
SYNC or secondary station address comparison for BCP-BOP
Idle transmission of SYNC/FLAG or MARK for BCP-BOP
Automatic detection and generation of special BOP control
sequences, i.e., FLAG, ABORT, GA
Zero insertion and deletion for BOP
Short character detection for last BOP data character
SYNC generation, detection, and stripping for BCP
Maintenance mode for self-testing
TTL compatible
Single +5V supply
PIN CONFIGURATION
Pin Function Pin Function

1
NC
23 NC
2
CE
24 A0
3
RxC
25 BYTE
4
RxSI
26 DBEN
5
S/F
27 DB07
6
RxA
28 DB06
7
RxDA
29 DB05
8
RxSA
30 DB04
9
RxE
31 DB03
10 GND
32 DB02
11
DB08
33 DB01
12 NC
34 NC
13 DB09
35 DB00
14 DB10
36 VCC
15 DB11
37 RESET
16 DB12
38 TxA
17 DB13
39 TxBE
18 DB14
40 TxU
19 DB15
41 TxE
20 R/W
42 TxSQ
21 A2
43 TxC
22 A1
44 MM
1
39
17
28
40
29
18
7
PLCC
6
TOP VIEW
INDEX
CORNER
NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
29
30
31
32
33
34
35
36
37
38
39
40
CE
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
GND
DB08
DB09
DB10
DB11
DB12
DB13
DB14
DB15
R/W
A2
A1
A0
BYTE
DBEN
DB07
DB06
DB05
DB04
DB03
DB02
DB01
DB00
VCC
RESET
TxA
TxBE
TxU
TxE
TxSQ
TxC
MM
DIP
TOP VIEW
SD00057
Figure 1. Pin Configuration
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
3
ORDERING CODE
V
CC
= 5V +5%
PACKAGES
Commercial
0
C to +70
C
Industrial
-40
C to +85
C
DWG #
40-Pin Ceramic Dual In-Line Package (DIP)
SCN2652AC2F40 / SCN68652AC2F40
0590B
40-Pin Plastic Dual In-Line Package (DIP)
SCN2652AC2N40 / SCN68652AC2N40
Contact Factory
SOT129-1
44-Pin Square Plastic Lead Chip Carrier (PLCC)
SCN2652AC2A44 / SCN68652AC2A44
Contact Factory
SOT187-2
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNIT
T
A
Operating ambient temperature
2
Note 4
C
T
STG
Storage temperature
65 to +150
C
V
CC
All inputs with respect to GND
3
0.3 to +7
V
NOTES:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification
is not implied.
2. For operating at elevated temperatures the device must be derated based on +150
C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
BLOCK DIAGRAM
DATA
BUS
BUFFER
DB15
DB00
RESET
MM
READ/
WRITE
LOGIC
AND
CONTROL
A2A0
BYTE
R/W
CE
DBEN
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
16 BITS
16
PCSAR
INTERNAL
BUS
RECEIVER
DATA/STATUS
REGISTER
RDSR
RECEIVER
LOGIC AND
CONTROL
16
PARAMETER
CONTROL
REGISTER
8 BITS
PCR
VCC
GND
TRANSMITTER
DATA/STATUS
REGISTER
TDSR
TRANSMITTER
LOGIC AND
CONTROL
16
RxC RxSI
TxC TxSO
S/F
RxE
RxA
RxDA
RxSA
TxE
TxA
TxBE
TxU
SD00058
Figure 2. Block Diagram
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
4
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
DB15DB00
1710
2431
I/O
Data Bus: DB07DB00 contain bidirectional data while DB15DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR'ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
A2A0
1921
I
Address Bus: A2A0 select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
BYTE
22
I
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
CE
1
I
Chip Enable: A high input permits a data bus operation when DBEN is activated.
R/W
18
I
Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
DBEN
23
I
Data Bus Enable: After A2A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
RESET
33
I
Reset: A high level initializes all internal registers (to zero) and timing.
MM
40
I
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
RxE
8
I
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
RxA
5
O
Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR
13
) is set, the first
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
RxDA*
6
O
Receiver Data Available: RxDA is asserted when an assembled character is in RDSR
L
and is ready to
be presented to the processor. This output is reset when RDSR
L
is read.
RxC
2
I
Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
S/F
4
O
SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
RxSA*
7
O
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSR
H
except for RSOM. It is cleared when RDSR
H
is read.
RxSI
3
I
Receiver Serial Input: RxSI is the received serial data. Mark = `1', space = `0'.
TxE
37
I
Transmitter Enable: A high level input enables the transmitter data path between TDSR
L
and TxSO. At
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
TxA
34
O
Transmitter Active: TxA is asserted after TSOM (TDSR
8
) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
TxBE*
35
O
Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
TxU*
36
O
Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR
11
. TxU is reset by RESET or setting of TSOM (TDSR
8
), synchronized by the
falling edge of TxC.
TxC
39
I
Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
TxSO
38
O
Transmitter Serial Output: TxSO is the transmitted serial data. Mark = `1', space = `0'.
V
CC
32
I
+5V: Power supply.
GND
9
I
Ground: 0V reference ground.
*Indicates possible interrupt signal
Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
5
Table 1.
Register Access
REGISTERS
NO. OF BITS
DESCRIPTION*
Addressable
PCSAR
Parameter control sync/
address register
16
PCSAR
H
and PCR contain parameters common to the
receiver and transmitter. PCSAR
L
contains a programmable
SYNC character (BCP) or secondary station address (BOP).
PCR
Parameter control register
8
RDSR
H
contains receiver status information.
RDSR
Receive data/status register
16
RDSR
L
= RxDB contains the received assembled character.
TDSR
Transmit data/status register
16
TDSR
H
contains transmitter command and status
information. TDSRL = TxDB contains the character to be
transmitted
Non-Addressable
CCSR
Control character shift register
8
HSR
Holding shift register
16
RxSR
Receiver shift register
8
These registers are used for character assembly (CSSR
TxSR
Transmitter shift register
8
These registers are used for character assembly (CSSR,
HSR, RxSR), disassembly (TxSR), and CRC
RxCRC
Receiver CRC accumulation
register
16
,
),
y (
),
accumulation/generation (RxCRC, TxCRC).
TxCRC
Transmitter CRC generation
register
16
NOTES:
*H = High byte bits 158
L = Low byte bits 70
Table 2.
Error Control
CHARACTER
DESCRIPTION
FCS
Frame check sequence is transmitted/received
as 16 bits following the last data character of a
BOP message. The divisor is usually
CRCCCITT (X
16
+ X
12
+ X
5
+ 1) with dividend
preset to 1's but can be other wise determined
by ECM. The inverted remainder is transmitter as
the FCS.
BCC
Block check character is transmitted/received as
two successive characters following the last data
character of a BCP message. The polynomial is
CRC16 (X
16
+ X
15
+ X
2
+ 1) or CRCCCITT
with dividend preset to 0's (as specified by
ECM). The true remainder is transmitted as the
BCC.
Table 3.
Special Characters
OPERATION
BIT PATTERN
FUNCTION
BOP
FLAG
01111110
Frame message
ABORT
11111111 generation
Terminate communication
01111111 detection
GA
01111111
Terminate loop mode
repeater function
Address
(PCSAR
L
)
1
Secondary station address
BCP
SYNC
(PCSAR
L
) or
(TxDB)
2
generation
Character synchronization
NOTES:
1. ( ) = contents of.
2. For IDLE = 0 or 1 respectively.
APA
PCSAR
PCR
RDSR
TDSR
15
PROTO
14
SS/GA
13
SAM
12
IDLE
11
E C M
10
9
8
S/AR
7
6
5
4
3
2 1
0
TxCL
15
14
13
12
11
RxCL
10
9
8
Tx
CL
E
R x
CL
E
RERR
15
A B C
14
13
ROR
12
RAB/
GA
11
REOM
10
9
8
RxDB
RSOM
TERR
15
NOT DEFINED
14
13
TGA
12
TABORT
11
TEOM
10
9
8
TxDB
TSOM
NOTE:
Refer to Register Formats for mnemonics and description.
SD00059
Figure 3. Short Form Register Bit Formats