Document Outline
- FEATURES
- GENERAL DESCRIPTION
- APPLICATIONS
- ORDERING INFORMATION
- PINNING
- CHARACTERISTICS
- APPLICATION INFORMATION
- PACKAGE OUTLINE
- SOLDERING
- DATA SHEET STATUS
- DEFINITIONS
- DISCLAIMERS
DATA SHEET
Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
2001 Oct 01
INTEGRATED CIRCUITS
TDA10021HT
DVB-C channel receiver
2001 Oct 01
2
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
FEATURES
4, 16, 32, 64, 128 and 256 Quadrature Amplitude
Modulation (QAM) demodulator (DVB-C compatible:
ETS 300-429/ITU-T J83 annex A/C)
High performance for 256 QAM, especially for direct
IF applications
On-chip 10-bit Analog-to-Digital Converter (ADC)
On-chip Phase-Locked Loop (PLL) for crystal frequency
multiplication (typically 4 MHz crystal)
Digital downconversion
Programmable half Nyquist filter (roll off = 0.15 or 0.13)
Two Pulse Width Modulated (PWM) AGC outputs with
programmable take over point (for tuner and
downconverter control)
Clock timing recovery, with programmable 2nd-order
loop filter
Variable symbol rate capability from SACLK/64 to
SACLK/4 (SACLK = 36 MHz maximum)
Programmable anti-aliasing filters
Full digital carrier recovery loop
Carrier acquisition range up to 18% of symbol rate
Integrated adaptive equalizer (linear transversal
equalizer or decision feedback equalizer)
On-chip Forward Error Correction (FEC) decoder
(de-interleaver and RS decoder) and fully DVB-C
compliant
DVB compatible differential decoding and mapping
Parallel and serial transport stream interface
simultaneously
I
2
C-bus interface, for easy control
CMOS 0.2
m technology.
APPLICATIONS
Cable set-top boxes
Cable modems
MMDS (ETS 300-749) set-top boxes.
GENERAL DESCRIPTION
The TDA10021HT is a single-chip DVB-C channel
receiver for 4, 16, 32, 64, 128 and 256 QAM modulated
signals. The device interfaces directly to the IF signal,
which is sampled by a 10-bit ADC.
The TDA10021HT performs the clock and the carrier
recovery functions. The digital loop filters for both clock
and carrier recovery are programmable in order to
optimize their characteristics according to the current
application.
After baseband conversion, equalization filters are used
for echo cancellation in cable applications. These filters
are configured as either a T-spaced transversal equalizer
or a Decision Feedback Equalizer (DFE), so that the
system performance can be optimized according to the
network characteristics. A proprietary equalization
algorithm, independent of carrier offset, is achieved in
order to assist carrier recovery. A decision directed
algorithm then takes place, to achieve final equalization
convergence.
The TDA10021HT implements a FORNEY convolutional
de-interleaver of depth 12 blocks and a Reed-Solomon
decoder which corrects up to 8 erroneous bytes. The
de-interleaver and the RS decoder are automatically
synchronized by the frame synchronization algorithm
which uses the MPEG-2 sync byte. Finally descrambling
according to DVB-C standard, is achieved at the Reed
Solomon output. This device is controlled via an I
2
C-bus.
Designed in 0.2
m CMOS technology and housed in a
64 pin TQFP package, the TDA10021HT operates over
the commercial temperature range.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA10021HT
TQFP64
plastic thin quad flat package; 64 leads; body 10
10
1.0 mm
SOT357-1
2001
Oct
01
3
Philips Semiconductors
Product specification
D
VB-C channel receiv
er
TD
A10021HT
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BLOCK DIA
GRAM
handbook, full pagewidth
MGW343
CLOCK
RECOVERY
I2
C-BUS
INTERFACE
GPIO
AGC
PWM
PWM
TIMING
INTERPOLATOR
RS
DECODER
OUTPUT
INTERFACE
JTAG
DE-SCRAMBLER
DE-INTERLEAVER
DECIMATION
FILTERS
BASEBAND
CONVERSION
ADC
PLL
EQUALIZER
HALF
NYQUIST
CARRIER
RECOVERY
DECISION
DIFFERENTIAL
DECODER
10
8
IF
TDA10021HT
2
3
62
61
64
63
1, 24,
7, 41
4, 8,
25, 42
14, 30,
43
15, 31,
44
50
49
52
51
55, 60
56, 59
13
5
9
11
17
54
18
19
SACLK
AGCTUN
AGCIF
SCL
SDA
SDAT
DEN
OCLK
programmable
interface
serial
interface
PSYNC
UNCOR
DO [ 7 : 0 ]
37 to 40,
45 to 48
36
35
34
33
20
21
22
23
26
27
28
32
29
21
6
16
58
57
10
SCLT
ENSERI
TCK
TDI
TRST
TMS
TDO
CTRL
GPIO
4
4
3
3
2
2
VDDD18
VSSD18
VDDD50
VDDD33
VSSD33
VSSA2
VDDD1
VSSD1
VCCD(PLL)
PLLGND
DGND
VCCA (PLL)
VDDA3
VSSA3
TEST
ENSERI
IICDIV
CLR#
VIP
VIM
Vref(neg)
VDDA2
XIN
XOUT
53
Vref(pos)
12
SADDR
Fig.1 Block diagram.
2001 Oct 01
4
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
PINNING
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
V
DDD18
1
S
digital supply voltage for the core (1.8 V typ.)
XIN
2
I
XTAL oscillator input pin: a fundamental XTAL oscillator is connected between the
XIN and XOUT pins. The XTAL frequency must be chosen so that the system
frequency SYSCLK (XIN
multiplying factor of the PLL) equals 1.6 times the tuner
output intermediate frequency; i.e. SYSCLK = 1.6
IF.
XOUT
3
O
XTAL oscillator output pin: a fundamental XTAL oscillator is connected between the
XIN and XOUT pins
V
SSD18
4
G
digital ground for the core
SACLK
5
O
sampling clock: this output clock can be fed to an external 10-bit ADC as the
sampling clock; SACLK = SYSCLK/2
TEST
6
I
test input pin: in normal mode, pin TEST must be connected to ground
V
DDD18
7
S
digital supply voltage for the core (1.8 V typ.)
V
SSD18
8
G
digital ground for the core
AGCTUN
9
O/OD
first PWM encoded output signal for AGC tuner: this signal is fed to the AGC
amplifier through a single RC network. The maximum signal frequency on the
VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.
IICDIV
10
I
IICDIV: this pin allows the frequency of the I
2
C-bus internal system clock to be
selected, depending on the crystal frequency. The internal I
2
C-bus clock is a
division of XIN by 4
IICDIV
.
AGCIF
11
O/OD
second PWM encoded output signal for the AGC IF: This signal is fed to the AGC
amplifier through a single RC network. The maximum signal frequency on the
VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.
However AGCIF can also be configured to output a PWM signal, the value of which
can be programmed through the I
2
C-bus interface.
SADDR
12
I
SADDR is the LSB of the I
2
C-bus address of the TDA10021HT. The MSBs are
internally set to 000110. Therefore the complete I
2
C-bus address of the
TDA10021HT is (MSB to LSB) 0, 0, 0, 1, 1, 0 and SADDR.
V
DDD50
13
S
digital supply voltage for the pad 5.0 V (necessary for 5 V tolerant inputs)
V
DDD33
14
S
digital supply voltage for the pads (3.3 V typ.)
V
SSD33
15
G
digital ground for the pads
CLR#
16
I
the CLR# input is asynchronous and active LOW, and clears the TDA10021HT:
When CLR# goes LOW, the circuit immediately enters its reset mode and normal
operation will resume 4 XIN falling edges after CLR# returns HIGH. The I
2
C-bus
register contents are all initialized to their default values. The minimum width of
CLR# at LOW level is 4 XIN clock periods.
SCL
17
I
I
2
C-bus clock input: SCL should nominally be a square wave with a maximum
frequency of 400 kHz. SCL is generated by the system I
2
C-bus master.
SDA
18
I/OD
SDA is a bidirectional signal: it is the serial input/output of the I
2
C-bus internal block.
A pull-up resistor (typically 4.7 k
) must be connected between SDA and V
DDD50
for
proper operation (open-drain output).
SDAT
19
I/OD
SDAT is equivalent to SDA I/O of the TDA10021HT but can be 3-stated by I
2
C-bus
programming. It is actually the output of a switch controlled by parameter BYPIIC of
register TEST (index 0F). SDAT is an open-drain output and therefore requires an
external pull-up resistor.
2001 Oct 01
5
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
SCLT
20
OD
SCLT can be configured to be a control line output or to output the SCL input. This
is controlled by parameter BYPIIC and CTRL_SCLT of register TEST (index 0F).
SCLT is an open-drain output and therefore requires an external pull-up resistor.
ENSERI
21
I
when HIGH this pin enables the serial output transport stream through the
boundary scan pins TRST, TDO, TCK, TDI and TMS (serial interface). Must be set
LOW in bist and boundary scan mode.
TCK
22
I/O
test clock: an independent clock used to drive the TAP controller in boundary scan
mode. In normal mode of operation, TCK must be set LOW. In serial stream mode,
TCK is the clock output (OCLK).
TDI
23
I/O
test data input: the serial input for test data and instruction in boundary scan mode.
In normal mode of operation, TDI must be set LOW. In serial stream mode, the TDI
is the PSYNC output.
V
DDDI8
24
S
digital supply voltage for the core (1.8 V typ.)
V
SSDI8
25
G
digital ground for the core
TRST
26
I/O
test reset: this active LOW input signal is used to reset the TAP controller in
boundary scan mode. In normal mode of operation, TRST must be set LOW. In
serial stream mode, TRST is the uncorrectable output (UNCOR).
TMS
27
I/O
test mode select: this input signal provides the logic levels needed to change the
TAP controller from state to state. In normal mode of operation, TMS must be set to
HIGH. In serial stream mode, TMS is the DEN output.
TDO
28
O
test data output: this is the serial test output pin used in boundary scan mode.
Serial data is provided on the falling edge of TCK. In serial stream mode, TDO is
the data output (DO).
GPIO
29
OD
GPIO can be configured by the I
2
C-bus either as:
A Front-End Lock indicator (FEL) (default mode)
An active LOW output interrupt line (IT) which can be configured by the I
2
C-bus
interface
A control output pin programmable by I
2
C-bus.
GPIO is an open-drain output and therefore requires an external pull-up resistor.
V
DDD33
30
S
digital supply voltage for the pads (3.3 V typ.)
V
SSD33
31
G
digital ground for the pads
CTRL
32
OD
CTRL is a control output pin programmable by the I
2
C-bus. CTRL is an open-drain
output and therefore requires an external pull-up resistor.
UNCOR
33
O
uncorrectable packet: this output signal is HIGH when the provided packet is
uncorrectable (during the 188 bytes of the packet). The uncorrectable packet is not
affected by the Reed Solomon decoder, but the MSB of the byte following the sync
byte is forced to logic 1 for the MPEG-2 process: error flag indicator (if RSI and IEI
are set LOW in the I
2
C-bus table).
PSYNC
34
O
pulse synchro: this output signal goes HIGH when the sync byte (0x47) is provided,
then it goes LOW until the next sync byte
OCLK
35
O
output clock: this is the output clock for the DO[7:0] data outputs. OCLK is internally
generated depending on which interface is selected.
DEN
36
O
data enable: this output signal is HIGH when there is valid data on the output bus
DO[7:0]
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
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