1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

FEATURES

Low power

Low supply voltage (2.7 V)

Integrated high-pass filter to cancel DC offset (ADC)

Analog loop-through function

Multiple digital input/output formats possible

256f

system clock frequency

Several power-down modes

Digital de-emphasis (DAC)

Overload detector to enable automatic recording level
adjustment (ADC)

Input pads suitable for 5.5 V; low supply voltage
interfacing

High dynamic range

DAC requires only one capacitor for post-filtering

Small 44-pin quad flat pack with 0.8 mm pitch

256f

system clock frequency in Analog-to-Digital (AD)

and Digital-to-Analog (DA) mode

Choice of three system clock frequencies
(192f

, 256f

or 384f

) in DA mode.

APPLICATION

Portable digital audio equipment.

GENERAL DESCRIPTION

The TDA1309H is a single chip stereo analog-to-digital
and digital-to-analog converter employing bitstream
conversion techniques. The low voltage requirement
makes the device eminently suitable for use in low-voltage
low-power portable digital audio equipment which
incorporates recording and playback functions.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA1309H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10

1.75 mm

SOT307-2

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

QUICK REFERENCE DATA
V

DDD

= V

DDA

= V

DDO

= V

DDD(F)

= 3 V; V

SSD

= V

SSA

= V

SSO

= V

SSD(F)

= 0 V; T

amb

= 25

C; full scale sine wave input;

mode 1; f

= 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless

otherwise specified.

Notes

1. The input voltage for full scale digital output is a function of V

DDA(AD)

2. At full scale digital input; no de-emphasis; V

O(rms)

is a function of V

DDA(DA)

3. 18-bit input data.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX. UNIT

Supply

DDA(AD)

ADC analog supply voltage (pin 8)

2.7

3.0

4.0

DDA(DA)

DAC analog supply voltage (pin 25)

2.7

3.0

4.0

DDO

operational amplifiers supply voltage
(pin 19)

2.7

3.0

4.0

DDD

ADC and DAC digital supply voltage
(pin 28)

2.7

3.0

4.0

DDD(F)

digital filters supply voltage (pin 34)

2.7

3.0

4.0

DDA(AD)

ADC analog supply current (pin 8)

12.5

DDA(DA)

DAC analog supply current (pin 25)

3.5

DDO

operational amplifiers supply current
(pin 19)

DDD

ADC and DAC digital supply current
(pin 28)

0.2

0.5

DDD(F)

digital filters supply current (pin 34)

PD(DA)

DAC power-down current

PD(AD)

ADC power-down current

amb

operating ambient temperature

+75

Analog-to-digital converter

I(rms)

input voltage (RMS value)

note 1

0.5

0.54

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB

60 dB; A-weighted

S/N

idle channel signal-to-noise ratio

= 0 V; A-weighted

channel separation

Digital-to-analog converter

O(rms)

output voltage (RMS value)

note 2

0.43

0.5

0.57

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

at 0 dB

60 dB; A-weighted

60 dB; A-weighted; note 3

S/N

idle channel signal-to-noise ratio

code 0000H; A-weighted

104

channel separation

100

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

BLOCK DIAGRAM

book, full pagewidth

MGE766

4.7 k

1.5 k

750

0.22

2.2 nF

330 pF

0.22

DAC

DIGITAL

FILTER

DIGITAL

FILTER

DAC

DIGITAL

INTERFACE

DIGITAL

INTERFACE

MODE SELECT

ADC

CURRENT

REFERENCE

ref

BAIR

VLO

ADENB

ADBCK

ADSD

ADPON

ANLPTR

ABCK

ASD

APON

SS(I/O)

DDD

SSD

analog output

ref

analog input

DACL

analog output

SSO

DDO

SSA(DA)

DDA(DA)

SSD(F)

DDD(F)

DADEM

MODE0

MODE1

MODE2

CLKEDGE

TEST0

TEST1

SYSCLK

ref(neg)

ref(pos)

BAOL

BAIL

ref

DDA(AD)

analog input

SSA(AD)

DDA(AD)

I ref

I DAC

TDA1309H

Supply decoupling on pins 19, 25, 28 and 34; 0.22

F (ceramic), 47

F (electrolytic).

Capacitance at pin 11 should be close to pins 11 and 9.

Fig.1 Block diagram.

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

PINNING

SYMBOL

PIN

DESCRIPTION

ADBCK

ADC input bit clock; 32f

or 64f

ADWS

ADC word select input at f

MODE0

ADC/DAC mode select input

ADENB

ADC serial data enable input (active HIGH)

OVLOAD

ADC output overload flag (active LOW)

ADPON

ADC power-on-mode input (active HIGH)

SSA(AD)

ADC analog ground supply voltage

DDA(AD)

ADC analog supply voltage

ref(neg)

ADC negative reference voltage input (ground)

ref

ADC decoupling capacitor

ref(pos)

ADC positive reference voltage decoupling capacitor

BAOL

ADC input amplifier output left

BAIL

ADC input amplifier virtual ground left

BAIR

ADC input amplifier virtual ground right

BAOR

ADC input amplifier output right

ref

ADC decoupling capacitor

ref

ADC/DAC reference current resistor input

ref

DAC decoupling capacitor

DDO

ADC/DAC operational amplifier supply voltage

SSO

ADC/DAC operational amplifier ground supply voltage

DAC output voltage left

DACL

DAC output current left

DACR

DAC output current right

DAC output voltage right

DDA(DA)

DAC analog supply voltage

SSA(DA)

DAC analog ground supply voltage

SSD

ADC/DAC digital ground supply voltage

DDD

ADC/DAC digital supply voltage

DAPON

DAC power-on-mode input (active HIGH)

DADEM

DAC digital de-emphasis input (active HIGH)

DABCK

DAC input bit clock; 32f

, 48f

or 64f

DAWS

DAC word select input at f

SSD(F)

ADC/DAC digital filters ground supply voltage

DDD(F)

ADC/DAC digital filters supply voltage

DASDA

DAC serial data input

ANLPTR

ADC/DAC analog loop-through input (active HIGH)

TEST0

ADC/DAC enable test mode 0 input (LOW is normal mode)

TEST1

ADC/DAC enable test mode 1 input (LOW is normal mode)

SS(I/O)

ADC/DAC digital input/output ground supply voltage

SYSCLK

ADC/DAC system clock input (f

sys

= 256f

; DAC also 192f

and 384f

)

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

FUNCTIONAL DESCRIPTION

Figure 1 illustrates the various components of the
TDA1309H.
The analog-to-digital converter is a bitstream type
converter, both channels are sampled simultaneously.
The digital-to-analog converter is a BCC (Bitstream
Continuous Calibration) type converter. The digital filter for
the ADC is a bit serial IIR filter that produces a fairly linear
phase response up to 15 kHz. A high-pass filter is
incorporated in the down-sampling path to remove DC
offsets. An overload detection circuit is incorporated to
facilitate automatic recording level adjustment.

The digital up-sample filter for the DAC is partly IIR, with
virtual linear phase response up to 15 kHz, and partly FIR.
A switchable digital de-emphasis circuit is also
incorporated. Due to the BCC principle used, the DAC
needs only single pole post-filtering (one external
capacitor) to meet the out-of-band suppression
requirement.

The ADC and DAC channels have separate power-down
modes, to reduce power if one of them is not in use.
An analog loop-through function enables analog-input
analog-output mode without using the ADC and DAC
converters or filters, thereby switching them off to reduce
power consumption.

The digital interfaces accommodates, 16 and 18-bit,
I

S-bus and LSB justified formats. The ADC digital output

can be made 3-state by means of the ADENB signal, this
enables the use of a digital bus.

The TDA1309H interface accommodates slave mode only,
therefore, the system ICs must provide the system clock,
bit clock and word clock signals. For the DAC, the
TDA1309H accepts the data together with these clocks,
for the ADC it delivers the data in response to these clocks.
Within one stereo frame, the first sample always
represents the left channel. When sending data the
unused bit positions are set to zero, when receiving data
these bit positions are don't cares.

To accommodate the various interface formats and
system clock frequencies four control pins are provided,
MODE0 to MODE2 for mode selection and CLKEDGE
which selects the active edge of the BCK signal. Table 1
gives the interface mode selection, Fig.3 illustrates the
ADC/DAC data formats and Fig.5 the operating modes.

The section of the TDA1309H is designed to
accommodate two main modes:

1. The 256f

mode in which analog-to-digital and

digital-to-analog can be used

2. The 192f

or 384f

mode (digital-to-analog only).

Table 1

Interface mode selection

Note

1. Only digital-to-analog.

Table 2

Clock edge mode

DEVICE PIN

ADC/DAC FORMATS

MODE 2

MODE 1

MODE 0

TYPE

BITS

BCK

SYS; f

sys

FIGURE

LSB justified

32f

256f

3(a)

LSB justified

64f

256f

3(b)

LSB justified

48f

192f

(1)

4(a)

LSB justified

64f

256f

3(c)

S-bus

32f

256f

3(d)

S-bus

64f

256f

3(e)

S-bus

48f

384f

(1)

4(b)

S-bus

64f

256f

3(f)

CLKEDGE

VALID EDGE OF BCK

ADC

DAC

falling

rising

falling

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Human body model: C = 100 pF; R = 1.5 k

; 3 zaps positive and 3 zaps negative.

2. Machine model: C = 200 pF; L = 0.5

H; R = 10

; 3 zaps positive and 3 zaps negative.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

"SNW-FQ-611E". The number of this quality specification can be found in the "Quality Reference

Handbook". The handbook can be ordered using the code 9397 750 00192.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDA(AD)

analog supply voltage (pin 8)

4.5

DDA(DA)

analog supply voltage (pin 25)

4.5

DDO

operational amplifiers supply voltage
(pin 19)

4.5

DDD

digital supply voltage (pin 28)

4.5

DDD(F)

digital filters supply voltage (pin 34)

4.5

maximum supply voltage difference

100

maximum ground supply voltage
difference

100

maximum input voltage

0.5

+ 0.5

DC clamp input diode current

0.5 V or

> V

+ 0.5 V

DC output clamp diode current;
(output type 2 mA)

0.5 V or

> V

+ 0.5 V

stg

storage temperature

+150

amb

operating ambient temperature

+75

electrostatic handling

note 1

1500

+1500

note 2

300

+300

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

CHARACTERISTICS
V

DDD

= V

DDA

= V

DDO

= V

DDD(F)

= 3 V; V

SSD

= V

SSA

= V

SSO

= V

SSD(F)

= 0 V; T

amb

= 25

C; full scale sine wave input;

mode 1; f

= 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless

otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

DDA(AD)

ADC analog supply
voltage (pin 8)

2.7

3.0

4.0

DDA(DA)

DAC analog supply
voltage (pin 25)

2.7

3.0

4.0

DDO

operational amplifiers
supply voltage (pin 19)

2.7

3.0

4.0

DDD

ADC/DAC digital supply
voltage (pin 28)

2.7

3.0

4.0

DDD(F)

digital filters supply voltage
(pin 34)

2.7

3.0

4.0

DDA(AD)

ADC analog supply current
(pin 8)

12.5

ADC power-down

0.3

DDA(DA)

DAC analog supply current
(pin 25)

3.5

DAC power-down

1.4

DDO

operational amplifiers
supply current (pin 19)

DAC power-down

5.5

ADC power-down

ADC/DAC power-down

DDD

ADC/DAC digital supply
current (pin 28)

0.2

0.5

DDD(F)

digital filters supply current
(pin 34)

DAC power-down

ADC power-down

DDD(F)q

digital filters quiescent
current

100

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

Analog-to-digital converter

I(rms)

input voltage (RMS value)

note 1

0.5

0.54

input current
(pins 13 and 14)

unbalance between
channels

0.3

RES

resolution

16-bit format

bits

18-bit format

bits

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB

20 dB

60 dB; A-weighted

S/N

idle channel
signal-to-noise ratio

= 0 V; A-weighted

channel separation

PSRR

power supply rejection ratio note 2

Digital-to-analog converter

O(rms)

output voltage
(RMS value)

note 3

0.43

0.5

0.57

unbalance between
channels

0.1

load resistance

load capacitance

note 4

200

RES

resolution

16-bit format

bits

18-bit format

bits

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB

20 dB

60 dB; A-weighted

60 dB; A-weighted;

note 5

S/N

idle channel
signal-to-noise ratio

code 0000H; A-weighted

104

channel separation

100

PSRR

power supply rejection ratio note 2

Analog loop-through (mode e)

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB

S/N

idle channel
signal-to-noise ratio

= 0 V; A-weighted

ltr

loop-through gain

note 1

1.1

DC offset error

1.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

Analog-to-digital decimation filter

s(o)

output sample frequency

44.1

kHz

s(i)

input sample frequency

128f

sys

system clock frequency

256f

signal bandwidth

s(o)

= 44.1 kHz

0.02

kHz

sup

aliasing suppression

s(o)

B < f

< 2f

s(o)

note 6

> 2f

s(o)

B; note 6

frequency response

= 20 Hz to 20 kHz

0.2

+0.2

det

overload detection level

note 7

0.11

Digital-to-analog interpolation filter

s(o)

output sample frequency

64f

s(i)

input sample frequency

44.1

kHz

sys

system clock frequency

256f

signal bandwidth

s(i)

= 44.1 kHz

0.02

kHz

frequency response

= 20 Hz to 20 kHz

0.2

+0.2

SUP

out-of-band suppression

Digital part; note 8

NPUTS

(

PINS

4, 6, 29

32, 35

38, 40

AND

44)

LOW level input voltage

0.5

0.3V

DDD

LOW level input current

= V

SSD

HIGH level input current

= V

DDD

I(max)

maximum input
capacitance

NPUTS

(

PINS

4, 6, 29

32, 35

38, 40

AND

42)

HIGH level input voltage

0.7V

DDD

5.5

NPUTS

(

PINS

AND

44)

HIGH level input voltage

0.7V

DDD

+ 0.5

UTPUTS

(

PINS

AND

41)

LOW level output voltage

= 2 mA

0.5

HIGH level output voltage

2 mA

DDD

0.5

3-state leakage current

= V

DDD

or V

SSD

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

Notes

1. V

for full scale digital output is a function of V

DDA(AD)

, 0.5 V (RMS) (at 3 V the digital voltages are equivalent to

1.1 dB in the digital domain).

2. V

ripple

= 1% of the supply voltage and f

ripple

= 100 Hz.

3. At full scale digital input; no de-emphasis; V

O(rms)

is a function of V

DDA(DA)

4. For a load capacitance greater than 33 pF a series resistor of 200

is recommended.

5. 18 bits input data.

6. The aliasing suppression frequency is mirrored around 128f

7. V

DDA

= 3 V; indicated digital level is with respect to

1.1 dB (no overload).

8. All digital voltages = 2.7 to 4.0 V; all ground supply voltages = 0 V; T

amb

20 to +75

Timing

IT CLOCK

(BCK)

RELATED SIGNALS

(see Fig.6); CLKEDGE = 0

clock period

300

clock HIGH time

100

clock LOW time

100

rise time

fall time

suWS

set-up time WS to rising
edge of BCK

hWS

hold time WS to rising edge
of BCK

suDA

set-up time SDA (DAC) to
rising edge of BCK

hDA

hold time SDA (DAC) to
rising edge of BCK

hAD

hold time SDA (ADC) to
falling edge of BCK

dAD

delay time SDA (ADC) to
falling edge of BCK

YSTEM CLOCK

(SYSCLK)

RELATED SIGNALS

(see Fig.7)

clock period

clock HIGH time

clock LOW time

rise time

fall time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9398 510 63011).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the

board direction and must incorporate solder
thieves downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages:
QFP52 (SOT379-1), QFP100 (SOT317-1),
QFP100 (SOT317-2), QFP100 (SOT382-1) or
QFP160 (SOT322-1).

During placement and before soldering, the package
must be fixed with a droplet of adhesive. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

C. When using a dedicated tool, all other leads can

be soldered in one operation within 2 to 5 seconds
between 270 and 320

1996 Oct 21

Philips Semiconductors

Product specification

Low-voltage low-power stereo bitstream
ADC/DAC

TDA1309H

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.2

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA52

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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

517021/1200/04/pp24

Date of release: 1996 Oct 21

Document order number:

9397 750 00879

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA1309H/N3

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA1309H/N3