1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

FEATURES

Voltage output

Space saving packages SO8 or DIP8

Low power consumption

Wide dynamic range (16-bit resolution)

Continuous Calibration (CC) concept

Easy application:

single 4 to 5.5 V rail supply

output current and bias current are proportional to the

supply voltage

integrated current-to-voltage converter

Fast settling time permits 2, 4 and 8

oversampling

(serial input) or double-speed operation at
4

oversampling

Internal bias current ensures maximum dynamic range

Wide operating temperature range (

C to +85

Compatible with most current Japanese input formats:
time multiplexed, two's complement, TTL

No zero-crossing distortion

Cost efficient.

GENERAL DESCRIPTION

The TDA1311A; AT is a voltage-driven digital-to-analog
converter and is new generation of DAC devices which
embodies the innovative technique of Continuous
Calibration (CC). The largest bit-currents are repeatedly
generated by one single current reference source. This
duplication is based upon an internal charge storage
principle which has an accuracy insensitive to ageing,
temperature matching and process variations.

The TDA1311A; AT is fabricated in a 1.0

m CMOS

process and features an extremely low-power dissipation,
small package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the CC-DAC is eminently
suitable for use in (portable) digital audio equipment.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA1311A

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

TDA1311AT

SO8

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

5.5

supply current

= 5 V at code 0000H

3.4

6.0

full scale output voltage

= 5 V

1.8

2.0

2.2

(THD+N)/S

total harmonic distortion
plus noise

at 0 dB signal level

0.04

0.07

60 dB signal level

60 dB signal level;

A-weighted

S/N

signal-to-noise ratio at
bipolar zero

A-weighted at code 0000H

current settling time to

LSB

0.2

input bit rate at data input

18.4

Mbits/s

BCK

clock frequency at clock
input

18.4

MHz

full scale temperature
coefficient at analog outputs
(I

; I

)

400

ppm

amb

operating ambient
temperature

+85

tot

total power dissipation

= 5 V at code 0000H

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (see Fig.3a) transistor M1 is connected as a diode
by applying a reference current. The voltage V

on the

intrinsic gate-source capacitance C

of M1 is then

determined by the transistor characteristics. After
calibration of the drain current to the reference value I

REF

the switch S1 is opened and S2 is switched to the other
position (see Fig.3b). The gate-to-source voltage V

M1 is not changed because the charge on C

preserved. Therefore, the drain current of M1 will still be
equal to I

REF

and this exact duplicate of I

REF

is now

available at the OUT terminal.

The 32 current sources and the spare current source of the
TDA1311A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors.

A symmetrical offset decoding principle is incorporated
that arranges the bit switching in such a way that the
zero-crossing is performed only by switching the LSB
currents.

The TDA1311A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs 4
and 5.

With a HIGH level on the word select input (WS), data is
placed in the left input register and with a LOW level on the
WS input, data is placed in the right input register (see
Fig.1). The data in the input registers are simultaneously
latched in the output registers which control the bit
switches.

An internal offset voltage V

is added to the full scale

output voltage V

; V

and V

are proportional to V

DD1

DD2

= V

FS1

FS2

= V

OS1

OS2

Fig.3 Calibration principle.

handbook, full pagewidth

MBG860

out

Cgs

Vgs

Cgs

Vgs

out

Iref

(a)

(b)

(a) = calibration.

(b) = operation.

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: C = 100 pF, R = 1500

, 3 pulses positive and 3 pulses negative.

2. Machine model: C = 200 pF, L = 0.5

H, R = 10

, 3 pulses positive and 3 pulses negative.

THERMAL RESISTANCE

QUALITY SPECIFICATION

In accordance with SNW-FQ-0611.

CHARACTERISTICS

= 5 V; T

amb

= 25

C; measured in Fig.1; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

6.0

stg

storage temperature

+150

XTAL

maximum crystal temperature

+150

amb

operating ambient temperature

+85

electrostatic handling

note 1

2000

+2000

note 2

200

+200

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

DIL8

100

K/W

SO8

210

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

4.0

5.0

5.5

supply current

at code 0000H

3.4

6.0

Digital inputs; pins WS, BCK and DATA

input leakage current LOW

= 0.8 V

input leakage current HIGH

= 2.4 V

BCK

clock frequency

18.4

MHz

bit rate data input

18.4

Mbits/s

word select input frequency

384

kHz

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

Note

1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.

Timing (see Fig.4)

rise time

fall time

bit clock cycle time

BCKH

bit clock pulse width HIGH

BCKL

bit clock pulse width LOW

SU;DAT

data set-up time

HD:DAT

data hold time to bit clock

HD:WS

word select hold time

SU;WS

word select set-up time

Analog outputs; pins V

and V

full-scale voltage

1.8

2.0

2.2

full-scale temperature
coefficient

400

ppm

offset voltage

= V

OL/ORmax

0.45

0.50

0.55

(THD+N)/S

total harmonic distortion plus
noise

at 0 dB signal level; note 1

0.04

0.07

60 dB signal level; note 1

60 dB signal level;

A-weighted; note 1

at 0 dB signal level; f = 20 Hz
to 20 kHz

0.05

0.09

current settling time to

1 LSB

0.2

channel separation

unbalance between outputs

note 1

0.2

0.3

time delay between outputs

0.2

S/N

signal-to-noise ratio at
bipolar zero

A-weighted at code 0000H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

APPLICATION INFORMATION

Basic application example

A typical example of a CD-application with the TDA1311A; AT is shown in Fig.6. It features typical decoupling
components and a third-order analog post-filter stage providing a line output.

Fig.6 Example of a 3rd order filter application.

handbook, full pagewidth

100 pF

22 k

420 pF

22 k

2.2 nF

TDA1311A

TDA1311AT

BCK

DATA

100 pF

22 k

420 pF

22 k

2.2 nF

100

VDD

MBG863

Attention to printed circuit board layout

The TDA1311A and even more so the TDA1311AT offers
great ease in designing-in to printed-circuit boards due to
its small size and low pin count. The TDA1311A; AT being
a mixed-signal IC in CMOS, some attention needs to be
paid to layout and topology of the application PCB.
Following some basic rules will yield the desired
performance. The most important considerations are:

1. Supply: care should be taken to supply the

TDA1311A; AT with a clean, noiseless V

, for a good

noise performance of the analog parts of the DAC.
Supply purity can easily be achieved by using an
RC-filtered supply.

2. Grounding: preferably a ground plane should be used,

in order to have a low-impedance return available at
any point in the layout. It is advantageous to make a
partitioning of the ground plane according to the nature
of the expected return currents (digital input returns
separate from supply returns and separate from the
analog section).

3. Topology: the capacitor decoupling high-frequency

supply interference from V

to GND should be placed

as close as is physically possible to the IC body,
ensuring a low-inductance path to ground. The digital
input conductors may be shielded by ground leads
running alongside. The placement of a passive ground
plane underside the entire IC surface gives `free`
additional decoupling from the IC body to ground as
well as providing a shield between the digital input pins
and the analog output pins.

Figure 7 shows recommended layouts for printed-circuit
boards for the SO8 and DIL8 versions respectively. Both
layouts use a single-interconnect layer.

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

Evaluation of audio parameters

The following measurement graphs are performed on singular engineering samples; therefore no guarantee of typical
parameter values is implied. Measurement conditions are typical, as stated in the section Characteristics, unless
otherwise indicated. The normal measurement set-up includes a 20 kHz band-limiting filter for bandwidth definition, and
an A-weighting filter where indicated.

Fig.15 Total harmonic distortion plus noise as a function of signal level (4FS).

handbook, halfpage

100

THD

(dB)

signal level (dB)

100

MBG871

Fig.16 Total harmonic distortion plus noises as a function of frequency (4FS).

(1) Measured including all distortion plus noise at a signal level of

60 dB.

(2) Measured including all distortion plus noise at a signal level of 0 dB.

handbook, halfpage

MBG873

frequency (Hz)

THD

(dB)

THD

(%)

0.1

0.01

0.001

100

(1)

(2)

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

UNIT

max.

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

1.75

0.25
0.10

1.45
1.25

0.25

0.49
0.36

0.25
0.19

5.0
4.8

4.0
3.8

1.27

6.2
5.8

1.05

0.7
0.6

0.7
0.3

8
0

0.25

0.1

0.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.0
0.4

SOT96-1

detail X

(A )

pin 1 index

076E03S

MS-012AA

0.069

0.010
0.004

0.057
0.049

0.01

0.019
0.014

0.0100
0.0075

0.20
0.19

0.16
0.15

0.050

0.244
0.228

0.028
0.024

0.028
0.012

0.01

0.041

0.004

0.039
0.016

2.5

5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

95-02-04
97-05-22

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

DIP

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

EFLOW SOLDERING

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1995 Dec 18

Philips Semiconductors

Preliminary specification

Stereo Continuous Calibration DAC
(CC-DAC)

TDA1311A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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SCD47

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

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other industrial or intellectual property rights.

Printed in The Netherlands

513061/50/02/pp20

Date of release: 1995 Dec 18

Document order number:

9397 750 00532

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA1311A/N2

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA1311A/N2