Document Outline
- FEATURES
- GENERAL DESCRIPTION
- ORDERING INFORMATION
- QUICK REFERENCE DATA
- PINNING
- FUNCTIONAL DESCRIPTION
- LIMITING VALUES
- THERMAL RESISTANCE
- CHARACTERISTICS
- PACKAGE OUTLINES
- SOLDERING
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
DATA SHEET
Preliminary specification
File under Integrated Circuits, IC01
July 1993
INTEGRATED CIRCUITS
TDA1312A; TDA1312AT
Stereo continuous calibration
DAC (CC-DAC)
July 1993
2
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
FEATURES
8
oversampling (simultaneous input) possible
Voltage output
Space saving package SO8 or DIL8
Low power consumption
Wide dynamic range (16-bit resolution)
Continuous Calibration (CC) concept
Easy application:
single 4 to 5.5 V rail supply
output current and bias current are proportional to the
supply voltage
integrated current-to-voltage converter
Internal bias current ensures maximum dynamic range
Wide operating temperature range (
-
40
C to
+
85
C)
Compatible with most current Japanese input formats:
time multiplexed, two's complement and TTL
No zero-crossing distortion
Cost efficient.
GENERAL DESCRIPTION
The TDA1312A; 1312AT is a voltage driven D/A converter
and is a device of a new generation of digital-to-analog
converters which embodies the innovative technique of
Continuous Calibration (CC). The largest bit-currents are
repeatedly generated by one single current reference
source. This duplication is based upon an internal charge
storage principle having an accuracy insensitive to ageing,
temperature matching and process variations.
The TDA1312A; 1312AT is fabricated in a 1.0
m CMOS
process and features an extremely low power dissipation,
small package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
preclude zero-crossing distortion and ensures high quality
audio reproduction. Therefore, the CC-DAC is eminently
suitable for use in (portable) digital audio equipment.
ORDERING INFORMATION
Notes
1. SOT97-1; 1996 August 14.
2. SOT96-1; 1996 August 14.
EXTENDED TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
TDA1312A
(1)
8
DIL
plastic
SOT97DE
TDA1312AT
(2)
8
SO8
plastic
SOT96AG
July 1993
3
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
4
5
5.5
V
I
DD
supply current
V
DD
= 5 V; at code 0000H
-
3.4
6.0
mA
V
FS
full scale output voltage
V
DD
= 5 V
1.8
2.0
2.2
V
(THD
+
N)/S
total harmonic distortion plus
noise
at 0 dB signal level
-
-
68
-
63
dB
-
0.04
0.07
%
at
-
60 dB signal level
-
-
30
-
24
dB
-
3
6
%
at
-
60 dB signal level;
A-weighted
-
-
33
-
dB
-
2
-
%
S/N
signal-to-noise ratio at
bipolar zero
A-weighted; at code 0000H
86
92
-
dB
t
CS
current settling time to
1
LSB
-
0.2
-
s
BR
input bit rate at data input
-
-
18.4
Mbits/s
f
BCK
clock frequency at clock
input
-
-
18.4
MHz
TC
FS
full scale temperature
coefficient at analog
outputs (I
OL
; I
OR
)
-
400
-
ppm
T
amb
operating ambient
temperature
-
40
-
+
85
C
P
tot
total power dissipation
V
DD
= 5 V; at code 0000H
-
17
30
mW
July 1993
4
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312A
T
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Fig.1 Block diagram.
handbook, full pagewidth
MGE225
32 (5-BIT)
CALIBRATED
CURRENT
SOURCES
1 CALIBRATED
SPARE SOURCE
11-BIT
PASSIVE
DIVIDER
LEFT BIT SWITCHES
LEFT INPUT REGISTER
LEFT OUTPUT REGISTER
RIGHT BIT SWITCHES
RIGHT INPUT REGISTER
RIGHT OUTPUT REGISTER
7
32 (5-BIT)
CALIBRATED
CURRENT
SOURCES
1 CALIBRATED
SPARE SOURCE
11-BIT
PASSIVE
DIVIDER
I / V
REFERENCE
SOURCE
CONTROL
AND
TIMING
1
2
3
8
5
4
C2
100 nF
VDD
IOR
GND
TDA1312A
TDA1312AT
BCK
WS
DATAR
DATAL
IOL
VOR
6
I / V
VOL
July 1993
5
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
PINNING
SYMBOL
PIN
DESCRIPTION
BCK
1
bit clock input
DATAR
2
right data input
DATAL
3
left data input
GND
4
ground
V
DD
5
positive supply voltage
V
OL
6
left channel output
V
OR
7
right channel output
WS
8
word select input
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
8
7
6
5
MGE224
TDA1312
TDA1312AT
WS
VOR
DATAR
VOL
VDD
GND
DATAL
BCK
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage V
gs
on the
intrinsic gate-source capacitance C
gs
of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
ref
,
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage V
gs
of M1 is
not changed because the charge on C
gs
is preserved.
Therefore, the drain current of M1 will still be equal to I
REF
and this exact duplicate of I
REF
is now available at the OUT
terminal.
The 32 current sources and the spare current source of the
TDA1312A; AT are continuously calibrated (see Fig.1).
The spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The TDA1312A; AT (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in Figs.4
and 5.
Data is placed in the right and left input registers (see
Fig.1). The data in the input registers is simultaneously
latched in the output registers which control the bit
switches.
An internal offset voltage V
OFF
is added to the full scale
output voltage V
FS
; V
OFF
and V
FS
are proportional to V
DD
:
Where V
DD1
/V
DD2
= V
FS1
/V
FS2
= V
OFF1
/V
OFF2
.
July 1993
6
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Human body model: C = 100 pF; R = 1500
; 3 zaps positive and negative.
2. Machine model: C = 200 pF; L = 0.5
H; R = 10
; 3 zaps positive and negative.
THERMAL RESISTANCE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
supply voltage
-
6.0
V
T
stg
storage temperature
-
55
+
150
C
T
XTAL
maximum crystal temperature
-
+
150
C
T
amb
operating ambient temperature
-
40
+
85
C
V
es
electrostatic handling
note 1
-
2000
+
2000
V
note 2
-
200
+
200
V
SYMBOL
PARAMETER
THERMAL RESISTANCE
R
th j-a
from junction to ambient in free air
DIL8
100 K/W
SO8
210 K/W
Fig.3 Calibration principle; (a) calibration (b) operation.
handbook, halfpage
MGE226
Cgs
S1
M1
(a)
(b)
Vgs
S2
IREF
OUT
+
Cgs
S1
M1
Vgs
S2
IREF
IREF
OUT
+
July 1993
7
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
CHARACTERISTICS
V
DD
= 5 V; T
amb
= 25
C; measured in Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
positive supply voltage
4.0
5.0
5.5
V
I
DD
supply current
at code 0000H
-
3.4
6.0
mA
Digital inputs; pins WS, BCK and DATA
I
IL
input leakage current LOW
V
I
= 0 V
-
-
10
A
I
IH
input leakage current HIGH
V
I
= 5 V
-
-
10
A
f
BCK
clock frequency
-
-
18.4
MHz
BR
bit rate data input
-
-
18.4
Mbits/s
f
WS
word select input frequency
-
-
384
kHz
Timing (see Fig.4)
t
r
rise time
-
-
12
ns
t
f
fall time
-
-
12
ns
t
CY
bit clock cycle time
54
-
-
ns
t
BCKH
bit clock pulse width HIGH
15
-
-
ns
t
BCKL
bit clock pulse width LOW
15
-
-
ns
t
SU;DAT
data set-up time
12
-
-
ns
t
HD:DAT
data hold time to bit clock
2
-
-
ns
t
HD:WS
word select hold time
2
-
-
ns
t
SU;WS
word select set-up time
12
-
-
ns
Analog outputs; pins V
OL
and V
OR
V
FS
full-scale voltage
1.8
2.0
2.2
V
TC
FS
full-scale temperature coefficient
-
400
-
ppm
V
OFF
offset voltage
at code 1000H
0.42
0.47
0.52
V
(THD+N)/S
total harmonic distortion plus noise
at 0 dB signal level;
note 1
-
-
68
-
63
dB
-
0.04
0.07
%
at
-
60 dB signal level;
note 1
-
-
30
-
24
dB
-
3
6
%
at
-
60 dB signal level;
A-weighted; note1
-
-
33
-
dB
-
2
-
%
at 0 dB signal level;
f = 20 Hz to 20 kHz
-
-
65
-
61
dB
-
0.05
0.09
%
July 1993
8
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
Note
1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.
Analog outputs; pins V
OL
and V
OR
t
cs
current settling time to
1 LSB
-
0.2
-
s
channel separation
75
80
-
dB
I
O
unbalance between outputs
note 1
-
0.2
0.3
dB
t
d
time delay between outputs
-
0.2
-
s
S/N
signal-to-noise ratio at bipolar zero
A-weighted;
at code 0000H
86
92
-
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.4 Input signals timing.
handbook, full pagewidth
MGE227
tCY
>
54
SAMPLE OUT
MSB
LSB
DATAR
DATAL
BCK
WS
RIGHT
LEFT
tf
<
12
tr
<
12
tBCKL
>
15
tBCKH
>
15
tHD; WS
>
2
tSU; DAT
>
12
tHD; DAT
>
2
tSU; WS
>
12
July 1993
9
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312A
T
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
handbook, full pagewidth
MGE228
DATAR
DATAL
BCK
WS
MSB
LSB
SAMPLE OUT
Fig.5 Input signals format.
July 1993
10
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
PACKAGE OUTLINES
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT97-1
92-11-17
95-02-04
UNIT
A
max.
1
2
b
1
(1)
(1)
(1)
b
2
c
D
E
e
M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.14
0.53
0.38
0.36
0.23
9.8
9.2
6.48
6.20
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
1.15
4.2
0.51
3.2
inches
0.068
0.045
0.021
0.015
0.014
0.009
1.07
0.89
0.042
0.035
0.39
0.36
0.26
0.24
0.14
0.12
0.01
0.10
0.30
0.32
0.31
0.39
0.33
0.045
0.17
0.020
0.13
b
2
050G01
MO-001AN
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
8
1
5
4
b
E
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
pin 1 index
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
July 1993
11
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(2)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S
MS-012AA
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.01
0.041
0.004
0.039
0.016
0
2.5
5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
95-02-04
97-05-22
July 1993
12
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300
C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400
C, contact may be up to 5 seconds.
SO
R
EFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
W
AVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The longitudinal axis of the package footprint must be
parallel to the solder flow.
The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
July 1993
13
Philips Semiconductors
Preliminary specification
Stereo continuous calibration
DAC (CC-DAC)
TDA1312A; TDA1312AT
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
PDF 
ZIP