Document Outline
- FEATURES
- GENERAL DESCRIPTION
- ORDERING INFORMATION
- QUICK REFERENCE DATA
- BLOCK DIAGRAM
- PINNING
- FUNCTIONAL DESCRIPTION
- Modes of operation
- General
- LIMITING VALUES
- HANDLING
- THERMAL CHARACTERISTICS
- CHARACTERISTICS
- TEST AND APPLICATION INFORMATION
- Test information
- Stand alone application (receive only)
- Microcontroller based application (receive and/or transmit)
- Transmit mode only application (also possible without microcontroller)
- PACKAGE OUTLINE
- SOLDERING QFP
- Introduction
- Reflow soldering
- Wave soldering
- Repairing soldered joints
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
DATA SHEET
Product specification
Supersedes data of December 1994
File under Integrated Circuits, IC01
1995 Jul 17
INTEGRATED CIRCUITS
TDA1315H
Digital audio input/output circuit
(DAIO)
1995 Jul 17
2
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
FEATURES
Transceiver for SPDIF and
"IEC 958" encoded signals
High sensitivity input for transformer-coupled links
TTL-level input for optical links
Built-in IEC input selector
Built-in IEC feed-through function
Automatic sample frequency (f
s
) detection
System clock recovery from IEC input signal
Low system clock drift when IEC input signal is removed
Error detection and concealment
PLL lock detection in transmit mode
Serial audio interface conforms to I
2
S-bus format
Auxiliary I
2
S-bus input for Analog-to-Digital Converter
(ADC)
Audio output selector
Microcontroller-controlled and stand-alone mode
128-byte buffer for user data
Bytewise exchange of user data with microcontroller
Decoding of Compact Disc (CD) subcode Q-channel
data
Support for serial copy management system (SCMS)
Light Emitting Diode (LED) drive capability
(sample frequency and error indication)
Pin-selectable device address for
microcontroller interface
Power-down mode.
GENERAL DESCRIPTION
The Digital Audio Input/Output circuit (DAIO) of the
TDA1315H is a complete transceiver for biphase-mark
encoded digital audio signals that conform to the SPDIF
and
"IEC 958" interface standards (consumer mode),
made in the full CMOS-process C200.
In the receive mode, the device adjusts automatically to
one of the three standardized sample frequencies
(32, 44.1 or 48 kHz), decodes the input signal and
separates audio and control data. A clock signal of either
256 or 384 times the sample frequency is generated to
serve as a master clock signal in digital audio systems.
In the transmit mode, the device multiplexes the audio
control and user data and encodes it for subsequent
transmission via a cable or optical link.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
PIN POSITION
VERSION
TDA1315H
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
10
1.75 mm
SOT307-2
1995 Jul 17
3
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
QUICK REFERENCE DATA
All inputs are TTL compatible; all outputs are CMOS compatible; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
supply voltage
V
DDD
= V
DDA
3.4
5.0
5.5
V
I
DDAq
analog quiescent current
PD = 1; T
amb
= 25
C
-
-
10
A
I
DDDq
digital quiescent current
PD = 1; T
amb
= 25
C
-
-
10
A
I
DDA
analog supply current
f
s
= 48 kHz; CLKSEL = 0;
when IECIN1 input is used
-
2.6
-
mA
I
DDD
digital supply current
f
s
= 48 kHz; CLKSEL = 0
-
13
-
mA
Power
P
tot
total power dissipation
f
s
= 48 kHz; CLKSEL = 0;
when IECIN1 input is used
-
80
-
mW
Temperature
T
amb
operating ambient temperature
-
20
-
+70
C
IEC interface; pin IECIN1 (high sensitivity IEC input)
V
i(p-p)
AC input voltage
(peak-to-peak value)
0.2
-
V
DD
V
Control part
CHMODE, UNLOCK, FS32, FS44, FS48
AND
COPY (
OPEN
-
DRAIN OUTPUTS
)
V
OL
LOW level output voltage
I
OL
= 3 mA
-
-
0.5
V
RESET, SCK, LCLK, LMODE
AND
SYSCLKI (
HYSTERESIS INPUTS
)
V
tHL
negative-going threshold
V
DD
= 4.5 to 5.5 V
0.6
-
-
V
V
tLH
positive-going threshold
V
DD
= 4.5 to 5.5 V
-
-
2.4
V
V
hys
input voltage hysteresis
V
DD
= 4.5 to 5.5 V
-
0.7
-
V
Clock and timing
V
ref
output reference voltage
-
2.1
-
V
RC
int
(
PIN
44)
I
CHfr
charge-pump output current
frequency detector loop
-
12
-
A
I
CHph
charge-pump output current
phase detector loop
-
24
-
A
1995 Jul 17
4
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
BLOCK DIAGRAM
Fig.1 Block diagram.
1995 Jul 17
5
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
PINNING
SYMBOL
PIN
PADCELL
DESCRIPTION
RC
fil
1
E029
PLL loop filter input
V
ref
2
E029
decoupling internal reference voltage output
V
DDA
3
E008
analog supply voltage
V
SSA
4
E004
analog ground
IECIN1
5
E007
high sensitivity IEC input
IECIN0
6
IPP04
TTL level IEC input
IECSEL
7
IUP04
select IEC input 0 or 1 (0 = IECIN0; 1 = IECIN1); this input has an internal pull-up
resistor
IECO
8
OPFH3
digital audio output for optical and transformer link
IECOEN
9
IUP04
digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
internal pull-up resistor
TESTB
10
IPP04
enable factory test input (0 = normal application; 1 = scan mode)
TESTC
11
IPP04
enable factory test input (0 = normal application; 1 = observation outputs)
UNLOCK
12
OPP41A
PLL out-of-lock (0 = not locked; 1 = locked); this output can drive an LED
FS32
13
OPP41A
indicates sample frequency = 32 kHz (active LOW); this output can drive an LED
FS44
14
OPP41A
indicates sample frequency = 44.1 kHz (active LOW); this output can drive an LED
FS48
15
OPP41A
indicates sample frequency = 48 kHz (active LOW); this output can drive an LED
CHMODE
16
OPP41A
use of channel status block (0 = professional use; 1 = consumer use); this output
can drive an LED
V
DDD2
17
E008
digital supply voltage 2
V
SSD2
18
E009
digital ground 2
RESET
19
IDP09
initialization after power-on, requires only an external capacitor connected to V
DDD
;
this is a Schmitt-trigger input with an internal pull-down resistor
PD
20
IPP04
enable power-down input in the standby mode (0 = normal application; 1 = standby
mode)
CTRLMODE
21
IUP04
select microcontroller/stand-alone mode (0 = microcontroller; 1 = stand-alone); this
input has an internal pull-up resistor
LADDR
22
IPP04
microcontroller interface address switch input (0 = 000001; 1 = 000010)
LMODE
23
IPP09
microcontroller interface mode line input
LCLK
24
IPP09
microcontroller interface clock line input
LDATA
25
IOF24
microcontroller interface data line input/output
STROBE
26
IDP04
strobe for control register (active HIGH); this input has an internal pull-down resistor
UDAVAIL
27
OPF23
synchronization for output user data (0 = data available; 1 = no data)
TESTA
28
IPP04
enable factory (scan) test input (0 = normal application; 1 = test clock enable)
COPY
29
OPP41A
copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output
can drive an LED
INVALID
30
IOD24
validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin
has an internal pull-down resistor
DEEM
31
OPF23
pre-emphasis output bit (0 = no pre-emphasis; 1 = pre-emphasis)
MUTE
32
IUP04
audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an
internal pull-up resistor
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