1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

FEATURES

Adjustment-free voltage controlled PLL oscillator for
ceramic resonator (f = 456 kHz)

Pilot signal dependent mono/stereo switching

Analog control of mono/stereo change over
[stereo blend, Stereo Noise Controller (SNC)]

Adjacent channel noise suppression (114 kHz)

Pilot canceller

Analog control of de-emphasis; High Cut Control (HCC)

Reduced and controlled de-emphasis for AM operation
(pin 7 to GND)

Applicable as source selector for AM/FM/cassette
switching

Soft mute for silent tuning

Separate interference noise detector

Integrated input low-pass filter for delayed noise
blanking

Noise blanking at MPX-demodulator outputs.

GENERAL DESCRIPTION

The TDA1592 is a monolithic bipolar integrated circuit
providing the stereo decoder function and noise blanking
for FM car radio applications.

The device operates in a power supply range of
7.5 to 12 V.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage (pin 5)

7.5

supply current

o(rms)

audio output signal (RMS value)

800

900

1000

THD

total harmonic distortion

0.1

0.3

S/N

signal-to-noise ratio

channel separation

trigg

interference voltage trigger level

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA1592

DIP20

plastic dual in-line package; 20 leads (300 mil)

SOT146-1

TDA1592T

SO20

plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

PINNING

SYMBOL

PIN

DESCRIPTION

PLL

phase locked loop filter

OSC

oscillator input/output pin for
ceramic resonator

GND

ground (0 V)

ref

reference current

supply voltage (+10 V)

INFI

interference signal input

PUFO

pulse former time constant; VCO
off

NDET

noise detector time constant; mute
on

FB-L

AF feedback input for left audio
signal

AF output signal left

AF output signal right

FB-R

AF feedback input for right audio
signal

DEEL

de-emphasis capacitor for left
channel

DEER

de-emphasis capacitor for right
channel

HCC

HCC input for de-emphasis control

SNC

stereo blend input

ref

externally applied reference
voltage of 1 to 5 V

IDENT

identification output (HIGH = pilot
existing; stereo)

PILOT

pilot detector level (forced mono
input)

i MPX

MPX input signal from IF
demodulator

Fig.2 Pin configuration.

handbook, halfpage

PLL

OSC

GND

Iref

INFI

PUFO

NDET

FB-L

VoL

Vi MPX

PILOT

IDENT

Vref

HCC

CDEER

SNC

CDEEL

FB-R

VoR

TDA1592

MED726

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

FUNCTIONAL DESCRIPTION

The MPX input of the TDA1592 (pin 20) is the null-node of
an operational amplifier with internal feedback resistor.
Adapting the stereo decoder input to the level of the FM
demodulator output is realized by the value of input
resistor R

(see Fig.3). The total gain of the stereo

decoder is applicable by varying the feedback resistors
R

out

(pins 9, 10, 11 and 12) of the output operational

amplifiers (see Fig.4).

The input amplifier is followed by an integrated 4

order

Bessel low-pass filter with a cut-off frequency of 80 kHz.
It provides necessary signal delay for noise blanking and
damping of high frequency interferences at the stereo
decoder input.

The soft mute facility (pin 8) provides silent tuning for RDS
processing. The mute time constant may be adjusted from
pin 8. In mute position and the VCO switched off (pin 7),
the output amplifiers can be used for cassette playback,
AM stereo purpose or other signal sources.

The voltage to current converted MPX signal is fed to
phase detector, pilot detector and pilot canceller circuits.
The oscillator is alignment-free with an external ceramic
resonator at 456 kHz as reference (pin 2). The required
19 kHz and 38 kHz signals are generated by division of the
oscillator output signal in a logical circuit. For regeneration
of the 38 kHz subcarrier, a PLL is used. The 19 kHz
quadrature phase signal is fed to the 19 kHz
phase detector, where it is compared with the incoming
pilot tone. The DC output signal of the phase detector
(pin 1) controls the oscillator (PLL).

The pilot presence detector is driven by internally
generated in-phase 19 kHz. Its pilot-dependent DC output
voltage (pin 19) is fed to a threshold switch, which
activates the pilot indicator logic output (pin 18) and turns
the stereo decoder to stereo operation. The same
DC voltage is used to control the amplitude of an
anti-phase internally generated 19 kHz signal. In the
pilot canceller, the pilot tone is compensated by this
anti-phase 19 kHz signal.

The pilot cancelled signal is fed to the multiplex decoder.
There, the side signal is demodulated and combined with
the main signal in a matrix to left and right audio channel.

Compensation for roll-off in the incoming MPX signal
caused by IF filters and FM demodulator is realized by
corresponding side signal amplification.

A smooth mono to stereo take-over, which is controlled by
the level detector voltage of the IF part, is achieved by the
SNC (pins 16 and 17; see Fig.6).

From the output of the MPX demodulator the signals are
fed to 2-pole low-pass filters with a cut-off frequency of
30 kHz to provide additional signal delay for noise blanking
and attenuation of the subcarrier and its harmonics.

These filters are followed by the noise suppression gates,
which are combined with de-emphasis and HCC. The
de-emphasis is defined by internal resistors (aligned by an
external current) and external capacitors (pins 13 and 14).
For HCC, the de-emphasis time constant can be changed
to higher values (pins 15 and 17; see Figs 7 to 9). This
function is controlled by an analog input signal, derived
from the level detector voltage of the IF part. When the
VCO is turned off (pin 7 to GND), de-emphasis is reduced
to 20

s for full frequency response when AM-AF is fed

through the stereo decoder. De-emphasis remains
controllable.

From the gate circuits audio is fed through internal series
resistors to the inverting inputs of the output operational
amplifiers (pins 9 and 12), which can also be used as
signal inputs for cassette playback or other sources when
the mute is activated. The gain of these amplifiers is
defined by external feedback resistors R

out

(pins 9, 10, 11 and 12).

The input of the ignition noise blanker is the null node of an
operational amplifier (pin 6). It can be driven by the level
detector output of the FM-IF limiter and/or the MPX signal.
Its sensitivity is dependent on the value of the series input
resistor at pin 6.

The operational amplifier output signal is fed through an
integrated 120 kHz high-pass filter, becomes amplified
and is then fed in parallel to the noise detector and the
interference detector. The noise detector is a negative
peak detector. Its output (pin 8) controls the trigger
sensitivity (prevention to false triggering at noisy input
signals) and the attenuation of the input operational
amplifier. The output of the interference detector, when
receiving a steep pulse, triggers a mono flip-flop, which is
a part of the pulse former circuit. The time constant of the
mono flip-flop is defined by an external capacitor (pin 7)
and its output activates the blanking gates in the audio.

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Equivalent to discharging a 200 pF capacitor through a 0

series resistor.

CHARACTERISTICS
V

= 10 V; T

amb

= 25

C; input signal V

i MPX(p-p)

= 1.7 V; m = 100% (

f =

75 kHz, f

mod

= 1 kHz); de-emphasis of 50

and series resistor at input R

= 164 k

; measurements taken in Fig.1; unless otherwise specified.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage (pin 5)

13.2

tot

total power dissipation

0.25

stg

storage temperature

+150

amb

operating ambient temperature

+85

electrostatic handling for all pins; note 1

400

+400

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage (pin 5)

7.5

supply current

Stereo decoder

i MPX(p-p)

MPX input signal

1.7

i MPX(p-p)

overdrive margin of MPX input signal

THD = 1%

o(rms)

AF mono output signal at pins 10 and 11
(RMS value)

without pilot

800

900

1000

overdrive margin of output signal

THD = 1%

10-11

difference of output voltage levels

o 10,11

DC output voltage (pins 10 and 11)

3.2

3.7

4.2

o 10,11

output resistance

150

output current

330

400

2,3

maximum feedback resistor

4,3

reference voltage

3.7

3.8

3.9

channel separation

pin 16 open-circuit;
see Fig.6

THD

total harmonic distortion

0.1

0.3

S/N

signal-to-noise ratio

f = 20 to 16000 Hz

pilot signal suppression

f = 19 kHz

subcarrier suppression

f = 38 kHz

f = 57 kHz

f = 76 kHz

IM2

intermodulation for f

spur

= 1 kHz

mod

= 10 kHz; note 1

IM3

mod

= 13 kHz

57 VF

traffic radio (VWF)

f = 57 kHz; note 2

SCA (Subsidiary Communications
Authorization)

f = 67 kHz; note 3

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

114

ACI (Adjacent Channel Interference)

f = 114 kHz; note 4

190

f = 190 kHz; note 4

PSRR

power supply ripple rejection

f = 100 Hz;
V

ripple (rms)

= 100 mV

VCO (pin 2)

osc

oscillator frequency (ceramic resonator)

456

kHz

frequency range of free running oscillator

451

459

kHz

f/f

capture and holding range

0.65

VCO-off voltage (pin 7)

0.6

Mono/stereo control (pins 16, 17 and 19)

i pilot

pilot threshold voltage for automatic switching
by pilot input voltage (RMS value)

stereo on

stereo off

HYS

hysteresis of pilot threshold voltage

switching voltage for external mono control
(pin 19)

0.7

ref

reference input voltage range (pin 17)

16-17

control voltage for channel separation due to
pin 17 (V

ref

)

= 6 dB; see Fig.5

100

120

= 20 dB; see Fig.5

Pilot indicator logic level output (pin 18)

LOW voltage

= 500

250

400

HIGH current

= 10 V

Muting (pin 8)

MUTE

att

mute attenuation (pin 8)

< 1.6 V

> 4 V

0.2

o(offset)

DC offset voltage (pins 10 and 11)

after muting

HCC (pin 15)

deem

control range of de-emphasis

see Figs 7 and 8

for European standard

deem

= 6.8 nF

150

for USA standard

deem

= 10 nF

225

15-17

control voltage (pin 15 due to pin 17) in both
standards

lower value CR

deem

upper value CR

deem

300

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

Notes

1. Intermodulation suppression [Beat Frequency Components (BFC)]:

;

measured with 91% mono signal; f

mod

= 10 kHz or 13 kHz; 9% pilot signal.

2. ARI suppression:

measured with 91% stereo signal; f

mod

= 1 kHz; 9% pilot signal; 5% ARI subcarrier

= 57 kHz; f

mod

= 23 Hz; AM m = 0.6).

3. Subsidiary Communication Authorization (SCA):

;

measured with 81% mono signal; f

mod

= 1 kHz; 9% pilot signal; 10% SCA subcarrier (f

= 67 kHz, unmodulated).

4. Adjacent Channel Interference (ACI):

;

measured with 90% mono signal; f

mod

= 1 kHz; 9% pilot signal; 1% spurious signal

= 110 kHz or 186 kHz, unmodulated).

HCC (pin 15, pin 7 to GND)

deem

control range of de-emphasis

see Fig.9

for European standard

deem

= 6.8 nF

for USA standard

deem

= 10 nF

135

15-17

control voltage (pin 15 due to pin 17) in both
standards

lower value CR

deem

upper value CR

deem

300

DC offset voltage at AF outputs (AM on/off)

200

Noise interference detector

pulse

trigger sensitivity

pulse

= 10

trigger threshold voltage offset as a function of
V

trigg

int

= 120 kHz

interf.in

= 10 mV

150

200

250

interf.in

= 100 mV

550

650

750

sup

AF suppression time; pulse width

13,14

input offset current (pins 13 and 14)

during AF suppression
time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

IM2

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

(

)

--------------------------------------------------------

10 kHz

(

)

19 kHz

IM3

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

(

)

--------------------------------------------------------

13 kHz

(

)

38 kHz

ARI

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

23 Hz

(

)

-----------------------------------------------------------------------------

o(signal)

at 1 kHz

(

)

o(spurious)

at 9 kHz

(

)

--------------------------------------------------------

38 kHz

(

)

67 kHz

114

o(signal)

at 1 kHz

(

)

o(spurious)

at 4 kHz

(

)

--------------------------------------------------------

110 kHz

38 kHz

(

)

190

o(signal)

at 1 kHz

(

)

o(spurious)

at 4 kHz

(

)

--------------------------------------------------------

186 kHz

38 kHz

(

)

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

DIP

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

EFLOW SOLDERING

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1996 May 31

Philips Semiconductors

Preliminary specification

PLL stereo decoder and noise blanker

TDA1592

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com/ps/

(1)

ADDRESS CONTENT SOURCE May 31, 1996

Philips Semiconductors a worldwide company

SCA49

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Printed in The Netherlands

517021/1200/02/pp20

Date of release: 1996 May 31

Document order number:

9397 750 00875

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